JPS5828787B2 - Saidaichi Count Souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a maximum value counting device, and in particular, by incorporating a non-volatile memory element inside the counter, both the contents of the count and the contents of the maximum value are lost even when the power is turned off. Concerning maximum value counters without.

Conventional maximum value counting devices provide the same device or a latch separately from the counter body, and exclude these.
They are mainly configured by connecting gates such as sive OR circuits, but MOS type counters are used when high-speed counting is required, and MOS type counters are used to store the maximum value in a non-volatile manner. An electromagnetic counter in which a memory element is connected to the outside of the counter is used.

In this way, conventional maximum value counting devices do not have a device that stores the maximum value in a non-volatile manner within the counter body; for example, in the case of a counter using a MOS transistor, a non-volatile storage element is connected externally. must be activated simultaneously by

However, if the aforementioned electromagnetic counter is used as this memory element, the counting frequency of the counter itself is suppressed by this electromagnetic counter, making it difficult to increase the speed.

Furthermore, since the above-mentioned latch type requires a parallel signal to transfer the maximum value, an output terminal from the counter is provided for each bit.

Therefore, it becomes difficult to integrate this counter as the number of bits increases.

The present invention was made to eliminate the drawbacks of conventional maximum value counting devices, and even if the power is cut off in a single-chip integrated circuit, the contents of the count and the contents of the maximum value set at that time are both retained. It is an object of the present invention to provide a maximum value counting device which is retained without being lost and in which the counting speed of the counter itself is not restricted by the speed of a non-volatile retaining element.

A further object of the present invention is to provide a maximum value counting device that does not require an external logic circuit by adding a nonvolatile memory function and a comparison function to the latch function provided inside the counter.

The present invention will be explained in detail below with reference to the drawings.

The present invention is based on the provision of a nonvolatile semiconductor memory capable of performing storage operations inside the counter.

A counter having a non-volatile semiconductor memory is described in detail in Japanese Patent Application No. 109005/1985, which was previously filed by the applicant, but this will be briefly explained using FIG. 1.

Figure 1 shows the basic configuration of the nonvolatile counter circuit2.
This shows the circuit configuration for one bit of the decimal bit.

MT12 and MT2 are p-channel MNOS transistors, T1 to T6 are p-channel MOS transistors, and a total of eight elements constitute one bit.

Among the above eight elements, active element T1. T2 is flip-flop switching MO8I-transistor T5+T
6 is a load MOS transistor.

MNOS transistors MT12MT2 are switching MOS transistors T1 p T2 and load MO8I
- inserted between each of the transistors T, , T6;

In addition, MOS transistors T3゜T are connected in parallel to MNO8I and transistors MT12 and MT2 as switching elements.
4 is provided.

Here, the load MOS transistors T5j and T6 are depletion type, and all other MOS transistors are enhancement type.

When a positive erase voltage (for example, +24 mm) is applied to the MNOS trough 32MT12 in the circuit shown in Fig. 1, the gate threshold voltage moves in the positive direction, and a negative write voltage (for example, -24 mm) is applied to the source potential. Then, a device in which the gate threshold voltage moves in the negative direction is used.

Also, in this figure, the signal M is the MNOS transistor MT1.
A control signal for restoring information, erasing information, and writing information in 2MT2, VDD=vss, is a power supply voltage, a signal, or a control signal for operating this nonvolatile counter circuit as a normal counter circuit.

In this circuit, when energizing, signal M turns off MNO8I-transistor MT12MT2, and signal I turns off MNO8I-transistor MT12MT2.
MOS transistors T3 and T4 connected in parallel to the OS transistor are turned on.

Therefore, in this state, this counter operates as a normal MOS flip-flop.

Now, when the M)S transistor T1 is on and the MOS transistor T2 is off, the contents of this flip-flop are MN
Consider the case of writing to an OS transistor.

First, it is assumed that a pulse of about 24 V positive than VSS is applied in advance by the signal M to move the gate thresholds of the MNOS transistor and MT12MT2 in the positive direction and set them to about -2.

In this state, a pulse approximately 24 V more negative than VSS (+12 V), that is, a pulse of -12 V, is applied by signal M.

As a result, the insulating film of the MNOS transistor MT1 has approximately -
A voltage of 24V is applied, and the MNO8I-transistor MT
The gate threshold of 1 moves in the negative direction to about -8■.

On the other hand, the insulating film of the MNOS transistor MT2 has a channel voltage of 16V directly under the gate, so it is approximately -6V.
L is not applied and variations in the gate threshold are prevented.

In this way, the contents of the flip-flop are stored non-volatilely as the gate threshold of the MNOS transistor.

When energized, MOS transistors T3 and T4 are activated as described above.
is operating, but MNO8 stored as above
To read the contents of the I-transistor, first set I to VS.
Set to S level and turn off both MO8h transistors T3t and T4.

When the MOS transistors T3 t T4 are turned off, there is no load on the flip-flop, and only the memory function due to the gate capacitance of the MOS transistors T1 and T2 remains.

The charge due to this capacitance varies depending on the value of the stray capacitance and the size of the gate threshold, but is lost due to leakage current of the pn reverse junction.

When the remaining charge potential becomes almost 0, if a negative voltage is gradually applied from VSS to the signal M, the MNOS transistor with the lower gate threshold (in this case, the MNO
The S transistor MT2 is turned on first.

Therefore, since a negative voltage is applied to the source of the MNO8I transistor MT2 earlier than VDD, the MOS transistor T1 is turned on, the MOS transistor T2 is turned off, and the contents previously stored in the MNOS transistor are read out.

Therefore, by detecting whether the power is on or off and controlling the signals M and φ, the contents of the flip-flop are changed to the MNOS transistor MT1 when the power is turned off.

This memory content can be written to the MT2 and read out when the power is turned on.

The present invention is based on the above principle, and consists of a pair of circuits shown in Fig. 1, one of which is a counter section and the other a latch section, each of which has a 1-bit configuration, and the maximum value is always stored in the latch section. This is how it was done.

FIG. 2 is a circuit diagram showing an embodiment of the maximum value counting device of the present invention.

This figure shows one digit of a decimal counter, which is composed of 4 bits.

A pair of counter circuits shown in FIG. 1 are provided in one bit, with the lower part being a counter part and the upper part being a latch part.

A case in which the counter section in this maximum value counting device advances the count while being cleared at a constant period T as shown in FIG. 3 will be described below.

First, at time t in FIG.

Assume that a certain count number A is latched in the latch section.

It is also assumed that the signal CM applied to the coincidence detection circuit 1 and the signal TR applied to the O1 synchronization control circuit 2 are also O''.

Here, the signal value "0" indicates the VDD level (-6V), and the signal value "1" described later indicates the vss level (+12V).
shows.

When the signal CM applied to the coincidence detection circuit 1 is "O", the MOS transistor T"ta in the coincidence detection circuit 1 is turned on, the signal MAT becomes "ll+", and the MOS transistor T18 in the synchronous control circuit 2 is turned off. .

On the other hand, at this time, the signal TR applied to the synchronous control circuit 2 is “
0'', MO8I-transistor T1□ is turned on.

Therefore, if the signal CM and the signal TR are both 011 in this way, the MOS transistor TIO provided in the latch section is turned off, and the counter section and the latch section are separated.

In this state, when count inputs IN and IN are applied to the counter section, the counter section sequentially increments the count from 0 as shown by the broken line.

However, the latch section is at time t. The count value is maintained as is.

In this way, when both the signal CM and the signal TR are O'', only the counter section operates and the latch section does not operate at all.

This state is hereinafter referred to as "asynchronous."

Next, consider a case where the signal CM is 0'' and the signal TR is 1''.

In this case, transistor T16 is on, transistor T
Since the transistor T18 is turned off and the transistor T17 is turned off, the transistor T1o is turned on.

Therefore, in this state, the count inputs IN and IN are input to the counter section.
When is added, the launch section operates in synchronization with the counter section, and as the counter section counts up, the latch section also counts up.

At this time, if the initial value A is stored in the latch section as described above, the latch section increments the count using A as the initial value.

Hereinafter, this state will be referred to as "synchronization". Next, the signal CM is “1”
When the signal TR is 0'' at '', the transistor T16 is turned off and the transistor T1□ is turned on.

Therefore, if the signal MAT is applied to the gate terminal of the transistor T□ in the match detection circuit 1, No? 1 is input and T1
If T15 is on, it will be "1", and if T15 is off and T15 is off, it will be "0".

When the signal MAT is °1', the transistor T18 in the synchronous control circuit 2 is turned off, and when the signal MAT is "o", the transistor T18 is turned off.
8 turns on.

However, the transistor T1□ in the synchronous control circuit 2 is always on due to the signal TR.

Therefore, the transistor TIO in the latch section is always turned off, separating the latch section and the counter section.

Therefore, this case is "asynchronous".

Finally, consider the case where both the signal CM and the signal TR are 1''.

Since the signal CM is 1'', the transistor T16 in the coincidence detection circuit 1 is off.

Therefore, the signal MAT is the input signal of the transistor T15.
0", "l? When F, n 1j+, it becomes 0''.

Further, since the signal TR is 1'', the transistor T1□ in the synchronous control circuit 2 is always off.

Therefore, the on/off state of the transistor TIO in the latch section depends on the signal MAT, and when the signal MAT is 1'', T'to
is on, and when MAT is 0'', Tlo is off.

Needless to say, when Tlo is turned on, it becomes synchronized and T
If lo is off, it will be in an asynchronous state.

Here, a comparison between the contents of the latch section and the contents of the counter section will be described.

When the signal input to the gate of transistor T15 in coincidence detection circuit 1 is 0'', this means that the contents of all 4 bits of the counter match the contents of the latch, and when the gate input of T15 is 1'. is a case where this matching is not achieved.

In other words, if the contents of the counter section for one bit and the contents of the latch section are both 0'', the output Q of the counter section is
Since A is 0'' and the voltage is 1'', the transistor T8 in the latch section is turned off and T is turned on.

Therefore, the output QA (Y1) (ie, VSS level) of the latch section is applied to the transistor T1□ in the coincidence detection circuit 1, and TI□ is turned off.

Also, the contents of the counter section and the contents of the latch section are both °゛ll.
When the transistor T8 in the latch section turns on, Q
, A (31) is the transistor T1 in the coincidence detection circuit 1
□ and T1 is turned off.

In this manner, when the contents of the counter section and the contents of the latch section are compared and they match, the transistor Tll is turned off.

Conversely, if the current contents of the counter section are lpp and the contents of the latch section are "0", the transistor T8 in the latch section is turned on, QA (30) (that is, VDD level) is applied to the transistor Tll, and T1□ is turned on. becomes.

Also, the content of the counter part is 0'' and the content of the latch part is "1".
”, Tll is also turned on.

In this way, when the contents of the counter section and the contents of the latch section do not match, the transistor Tll is turned on.

Therefore, if all 4 bits match, T
1□ and T□21 T'ts PT14 are both turned off, so the gate input of the transistor T15 becomes the VDD level, that is, 0''.

On the other hand, if even one bit does not match, one of T1□ to T14 is in the on state, so that the signal "1" is input to the gate of T15.

The above operation modes are summarized in FIG. 4.

Next, based on the above explanation, both the signal CM and the signal TR are set to n.
, tt and add count inputs IN and IN.

The counter section counts up sequentially from 0, but if this count number is less than the initial value A stored in advance in the latch section, the transistor T1 in the coincidence detection circuit 1
5 remains off and the signal MAT is 0''.

Therefore, the transistor T18 in the synchronous control circuit 2 is kept on, and the transistor T1o (for all 4 bits) in the latch section is kept off.

Therefore, the latch section and the counter section are asynchronous, and only the counter section continues counting up, and the latch section maintains the initial A.1 The count up in the counter section progresses, and at time t in FIG. When the contents of the latch portion match, the transistor T'o in the match detection circuit 1
j T12 t T13 t T14 are all turned off, transistor T15 is turned on, and signal MAT is set to "1".

As a result, the transistor T'ta in the synchronous control circuit 2 is turned off, and the transistor T'io in the latch section is turned on for all four bits.

Therefore, regarding the subsequent count-up, the latch section also counts up in synchronization with the counter section.

Assume that the count further advances and reaches time t2 (the count number is B) shown in FIG.

When time t2 is reached, a count clear signal C is sent to the counter section.
L is added.

Since this signal CL is applied to all 4 bits, the counter section is cleared and returns to O.

When the contents of the counter section become 0, the contents of the latch section (count number B) and the contents of the counter section no longer match, so the output signal MAT of the coincidence detection circuit 1 becomes "0".

Therefore, the transistor T18 in the synchronous control circuit 2 is turned on, and the transistor T10 in the latch section is turned on.

Therefore, an asynchronous state is established, and the counter section sequentially counts up from O while the count number B remains stored in the latch section.

When the count-up progresses and reaches time t3 shown in FIG. 3, the count contents of the counter section match the contents of the latch section (ie, B).

As a result, the transistor T15 in the coincidence detection circuit 1 is turned on, the signal MAT becomes 1'', the transistor T18 in the synchronization control circuit 2 is turned off, and the transistor T' in the latch section is turned on.
to turns on.

Therefore, for subsequent counting, the counter section and the latch section operate synchronously.

As described above, according to the present invention, when the counter section continues counting while being cleared at a constant period T, the maximum value is always stored in the latch section.

The period between times t4 and t5 in FIG. 3 shows a case where the counter cleared at time t4 has not reached the maximum value C stored in the latch section by time t5.

Next, a case will be described in which the power supply that energizes this maximum value counting device is turned off.

As is clear from the explanation of FIG. 1, it is detected that the power is turned off, and the signal M is made negative by about 24V, that is, -12V, and returned to VSS again.

As a result, the contents of the flip-flops of the counter section and the latch section are each written to the MNOS transistor in a non-volatile manner.

Furthermore, when the power is turned on, this is detected and V is set to the VSS level, and then the content of the MNOS transistor is read out to the flip-flop by gradually setting the signal M from VSS to a negative voltage.

As described in detail above, according to the present invention, the four digits of the decimal counter mentioned in the embodiment can be integrated into a single chip integrated circuit.
By controlling the signal M<15, both the count contents and the maximum value contents can be maintained even when the power is turned off.
- It is possible to write to the transistor and read it again when the power is restored.5Moreover, since this writing and reading is performed only when the power is turned on and off, the counting speed of the counter itself is limited to the speed of the non-volatile holding element. There is no.

Furthermore, according to the present invention, after the count contents of the counter section and the count contents of the latch section match, they operate synchronously without performing comparison, so unlike conventional devices, the count progresses while performing comparison each time. The configuration is simpler than many others.

Further, according to the present invention, since the comparison operation is performed within one chip, there is no need for a signal extraction pin for coupling with a comparison means provided outside the chip as in the conventional art.

In addition, in the above embodiment, the MNOS transistor MO8I
- Although the transistors are of p-channel type, they can be similarly implemented with n-channel types, and the flip-flops can also be of bipolar type.

Furthermore, in the present invention, an MNOS transistor is taken as an example of a non-volatile memory, but it is not limited to this, as long as it has an MIO8 structure or an MIS structure and stores information in a non-volatile manner in an insulating film. It is also possible to use one that can be erased and electrically written.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the constituent units of the device of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the device of the present invention, FIG. 3 is a diagram for explaining the operation of the device of the present invention, and FIG. The figure is a diagram showing the relationship between signals applied to the device of the present invention and operation modes. MT t 2MT 2...MNOS transistor, T1~TtTB~T'is...MOS) transistor, 1...Coincidence detection circuit, 2...
・Synchronous control circuit.

Claims (1)

[Claims] A counter section is formed by inserting a parallel circuit of a nonvolatile field effect memory transistor and a switching element between the active element of a flip-flop that constitutes each bit of the hexadecimal code and the load, and the circuit configuration is the same as that of this counter section. A latch section provided corresponding to the counter section, means for comparing the count contents of this latch section and the count contents of the counter section, and a comparison output obtained by this means to compare the count contents of the counter section and the latch section. A maximum value counting device comprising means for controlling connection, and operating the counter section and the latch section in synchronization when a matching output is obtained from the comparison means.