JPS589610B2 - Preset counter - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a preset counter, and in particular, the number of presets is serially inputted and written in a non-volatile semiconductor memory built into the counter, so that the counter can be preset in parallel at any time. Regarding preset counters.

Conventional preset counters are configured to perform presetting by connecting a switch for setting the number of presets, such as a digital switch, in parallel to the input terminal of each bit of a counter based on a flip-flop using a TTL or MOS circuit. .

FIG. 1 shows one decimal digit of this conventional preset counter.

As shown in this figure, the number of presets is 1 digital switch.
The signal is then applied to the preset data input terminals A, B, C, and D of the counter 2 as a 4-bit signal.

When a preset input signal is applied to the terminal LOAD in this state, the preset number given by 4 bits is set in the counter.

With the preset number thus set as the initial value, the count contents increase or decrease according to the input of the clock signal, and the count contents are increased or decreased at the data output terminals QA, QB t Qc p QD.
It is output from

However, the conventional preset counter cannot retain the contents of the counter when the counter itself is powered off, and the preset number must be reset again.

In order to eliminate this inconvenience, conventionally, a method was used in which the preset data input terminals A, B, C, and D provided on the counter were fixedly connected to the data terminal of the digital switch, which was the setting means, by soldering or the like. .

Therefore, a conventional preset counter necessarily has a manual device connected to the outside of the counter to provide a preset number.

Furthermore, since this input device is provided for each digit of the counter, the proportion occupied by the external device becomes extremely large, which causes the device to become larger and more complex.

In addition, when this preset counter is realized as an integrated circuit, all the terminals for coupling the input device and the counter must be provided as pins, which causes a large cost in the manufacture of the integrated circuit.

For example, if we consider a 4-digit decimal preset counter, four pins are required for one decimal digit, and 16 pins are required for the four digits.

Therefore, simply adding a preset function to a normal counter requires 16 additional pins, which is not desirable in terms of manufacturing integrated circuits.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a preset counter that does not require an external input device for setting the number of presets.

Another object of the present invention is to provide a preset counter that allows electrically easy setting and changing of the number of presets.

The present invention will be explained in detail below.

The present invention is based on the provision of a nonvolatile semiconductor memory capable of performing storage operations inside the counter.

A counter having a non-volatile generation semiconductor memory is described in detail in Japanese Patent Application No. 109005/1985, previously filed by the applicant, which will be briefly explained with reference to FIG.

Figure 2 shows the basic configuration of the non-volatile generation counter circuit.
This shows the circuit configuration for one bit of the decimal bit.

MT1 and MT2 are P-channel MNOS transistors, T1 to T6 are P-channel MOS transistors, and a total of eight elements constitute one bit.

Of the eight elements mentioned above, T1 and T2 are flip-flop switching MOS transistors, and T5 and T6 are load MOS transistors.

MNOS transistors MT1 and MT2 are interposed between switching MOS transistors T, T2 and load MOS transistors T5 and T6, respectively.

In addition, MOS transistors T3, T,
is provided.

Here, the load MOS transistors T, , T6 are of the depletion type, and all other MOS transistors are of the enhancement type.

MNOS transistors MT1, M in the circuit of Fig. 2
T2 applies a positive erase voltage (e.g. +
When applying 24■), the gate threshold voltage moves in the positive direction,
Conversely, a write voltage that is negative with respect to the source potential (for example, -24
) is applied, the gate threshold voltage shifts in the negative direction.

Also, in FIG. 2, the signal M is the MNOS transistor MT.
1. Control signals for restoring information, erasing information, and writing information in MT2, VDD and VSS are power supply voltages, and signal V
is a control signal for operating this non-volatile generation counter circuit as a normal counter circuit.

In this circuit, when energized, the signal M turns off the MNOS transistors MT and MT2, and the signal O turns off the MNOS transistors MT and MT2.
MOS transistors T3 and T4 connected in parallel to the S transistor are turned on.

Therefore, in this state, this counter operates as a normal MOS flip-flop.

Now, when MOS transistor T1 is on and MOS transistor T2 is off, the contents of this flip-flop are MN
Consider the case of writing to an OS transistor.

First, it is assumed that a pulse of about 24 V positive than VSS is applied in advance by the signal M to move the gate thresholds of the MNOS transistors MT1 and MT2 in the positive direction and set them to about -2.

In this state, signal M causes V ss (+1.2 V
), apply a 24V negative pulse, that is, a -12V pulse.

As a result, the insulating film of the MNOS transistor MT1 has approximately -
A voltage of 24 cm is applied, and the gate threshold of the MNOS transistor MT moves in the negative direction to about -8 cm.

On the other hand, since the channel potential directly under the gate of the insulating film of MNOS transistor MT2 is -6■, approximately -6
Only V is applied and gate threshold variations are prevented.

In this way, the contents of the flip-flop are non-volatilely stored as the gate threshold of the MNOS transistor.

When energized, as mentioned above, MOS transistors T3 and T4
is running, but the MNOS stored as described above
To read the contents of the transistor, first set Oka to VS.
It is set to S level and both Mos transistors T3 and T4 are turned off.

When MOS transistors T3 and T4 are turned off, there is no load on the flip-flop, and the MOS transistor T
Only the memory effect due to the gate capacitance of T2 remains.

The charge due to this capacitance varies depending on the value of the stray capacitance and the size of the gate threshold, but is gradually lost due to the leakage current of the P-N reverse junction.

When the remaining charge potential becomes almost O, if a negative potential is gradually applied from VSS to the signal M, the MNOS transistor with the lower gate threshold (in this case, the MNO
The S transistor MT2) turns on first.

Therefore, since a negative voltage is first applied to the source of the MNOS transistor MT2 from VDD, the MOS transistor T1 is first turned on, and the MOS transistor T2 is turned off, so that the contents stored in the MNOS transistor are read. Being exposed.

Therefore, by detecting whether the power is on or off and controlling the signal M,<15, the contents of the flip-flop are written to the MNOS transistors MT1 and MT2 when the power is turned off, and this memory content is stored when the power is turned on. can be read out.

The present invention is based on the above principle, and the preset number is stored in the memory by externally applying a signal to write the contents of the flip-flop to the non-volatile memory, and thereafter the counting operation is performed independently of the contents of the non-volatile memory. The preset counter according to the present invention has the circuit shown in FIG. As 1 bit, incorporate 4 bits of this to make 10
Consists of one hex digit.

If a 4-digit decimal count is required as a preset counter, four sets of these are further arranged.

FIG. 3 is a diagram showing one decimal digit of the preset counter of the present invention.

That is, one digit is constructed by arranging the circuits shown in Figure 2 for 4 bits, and for this one digit, input control circuit 1, reset and carry circuit 2, carry circuit 3, and signals to be applied to this circuit are generated. A control signal generation circuit 4 is provided.

In this figure, the signals M, v, ■DD Vss are the same as the signals shown in FIG.
The signal R is a control signal for inhibiting count input when writing information to the OS transistor, and is also a reset signal for resetting the circuit.

Furthermore, the output signals IN and IN of the input control circuit 1 are input signals to the first stage flip-flop circuit, and the signals Qt, Qe,
Q2q, Q3, and Q3 are the output signals of the flip-flops in each stage, and are also input signals to the flip-flops in the next stage.

In this figure, the carry circuit 3 has exactly the same configuration as that provided in a conventionally known MOS flip-flop circuit, and the input control circuit 1 and the reset and carry circuit 2 also have a switch function added to interrupt counting. has exactly the same configuration as the conventional one.

Further, the control signal generating circuit 4 is a switch mechanism for applying a predetermined voltage as shown in the figure.

Power supply voltage VSS = +12V, VDD = -6V
Next, the procedure for switching the switches in the control signal generating circuit 4 will be described.

In other words, first flip the switch to terminal ■, and set signal M to +36.
Let it be V.

As a result, all MNOS transistors in FIG. 3 are erased and their gate thresholds move in the positive direction.

Next, the signal 7 is connected to the terminal (2) and set to GND level, and a count input pulse is applied to the input control circuit 1. When the count reaches the desired preset number, the signal M is switched to the terminal (2) and set to -12V.

As explained earlier using Fig. 2, the signal M is set to +12V.
By switching from -1 to -12V, the count contents at that time are written to the MNOS transistor, and the preset number is set.

Also, by switching the signal M to +12V again after writing is completed and before the next count input is applied,
After writing, it works as a normal counter again.

Next, when the normal counter operation is performed and the count contents are changing, in order to return the count contents to the previously set preset number, first switch signal 7 to terminal ■ and wait for an appropriate time (several seconds). ), then switch the signal M to ■ and gradually change it toward GND.

That is, the voltage at terminal (2) is gradually lowered using a variable resistor or the like.

As a result, the contents previously written in the MNOS transistor (ie, the preset number) are read out to each flip-flop operating as a counter.

At this time, reading is completed by switching the signal 7 to the terminal ■ and returning it to GND, and then returning the signal M to +l2■ (■ss level), and the contents of the counter become the preset number set previously.

The preset counter according to the present invention is preset as described above, and the signal φ in FIG. Added to reset and carry circuit 2.

FIG. 4 is a diagram showing each input/output signal when the preset counter of the present invention is integrated.

The output of this counter is a BCD output for only one digit, and the digits can be assigned by an oscillator.

As explained above, according to the present invention, when a normal counter input is performed and the input value reaches a preset number, the preset number is written to the MNOS transistor built in the counter, and the normal counter is always input. MNO if you want to work as a preset again.
Since the contents written in the S transistor are read out, an external input device for setting preset inputs is not required, and the device can be made smaller.

Furthermore, even if a counter that has been preset is installed in another device, the preset value is stored in the non-volatile memory inside the counter, so there is no need for a preset setting device and there is no need to read it. All you need to do is install the circuit.

Furthermore, according to the present invention, there is no need for a preset terminal, so
No matter how many digits the counter has, there is no need for a dedicated preset input terminal.

Therefore, integration is easy.

Further, according to the present invention, the number of presets can be easily changed electrically, so that the present invention can be used for a wide variety of purposes.

In the embodiments of the present invention described above, the configuration of the control signal generation circuit 4 is shown as a simple switch mechanism to simplify the explanation, but this switch mechanism may be configured, for example, with an electric circuit using a transistor or the like. It goes without saying that the applied voltage can be controlled by a time constant circuit, a delay circuit, etc.

In addition, in FIGS. 2 and 3 for explaining the writing and reading of the preset counter of the present invention, the MNOS transistor and the MOS transistor are of P-channel type, but they can be similarly implemented with N-channel type, and flip-flops can also be used. It is also possible to implement the configuration by using bibolar type MOS transistors.

Furthermore, in the present invention, an MNOS transistor is used as an example of a nonvolatile memory, but it is not limited to this, but any type of MIOS or MIS structure that stores information nonvolatilely in an insulating film may also be used. It is also possible to use one that can be erased and written electrically.

In addition, it is possible to connect another non-volatile memory transistor in parallel to each of the pair of non-volatile memory transistors shown in FIGS. 2 and 3, and to apply the signal M independently to each pair of memory transistors. Functions can be expanded.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional preset counter, FIG. 2 is a diagram for explaining the operating principle of the preset counter according to the present invention, and FIG. 3 is a block diagram showing an embodiment of the preset counter according to the present invention. FIG. 4 is a diagram showing input/output terminals provided in a package when the preset counter according to the present invention is integrated. MT, MT2...MNOSI-transistor, T
~,11 T6...MOSt-transistor, 1...input control circuit, . 2... Reset and carry circuit, 3... Carry circuit, 4... Control signal generation circuit.

Claims (1)

[Claims] 1. A non-volatile field effect memory transistor inserted between each active element of a flip-flop constituting each bit of a binary code and a load, a switching element provided in parallel with each of the memory transistors, and the active element. means for supplying a count signal to the memory transistor; means for writing the information content of the flip-flop into the memory transistor as a preset number when the count number supplied by the means reaches a desired number; and the information written by the means. A preset counter comprising means for returning the flip-flop to the flip-flop and closing the switching element to perform a counting operation.