JPS5831058B2 - stereo fukuchiyou warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention supplies a composite stereo signal and a subcarrier signal to a multiplication circuit, performs the multiplication, and adds the composite stereo signal to the two multiplication outputs having opposite polarities to produce a stereo demodulated output. This invention relates to a stereo demodulation circuit that obtains the following.

First, three examples of conventional stereo demodulation circuits of this type will be explained with reference to FIGS. 1 to 3. First, with reference to FIG. 1, a first conventional example will be explained.

In Figure 1, 1 is an input terminal to which a composite stereo signal is supplied, 2a and 2b are input terminals to which a 38 kHz (7) subcarrier signal is supplied, and 3L and 3R are left and right audio signals which are stereo demodulated outputs. This is a signal output terminal.

Further, 4 is a power supply terminal, to which a power supply element B is connected.

6 is a differential amplification circuit to which a composite stereo signal is supplied.

This differential amplification circuit 6 is composed of a pair of transistors, and a composite stereo signal is supplied to the base of one of the transistors.

10 is a multiplication circuit consisting of a pair of differential amplification circuits 8 and 9, each of which is connected to the differential amplification circuit 6.
The transistors are stacked on the collector side of each transistor.

A subcarrier signal of 38 kHz is supplied as a balanced input from input terminals 2a and 2b to each differential amplifier circuit 8.9 of this multiplication circuit 10.

On the other hand, the stereo signal from the differential amplification circuit 6 is also supplied to this multiplication circuit 10.

Then, these composite stereo signals and subcarrier signals are
These signals are multiplied in the multiplication circuit 10, and stereo demodulated outputs, that is, left and right audio signals, are obtained at the output terminals 3L and 3R.

Incidentally, in reality, low-pass filters are connected to these output terminals 3L and 3R to remove high frequency components.

Here, the separation control variable resistor 5 is applied to the constant current source circuit of the differential amplification circuit, and the separation is controlled by variably adjusting and fixing the constant current source circuit.

This stereo demodulation circuit is mostly composed of a monolithic IC circuit, and a variable resistor for separation control is externally connected to this IC circuit as a constant current source circuit for the differential amplifier circuit 6. .

By adjusting this variable resistor, the gain of the differential amplifier circuit 6 is controlled, and thereby the multiplication circuit 10
The mixing amount of the main audio signal component consisting of the sum signal L+R of the left and right audio signals in the composite stereo signal supplied to the stereo signal is varied, thereby controlling the separation.

Such a stereo demodulation circuit has the advantage that only one terminal is needed for the separation control variable resistor when it is configured with a monolithic IC circuit.
There is a drawback that the DC level of the demodulated stereo output fluctuates.

Next, a second conventional example will be described with reference to FIG. 2, and parts corresponding to those in FIG. 1 will be denoted by the same reference numerals and redundant explanation will be omitted.

In this stereo demodulation circuit, in addition to the differential amplification circuit 6, another differential amplification circuit 7 is provided, and a composite stereo signal is also supplied to this from the input terminal 1, and the output of this differential amplification circuit 7 is is supplied to the multiplication circuit 10, and the separation control variable resistor 5 is applied to the constant current source circuit of the differential amplification circuit 7.

If this stereo demodulation circuit is also made into a monolithic IC circuit like the conventional example shown in Fig. 1, only one terminal is needed for the separation control variable resistor 5, but
There is a drawback that the DC level of the stereo demodulation output fluctuates.

Next, a third conventional example will be explained with reference to FIG.

In the conventional example shown in FIG. 3, after a composite stereo signal is demodulated by a stereo demodulation circuit 12, each demodulated output is transferred to transistors 13L and 1, which constitute a common emitter amplifier.
3R to amplify the width, and the intervening transistor 13L.
, 13R are also connected to each emitter side, and a variable resistor 5 for separation control is connected between each emitter.
are connected.

In this case, there is no fluctuation in the DC level of the demodulated output as in the stereo demodulation circuits shown in Figs. This is not preferable because there are two, T1 and T2.

In view of this, the present invention provides that the DC level of the stereo demodulated output does not change even if the separation control variable resistor is adjusted, and that when integrated into an IC, the external terminal is a dedicated terminal for the separation control variable resistor. The purpose of this paper is to propose a stereo demodulation circuit that requires only one.

Hereinafter, one embodiment of the present invention will be explained in detail with reference to FIG. 4.

FIG. 4 shows an embodiment of a stereo demodulation circuit according to the present invention, and parts corresponding to those in FIGS. 1 to 3 described above are denoted by the same reference numerals, and some redundant explanations will be omitted.

6 and 7 are first and second differential amplification circuits to which composite stereo signals are respectively supplied.

10 consists of third and fourth differential amplification circuits 8 and 9;
This is a multiplication circuit to which the subcarrier signal and the composite stereo signal from the first differential amplification circuit 6 are supplied and multiplied.

23 is a current relay circuit (current mirror circuit).

The same bias voltage is applied to the base of each transistor of the first and second differential amplifier circuits 6 and 7, and the above-mentioned composite stereo signal is also supplied.

A separation control variable resistor 5 is connected to the base of one transistor of the second differential amplifier circuit 7 to which the composite stereo signal is supplied.

The differential amplification circuit 6 includes an amplification transistor Q1. Q2 and a constant current transistor Q3.

The amplification transistor Q0 consists of transistors Q13 and Qxb connected in a Darlington connection, and the other amplification transistor Q2 consists of a transistor Q connected in a Darlington connection.
2a and Q2b.

A bias voltage is applied to the constant current transistor Q3 by the bias power source E1.

The second differential amplifier circuit 7 includes an amplifier transistor q.

Q, and a constant current transistor.

The amplifier transistor Q4 is composed of transistors Q4a and Q4b connected in a Darlington manner, and the other transistor Q4 is composed of transistors Qsa and Q5b connected in a Darlington manner.

Further, a bias is applied to the constant current transistor Q6 by the bias power source E1 described above.

As described above, the multiplication circuit 10 is composed of the third and fourth differential amplification circuits 8 and 9.

The third differential amplifier circuit 8 includes an amplifier transistor Q7. Q8
and Ql.

The fourth differential amplifier circuit 9 includes an amplifier transistor Q9. Ql
o and Q2.

A subcarrier signal of 38 kHz is supplied as a balanced input to the third and fourth differential amplifier circuits 8 and 9 from the input terminals 2a and 2b.

This multiplication circuit 10 is connected to each amplifier transistor Q1 . They are connected so that they are stacked on the collector side of Q2.

Transistor Q7 and each collector, load resistor 20
is connected to power supply E3 through transistors Q8 and Q
Each collector of 10 is connected through a load resistor 21 to a power source E3.

These load resistors 20 and 21 have the same resistance value RL.

A left audio signal output terminal 3L is led out from the collectors of the transistors Q7 and Q9, and a right audio signal output terminal 3R is led out from the collectors of the transistors Hiroshi and Qlo.

Current relay circuit (current mirror circuit) 23 is multiplication circuit 1
A pair of transistors Q 1s t Qt□ and the second differential amplification circuit 7 connected in a stacked manner to the collector side of each transistor of the third and fourth differential amplification circuits 8 and 9 of 0
The transistor Q13. connected to the collector side of the transistor Q13. It consists of Q14.

The collectors of transistors Q7 and Q are connected to the collector of transistor Q11, and the emitter of transistor Qtt is connected to power supply terminal 4.

Further, the collectors of transistors Q8 and Qlo are connected to the collector of transistor Q12, and the collectors of transistors Q8 and Qlo are connected to the collector of transistor Q12.
2 emitters are connected to power supply terminal 4.

The collector of transistor Q4, that is, Q, is transistor Q.
The emitter of the transistor Q14 is connected to the power supply terminal 4, the collector of the transistor Q13 is grounded, the emitter of the transistor Q13 is connected to the base of the transistor Q14, and the emitter of the transistor Q14 is connected to the base of the transistor Q14. Q1
Connected to each base of 2.

In this way, the current based on the composite stereo signal flowing between the collector and emitter of transistor Q14 is relayed to transistors Q1□ and Q12.

Now, each transistor Q1. of the first and second differential amplifier circuits 6 and 7. Bias power supply (
Constant voltage power supply) E2 connects resistors 1 with the same resistance value.
The same bias voltage is applied through 5, 16, 17 and 18.

Then, the composite stereo signal from input terminal 1 is connected to resistor 1.
9 through the transistor Q2 of the amplifier circuit 6, i.e. Q10.
The composite stereo signal is supplied to the base of the separation control variable resistor 5.
through the transistor Q? of the second differential amplifier circuit 7. n
That is, it is supplied to the base of Qsa.

Next, the operation of the stereo demodulation circuit shown in FIG. 4 will be explained with reference to the equivalent circuit shown in FIG. 5.

In FIG. 5, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and redundant explanation will be omitted.

In FIG. 5, 27 and 28 indicate the power flow of the multiplication outputs -(R-L) and -(L-R) from the multiplication circuit 10.

Further, 25 and 26 indicate current sources of the main audio signal R+L in the composite stereo signal from the second differential amplification circuit 7, respectively.

Then, the left audio output obtained by adding the currents from the current sources 26 and 28 is obtained at the output terminal 3L, and the output terminal 3R
In this case, the right audio output is obtained by adding the currents from the current sources 25 and 27.

Furthermore, by adjusting the separation control resistor 5, it is possible to vary the input level of the composite stereo signal supplied to the second differential amplification circuit 7, especially the main audio signal component. Separation control is performed.

In this case, the transistors Q2 and Q of the first and second differential amplifier circuits 6 and 7 are supplied with composite stereo signals, respectively.
Since the potentials of the bases of , are exactly the same, no DC current flows through the resistors 19 and 5, and therefore, the DC level of the stereo demodulation output from the stereo demodulation output terminals 3L and 3R does not change.

According to the above-described stereo demodulation circuit of the present invention, the circuit includes first and second differential amplification circuits, which are respectively supplied with a composite stereo signal, and third and fourth differential amplification circuits, which are supplied with a subcarrier signal and a subcarrier signal. a multiplier circuit to which a composite stereo signal from one differential amplification circuit is supplied and multiplied; The stereo signals are added to obtain a stereo demodulated output, the same bias voltage is applied to the bases of the transistors of each of the fourth and second differential amplifier circuits, and a composite stereo signal is supplied. Since the separation control variable resistor is connected to the base of one of the transistors to which the composite stereo signal of the second differential amplification circuit is supplied, stereo demodulation can be performed by adjusting the separation control variable resistor. If the DC level of the circuit does not fluctuate and it is integrated into an IC, only one external terminal is required for the separation control variable resistor.

[Brief explanation of the drawing]

1, 2, and 3 are circuit diagrams showing conventional stereo demodulation circuits, FIG. 4 is a circuit diagram showing an example of a stereo demodulation circuit according to the present invention, and FIG. 5 is a circuit similar to the one shown in FIG. 4. FIG. 6.7.8 and 9 are the first to fourth differential amplifier circuits, respectively;
10 is a multiplication circuit, 23 is a current relay circuit (current mirror circuit), and 5 is a variable resistor for separation control.

Claims (1)

[Claims] 1 Consisting of first and second differential amplification circuits and third and fourth differential amplification circuits to which composite stereo signals are respectively supplied; a multiplication circuit to which the composite stereo signal is supplied and multiplied;
A composite stereo signal from the second differential amplification circuit is added to the two multiplication outputs of the multiplication circuit having opposite polarities, respectively, to obtain a stereo demodulated output, and the difference between the first and second The same bias voltage is applied to the base of each one of the transistors of the dynamic amplification circuit, and the composite stereo signal is supplied to the base of each transistor, and the composite stereo signal is transmitted to the second differential amplification circuit via the separation control variable resistor. A stereo demodulation circuit characterized in that the signal is supplied to the base of one of the above transistors.