JPS5833704B2 - semiconductor equipment - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor device.

Semiconductor device special feature: A multilayer wiring structure is used in semiconductor integrated circuits, and a metal wiring layer constituting one wiring layer of the multilayer wiring structure, such as an aluminum wiring layer, and a silicon substrate forming another wiring layer are used. Although electrical contact is obtained through a contact hole provided in an insulating layer and a diffusion layer or other wiring layer having a conductivity type different from that of the silicon substrate, such as a polycrystalline silicon wiring layer, good electrical contact is not possible. In order to obtain this, heat treatment is performed to alloy the desired interconnections.

However, alloying between wirings progresses more than necessary in the contact hole portion, or progresses violently locally, causing deterioration of the P-n junction and disconnection of the multilayer wiring layer.

The present invention provides a highly reliable and high yield semiconductor device, particularly a silicon semiconductor integrated circuit, by controlling the alloying reaction.

A conventional example will be explained using FIGS. 1 to 3.

That is, after forming an oxide film 2 on a p-type silicon substrate 1 using, for example, a thermal oxidation technique, a window is opened in the oxide film 2 in the transistor formation and diffusion wiring area using a conventional photolithography method.

Thereafter, a gate electrode 3 made of polycrystalline silicon is formed using thermal oxidation technology, polycrystalline silicon growth technology, photoetching technology, etc.
Then, wiring layers 4 and 5, electrodes 3, and gate oxide film 6 constituting one layer of multilayer wiring are formed.

Thereafter, phosphorus is diffused to form diffusion regions such as the drain region 7 and source region 8 of the MO8 transistor, and at the same time, impurities are added to the polycrystalline silicon gate electrode 3 and wiring layer 4.5 to make the resistance low.

After forming a low-temperature oxide film 9, contact holes, 10°11.
2 and 13 are provided, and the aluminum wiring layer 1 constituting the other layer of the multilayer wiring structure is further formed using vapor deposition technology and photoetching technology.
4, form 15.16.

Thereafter, drain region 7, source region 8, polycrystalline silicon wiring layers 4, 5 and aluminum wiring 14,
In order to obtain good ohmic contact with 15 and 16, heat treatment is performed at 500° C. for 15 minutes in a nitrogen atmosphere, for example.

During this heat treatment, silicon and aluminum react and form an alloy, but if the amount of aluminum connected to the contact area is large, the polycrystalline silicon wiring layers 4 and 5 will be disconnected as shown in FIG. The alloy layer 19.20 is formed when the pn junction 18 formed by the p-type silicon substrate 1 and diffusion regions such as the drain region 7 and the source region 8 is penetrated. This often results in deterioration of p-n junction characteristics.

In other words, silicon melts into aluminum in a certain amount at a certain temperature, and then diffuses through the aluminum.
For example, if only a long aluminum wiring with a narrow width, say 10μ, is in contact with silicon through a contact hole with a size of 6μ x 6μ, enough silicon will be supplied to the aluminum wire, but if the width is wide, say 10μ, Wider aluminum wiring 16 is in direct contact, for example in contact holes 12 and 13 with a size of 6μ x 6μ,
If there is not enough silicon to be supplied to the aluminum wiring 16 under the contact or within 30μ from the periphery of the contact hole 12.13, silicon is also supplied from the polycrystalline silicon wiring layer around the contact, and as a result, the disconnection 17 often occurs.
For example, as in a contact hole 11 with a size of 6μ x 6μ, an aluminum wiring 16 wider than XOμ may be located within 30μ from the edge of the contact hole.
For example, if the aluminum wiring 15 is provided via an aluminum wiring 15 with a width of 10μ, and there is no silicon supply source for the aluminum wiring 16 nearby other than the source region 9, silicon is mainly supplied from the end of the contact hole, which often causes local oxygen reactions. As the process progresses, an alloy layer 20 is formed that penetrates through the p-n junction 18, as shown in FIG. width wider than 10μ, e.g. 20
Aluminum wiring 14 and drain region 7 having a width of μ
If the aluminum wiring 14 at the end of the contact hole is in contact with the aluminum wiring 14 at the end of the contact hole
An alloy layer 19 is formed near the p-n junction 18 by passing through the p-n junction 18, similar to the contact hole 11'.
Furthermore, even if the above-mentioned wire breakage or alloy layer penetration does not occur during heat treatment, electromigration may cause the above-mentioned phenomenon during the operation of the semiconductor device, reducing the yield and reliability of semiconductor devices, especially integrated circuits. It was the cause of decreased sexual ability.

To eliminate these drawbacks, the conventional improvement method is to provide a thin layer of a metal that does not easily react with the silicon substrate, such as titanium, in the contact area, then provide an aluminum wiring, or provide a polycrystalline silicon film or an epitaxial layer. Although it has been attempted to provide an aluminum wiring layer or a deep diffusion layer, titanium has the disadvantage that it has a high melting point and is difficult to evaporate, and in the case of a polycrystalline silicon film, the contact resistance is high and the epitaxial layer is In this case, the process becomes complicated, and if the diffusion layer is provided deeply, it is difficult to achieve integration.

Further, Japanese Patent Application Laid-Open No. 50-29161 discloses connecting a rectangular At bonding pad and a contact hole of a diffusion wiring with an At wiring formed in a comb-shaped G shape.

However, in places where high integration is required, such as inside a chip, a technique such as adding At wires in the shape of a comb shape cannot be applied.

The present invention has been made in view of the above-mentioned circumstances, and aims at high integration by providing a slit-like cut in a wide metal wiring layer along the length direction of the wiring to suppress the diffusion of semiconductor material from the contact hole. However, it is possible to prevent the aforementioned disconnection of the polycrystalline silicon wiring layer and the penetration of the p-n junction of the At-8i alloy layer, thereby improving the yield and reliability of the semiconductor device.

Furthermore, in the present invention, a slit-like cut is provided along the wiring length direction, so by adjusting the length of the slit, the path from the contact hole to the wide wiring layer can be freely controlled. This makes it easier to design patterns for thin lines that connect to.

Furthermore, in the present invention, since the cut is in the form of a slit along the length direction of the wiring, the metal wiring can be kept wide everywhere, which reduces the increase in wiring resistance and achieves low wiring resistance while achieving high integration. You can do it like this.

Furthermore, there is no need to worry about metal wiring deterioration or disconnection due to electromigration or heat generation.

An embodiment of the present invention will be described below with reference to the drawings.

The method is the same as the conventional method except that the shape of the aluminum wiring in FIG. 4 is different.

To explain this embodiment in more detail, in FIG. 4, an aluminum wiring with a width of, for example, more than 10μ is provided within 30μ from a contact hole, and a silicon supply source is sufficient to supply silicon to the aluminum wiring near the contact hole. If not, for example source area 8
For example, a contact hole 11' with a size of 6μ x 6μ is formed in '.
For example, an aluminum wiring 15' with a width of 1.0μ and a length of 15μ (a = 15μ) is connected to a contact width of 30μ (e = 30μ) through the
When connected to the aluminum wiring 1σ of For example, a width of 6μ (d
A notch 17' having a diameter of 6μ) is provided.

The width of this cut may be as narrow as photolithography allows.

The cut may be made in a part of the thickness of the wiring layer.

By providing the notch 17, silicon diffusion into the surrounding aluminum layer is suppressed, resulting in the so-called "Aj?"
The "breakthrough" phenomenon was prevented.

The effective line width of the aluminum wiring 16' is 24μ (e-
d=24μ), which is less than 30μ, but if the current capacity is sufficient, there is no need to increase the width of the aluminum wiring 16'.

If the current capacity of the wiring is not sufficient, the effective line width (ed) can be made equal to the line width of 30μ before providing the notch 17', as seen in the latter two embodiments.

However, since the cut 17' is provided along the length direction of the wiring, the aluminum wiring 16' can be kept wide and its resistance is low.

Also, when an aluminum wiring with a width of 10μ or more comes into direct contact with a polycrystalline silicon wiring layer or a silicon diffusion layer through a contact hole, and there is no silicon supply source that can supply enough silicon to the aluminum wiring near the contact hole. For example, a cut 1 of 6μ (d-6μ) is formed on both sides or one side of the contact hole, such as in the contact holes 12' and 13' with a size of 6μ x 6μ.
For example, the line width of the aluminum wiring directly connected to the polycrystalline silicon wiring layers 4 and 5 through the contact holes 12/and 13' is 10μ (
f2g=10μ), length is 20μ or more (h″220μ,
20μ).

As a result, breakage of the polycrystalline silicon in the contact ball is prevented, and at this time, the cuts 1 B', 19', 20'
If the current capacity of the aluminum wiring 16' is increased by providing the cutouts 18', 19', and 20', it is necessary to cut the aluminum wiring 16' on the desired side of the aluminum wiring 16' so that the effective aluminum line width is the same as before providing the cuts 18', 19', and 20'. A protruding portion 21'22' can be provided (i+f+=g+430μ).

By narrowing the width of the cut, this bulge can be made sufficiently small.

In the above embodiment, the wide aluminum wiring is in direct contact with the polycrystalline silicon wiring layer through the contact hole, and the diffusion layers such as the drain and source regions are connected to the wide aluminum wiring through the narrow aluminum wiring. Although the case where the polycrystalline wiring layer is connected to a wiring has been described, the gist of the present invention does not change even if the polycrystalline wiring layer is connected to a wide aluminum wiring via a narrow aluminum wiring.

Further, in the above embodiments of the present invention, the case of an n-channel silicon gain MO8 type integrated circuit has been described, but it is not limited to an n-channel type, but may also be a p-channel type, and not limited to a silicon gate, but may also be an aluminum gate type. It goes without saying that the present invention is not limited to the present invention and can be applied to bipolar integrated circuits, and can be applied not only to integrated circuits but also to other semiconductor devices as long as they do not depart from the spirit of the present invention.

Further, it is preferable that the cut is made so that the width of the wiring connected to the contact hole is approximately equal to the width of the contact hole within 30 μm from the contact hole.

Further, although silicon is used as the semiconductor substrate and the polycrystalline semiconductor layer, other semiconductor materials such as germanium, gallium arsenide, and combinations of these materials may also be used without departing from the spirit of the present invention.

Further, although aluminum is used as the metal wiring layer, other materials may be used as long as they do not depart from the spirit of the present invention.

[Brief explanation of drawings]

1 and 2 are a sectional view and a plan view, respectively, showing the structure of a conventional n-channel silicon gate O8 type integrated circuit, FIG. 3 is a sectional view explaining the conventional example, and FIG. FIG. 2 is a plan view illustrating one embodiment. In the figure, 1 is a p-type silicon substrate, 2 is a thermal oxide film, 3, 4, and 5 are polycrystalline silicon gate electrodes and wiring layers, 6 is a gate oxide film, 7 and 8 are drain and source regions, respectively, and 9 is a Low temperature oxide film, 10,1
1, 12° 13 are contact holes, 14, 15, 16
17 is an aluminum wiring, 17 is a disconnection part, 18 is a p-n junction, 19 and 20 are aluminum alloy layers, 3', 4/, and 5/ are polycrystalline silicon gate electrodes and wiring layers, respectively, and 7' and 8' are respectively Drain and source regions, 10', 11', 12', 13' are contact holes, 14', 15', 16' are aluminum interconnections, 17', 18'. 19' and 20' are cut portions, 21' and 22' are protruding portions, and 23' and 24' are aluminum branch wirings.

Claims (1)

[Claims] 1. In a semiconductor device in which a semiconductor region and a wide metal wiring layer are connected via a contact hole, the wide metal wiring layer ζ suppresses diffusion of semiconductor material from the contact hole along the wiring length direction. A semiconductor device characterized by having a slit-like cut.