JPS5816338B2 - Hand tie souchi - Google Patents

Description

Detailed Description of the Invention A multilayer wiring structure is used in semiconductor devices, particularly semiconductor integrated circuits, and a metal wiring layer, such as an aluminum wiring layer, constitutes one wiring layer of the multilayer wiring structure, and a silicon substrate constitutes another wiring layer. Electrical contact is obtained through a contact hole formed in an insulating layer and a diffusion layer or other wiring layer having a conductivity type different from that of the silicon substrate provided therein, such as a polycrystalline silicon wiring layer. In order to obtain electrical contact, a heat treatment is performed to alloy the desired interconnections.

However, alloying between wirings progresses more than necessary in the contact hole portion, or progresses violently locally, causing deterioration of the pn junction and disconnection of the multilayer wiring layer.

The present invention provides a method for suppressing alloying reactions and obtaining highly reliable, high-yield semiconductor devices, particularly silicon semiconductor integrated circuits.

Next, a more detailed explanation will be given by taking an n-channel silicon gate type integrated circuit as an example.

The conventional method is to form an oxide film 2 on a p-type silicon substrate 1 using, for example, thermal oxidation technology, as shown in FIGS. Remove using etching method.

Thereafter, using thermal oxidation technology, polycrystalline silicon technology, photoetching technology, etc., the gate electrode 3 made of polycrystalline silicon, the wiring layers 4 and 5 constituting the seven layers of the multilayer wiring, the gate electrode 3, and only the bottom of the gate electrode 3 are removed. A gate oxide film 6 is formed.

Thereafter, phosphorus is diffused to form diffusion regions such as the drain region 7, the source region 8, and the diffusion wiring layer 9 constituting one layer of the multilayer wiring of the MO8 transistor, and at the same time, the polycrystalline silicon gate electrode 3 and the wiring layer 4. Impurities are added to 5 to lower the resistance.

After forming the low temperature oxide film 10, the drain region 7
In order to make electrical contact with the source region 8 and the wiring layers 4 and 5, contact holes 11 and 12 are formed using photolithography.
．． 13 and 14 are provided, and aluminum wiring layers 15, 16, and 17 constituting the other layer of the multilayer wiring structure are further formed using vapor deposition technology and photolithography technology.

Thereafter, drain region 7, source region 8, polycrystalline silicon wiring layers 4 and 5, and aluminum wiring 15.
In order to obtain good ohmic contact between 16 and 17, heat treatment is performed at 500° C. for 15 minutes in a nitrogen atmosphere, for example.

During this heat treatment, silicon and aluminum react and become alloyed, but if the amount of aluminum in contact with each other is large relative to the contact area, as shown in Figure 1, the polycrystalline silicon wiring layer is 4,5
A disconnection 18 may occur in the contact hole 12, or a reaction may progress locally as in the contact hole 12, causing the p-n junction 19 composed of the p-type silicon substrate 1 and diffusion regions such as the drain region I and the source region 8 to be damaged. When punching, an alloy layer 20 is formed p-n
Bonding properties deteriorate.

In other words, silicon dissolves in aluminum in a certain amount at a certain temperature, and then diffuses into aluminum.
For example, a long aluminum wiring 15 with a narrow width of 10μ, for example, is connected through a contact hole 11 with a size of 6μ×6μ.
If only the aluminum wiring 17 is in contact with silicon, sufficient silicon is supplied to the aluminum wiring 15, but if the aluminum wiring 17, which is wider than 10μ, for example, has a width of 30μ, is directly in contact with the silicon, as in the contact holes 13 and 14 with a size of 6μ x 6μ, for example. contact, below the contact or contact hole 13,1
4. If there is not enough silicon to be supplied to the aluminum wiring 17 within 20μ from the periphery, silicon is also supplied from the polycrystalline silicon wiring layer around the contact area. As a result, a disconnection part 1B often occurs, for example, a wire with a size of 6μ× As in the contact hole 12 of 6μ, an aluminum wiring 17 having a width of, for example, more than 1.0μ is placed within 20μ from the end of the contact hole, for example, an aluminum wiring 16 having a width of lOμ.
If there is no silicon supply source for the aluminum wiring 17 nearby other than the source region 9, silicon is supplied from the end of the contact hole, and the reaction often progresses locally as shown in FIG. Like p-n
There is a phenomenon in which the p'-n junction 19 is degraded due to the formation of the alloy layer 20 that penetrates through the junction 19, and even if the above-mentioned wire breakage or alloy layer penetration does not occur during heat treatment, the semiconductor device remains in operation. The above-mentioned phenomenon occurs due to electromigration, which causes a decline in the yield and reliability of semiconductor devices, especially integrated circuits.

To eliminate these drawbacks (conventional improvement methods include forming a thin layer of a metal, such as titanium, which does not react with the silicon substrate at the contact area, and then forming an aluminum wiring, or forming a polycrystalline silicon film or an epitaxial layer). However, titanium has a high melting point and is difficult to evaporate, and in the case of polycrystalline silicon films, contact resistance is high. In the case of an epitaxial layer, the process is complicated, and if the diffusion layer is provided deeply, it is difficult to achieve integration.

In addition to actively closing the diffusion layer as a multilayer wiring layer, the present invention also provides a diffusion layer near the contact hole and uses it as a silicon supply source to prevent the aforementioned disconnection and At penetration, thereby improving the yield and reliability of semiconductor devices, especially integrated circuits. The aim is to improve

Next, referring to FIG. 3, a fourth embodiment of the present invention will be described.
When removing the oxide film 2 in the transistor formation area and the diffusion wiring area by normal photolithography after forming the silicon oxide film 2, the diffusion regions 21', 22', 23', 24, which serve as silicon supply sources, are removed at the same time.
The portion of the oxide film 2' where the oxide film 2' will be formed is also removed.

In the subsequent process, when phosphorus is diffused into the drain region 7', the source region 8', and the diffusion wiring layer γ constituting one layer of the multilayer wiring, the diffusion regions 21', 22', 23', 2 are simultaneously diffused.
4 was also diffused with phosphorus, and contact holes 11' and 1
When 2', 13', and 14 holes are provided, a diffusion region 21' is newly provided as a silicon supply source.

Aluminum wiring 1 for 22', 23', 24'
Contact hole 25', 2 for making contact with 7'
6', 27'.

The process is the same as the conventional process except for providing 28'.

To explain this example in more detail, for example, 6μm×6
Contact holes 12', 13' with a size of μm.

For example, if an aluminum wiring 17';
Aluminum wiring 17' at a branch point between aluminum wiring 16' and aluminum wiring 11' having a width of, for example, 30 μm.
A silicon supply diffusion region 21' having a size of, for example, 34 μm x 34 μm and a size of, for example, 30 μm x 30 μm are provided at T.
Contact holes 259! are provided in the diffusion region 21' during heat treatment to obtain good ohmic contact. : Since a large amount of silicon is supplied to the 30 μm wide aluminum wire 17' through the contact hole 12' and the IO μm wide aluminum wire 16', a large amount of silicon is supplied to the 30 μm wide aluminum wire 17 from the source region through the contact hole 12' and the IO μm wide aluminum wire 16'. As a result, penetration of the alloy layer at the pn junction, which was observed in the conventional example, could be prevented.

In addition, as seen in the polycrystalline silicon wiring layer 1, within 20 μm from the contact hole 13', the size is 34 μm, for example.
×20μm silicon supply diffusion regions 22' and 23
′ on both sides of the silicon supply diffusion regions 22 ′ and 23 ′.
Contact hole 26' of 6 μm x 20 μm.

27', silicon supply diffusion regions 22', 2
From 3' onwards, silicon is connected to aluminum wiring 17 with a width of 30 μm.
Since a large amount of silicon is supplied to the aluminum wiring 17' from the contact hole 13', a large amount of silicon is prevented from being supplied to the aluminum wiring 17', and as a result, the disconnection seen in the conventional embodiment can be prevented.

Furthermore, when a diffusion wiring layer γ constituting one wiring layer of a multilayer structure is provided within 20 μm from the contact hole 14' as seen in the polycrystalline silicon wiring 5', silicon is supplied only to one side of the contact hole 14'. Diffusion area 2
4' and a contact hole 28' can also be provided. Even if the supply diffusion region and the contact hole are provided, if other diffusion wiring layers are provided on both sides of the polycrystalline silicon wiring 5', the silicon supply diffusion region and the contact hole are provided outside the two diffusion wiring layers. Even if a hole is provided, the effect of the present invention is that the silicon supply diffusion regions 22', 23 are immediately adjacent to both sides as in the wiring layer 4'.
The effect of the present invention was still small compared to the case where 1 was provided, and the effect of the present invention was still small from the perspective of the semiconductor device as a whole.

In the above embodiment of the present invention, the contact hole 25
In ', 26', 27', and 28', the phenomenon of punching out of the p-n junction of the alloy layer as seen in the conventional examples was not observed.

The reason for this is, for example, as seen in the contact hole 11' with a size of 6μ771×6μm.
When only an aluminum wiring 15' having a width of 10 μm, for example, which is equal to or slightly larger than 10 μm, is connected, sufficient silicon is supplied to the aluminum wiring 15' from the drain region 1' before the alloy layer is formed. Contact hole 25' as well.

Via 26', 27', 28', the diffusion regions 21', 22', 23' are penetrated before the alloy layer is formed.

Contact holes 25', 26', 27 from 24'
'.

28', for example, a width of 30 prn, and a sufficiently narrow width, for example, a width of 10 μm.
This is because silicon is sufficiently supplied to the m aluminum interconnections 16'.

Further, in the above embodiment of the present invention, the silicon supplying diffusion region 21' was provided separately from the source region 8' as shown in FIG. 3, but as shown in FIG. The region 8' and the diffusion region 21' may be provided as a common diffusion region ''. Furthermore, although not shown in the figure, the north region 8'
, the diffusion regions 21', 27, and 23' can also be provided as a common diffusion region.

Furthermore, in the embodiments of the present invention described above, the wide aluminum wiring is in direct contact with the polycrystalline silicon wiring layer through the contact hole, and the diffusion layer such as the source region is connected to the wide aluminum wiring through the narrow aluminum wiring. The case where the wide aluminum wiring is connected to a wide aluminum wiring has been described, but the wide aluminum wiring is in direct contact with a diffusion layer such as a source region through a contact hole, and the polycrystalline silicon wiring layer is connected to a narrow aluminum wiring. The gist of the present invention does not change even if the wire is connected to a wide aluminum wire.

Furthermore, in the embodiments of the present invention, when providing a silicon supply diffusion region, the area increases unnecessarily from the viewpoint of the original circuit operation, and electrical contact is not made to the silicon supply diffusion region through a contact hole. In this case, if the aluminum wiring is broken at the step part of the contact hole or the step part of the diffusion region, resulting in a decrease in yield and reliability, which is contrary to the purpose of the present invention, when providing the silicon supply diffusion region, it is necessary to Due to the complexity of the process, it is not necessarily necessary to provide a silicon supply diffusion region at all locations where aluminum wiring, which is wider than the contact hole, is provided within 20 μm from the contact hole. There is no change in the gist of the invention.

In addition, in the above embodiments of the present invention, the case of an n-channel silicon gate (MO8 type integrated circuit) has been described, but it is not limited to an n-channel type, but may also be a p-channel type, and not limited to a silicon gate, but may also be an aluminum gate type. It goes without saying that the present invention is not limited to the present invention and can be applied to bipolar integrated circuits, and can also be applied not only to integrated circuits but also to other semiconductor devices as long as they do not depart from the gist of the present invention.

Although a diffusion region provided in a silicon substrate is used as a silicon supply source, the silicon substrate itself may be used as long as it does not affect the operation of the semiconductor device. It is clear that the present invention can be applied to germanium, gallium arsenide, etc., and also to metals such as tungsten, in addition to aluminum, as long as the gist of the present invention is not departed from.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining a conventional embodiment, and FIG. 2 is a plan view of a part of a semiconductor integrated circuit showing a conventional embodiment.
FIG. 3 is a plan view of a part of a semiconductor integrated circuit showing an embodiment of the present invention, and FIG. 4 is a plan view for explaining another embodiment of the invention. In the figure, 1: silicon substrate, 2: thermal oxide film, 3: polycrystalline silicon gate electrode, 4, 5: polycrystalline silicon wiring layer, 6: gate oxide film, 7: drain region, 8: source region, 9: diffusion Wiring area, 10: Low temperature oxide film, 11, 12
, 13, 14: contact hole, 15, 16, 17:
Aluminum wiring, 18: Polycrystalline silicon disconnection, 19
: p-n junction, 20 : Al-8i punching is alloy layer, 2
1′. 22', 23', 24': silicon supply diffusion region, 2
5', 26', 27', 28th contact hole, 8'': common diffusion region.

Claims (1)

[Claims] 1. In a semiconductor device having a continuous metal wiring layer that is connected through a contact hole, the metal wiring layer may be in contact with an intermediate part of the metal wiring layer near the contact hole.
A semiconductor device characterized in that a pn junction layer for supplying semiconductor material is provided on a semiconductor substrate.