JPS583378B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a wiring layer incorporated into a semiconductor device.

In integrated circuits (ICs), impurity diffusion layers formed on the surface of a semiconductor substrate are often used as wiring layers that electrically connect semiconductor elements.

It is desirable that the sheet resistance of the wiring layer made of such an impurity diffusion layer be as small as possible in order to eliminate adverse effects such as deterioration of the characteristics of the semiconductor device due to generation of Joule heat or delay in the transmission time of electric signals.

However, in order to reduce the sheet resistance, it is necessary to increase the impurity concentration and diffuse the impurities.
The diffusion depth becomes large, and the width of the formed wiring layer also becomes large, which has been a major hindrance to the integration of integrated circuits.

For example, the diffusion time and the formed diffusion layer when boron (B), which is a P-type impurity, is diffused onto the n-type silicon substrate surface at a temperature of 1000°C with a diborane flow rate of 270 cc/min and an oxygen flow rate of 14 cc/min. The relationship with the sheet resistance value is shown in the graph of FIG.

To make the sheet resistance surface of the diffusion layer 26Ω/□,
It takes about 20 minutes for diffusion, and the depth of the diffusion layer at this time is about 1.4μ.

Therefore, an object of the present invention is to provide a semiconductor device incorporating a wiring layer in which the depth of an impurity diffusion layer is reduced and the sheet resistance is reduced.

In order to achieve such an object, the present invention uses a polycrystalline silicon layer formed on a semiconductor substrate and a diffusion layer formed by diffusing impurities through this polycrystalline silicon layer as a wiring layer. It is something.

Hereinafter, details of the present invention will be explained using Examples.

FIG. 2 is a sectional view showing one embodiment of a semiconductor device according to the present invention, and particularly shows a semiconductor device incorporating a MOS type transistor.

In the figure, there is an N type silicon substrate 1, and a drain region 2 and a source region 3 are formed by selectively diffusing P+ type impurities into a certain region of the surface of the substrate.

A gate oxide film 4 made of a silicon thermal oxide film is formed on the surface of the N-type silicon substrate 1 between the drain region 2 and the source region 3, and a gate electrode 5 is formed on the upper surface of the gate oxide film 4.

On the other hand, another P+ type diffusive layer 6 is formed on the surface of the N type silicon substrate 1 to be connected to the source region 3, and is formed on the surface of the N type silicon substrate 1 between the source region 3 and the P+ type diffusion layer 6. CVD (Chemical Vapor
A polycrystalline silicon layer 7 formed by a polycrystalline silicon deposition method or the like is deposited, and the surface of the underlying N-type silicon substrate 1 is a P+ type diffusion layer in which boron (B) is diffused through the polycrystalline silicon layer 7. A wiring layer 8 is formed.

Then, a MOS type transistor formation region and a wiring layer 8
A thick field oxide film 9 is formed on the top surface of the N-type silicon substrate 1, which is an area other than the formation region, and the top surface of the N-type silicon substrate 1, which has been surface-processed in this way, is coated with, for example, phosphorus silicate glass. A passivation film 10 consisting of layers is coated.

Furthermore, a contact hole is provided in the passivation film 10 to expose a portion of each of the drain region 2 and the P+ type diffusion layer 6. A wiring layer 11 is formed on the passivation film 10.

In this way, a polycrystalline silicon layer with an arbitrary thickness is formed on the wiring layer formation region of the semiconductor substrate, and from the top surface of this polycrystalline silicon layer, the flow rate of diborane is set to 270 cc/min and the flow rate of oxygen is set to 14 cc/min. When boron B, a P-type impurity, is diffused for 12 minutes at a temperature of 1000°C, the sheet resistance measured on the top surface of the polycrystalline silicon layer was found to depend on the thickness of the polycrystalline silicon layer, as shown in the graph in Figure 3. do.

In order to obtain a sheet resistance of 26Ω/□, if the thickness of the polycrystalline silicon layer is 5000 Å, the depth of the impurity diffusion layer in the n-type silicon substrate 1 in which boron B is simultaneously diffused is 1.1 μ. was completed.

Therefore, the depth of the impurity diffusion layer can be made small, and the sheet resistance can be made small, so that the integration of semiconductor devices such as integrated circuits can be achieved.

In this example. Impurities are added from above the polycrystalline silicon layer.
Although it is diffused into a type silicon substrate, it is not necessarily limited to this, and it goes without saying that a diffusion process may be performed after forming a polycrystalline silicon layer doped with impurities in advance.

Further, in this embodiment, boron B is used as an example of the impurity, but it goes without saying that similar effects can be obtained using other impurities.

Further, in this embodiment, a wiring layer is incorporated together with a MOS type transistor, but other semiconductor elements such as a bipolar transistor may be used.

As explained above, according to the semiconductor device according to the present invention, the depth of the impurity diffusion layer in the silicon substrate is reduced,
Moreover, a wiring layer with low sheet resistance can be obtained.

As a result, it is possible to improve the integration of the semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a graph showing the relationship between impurity diffusion time and sheet resistance when forming a conventional wiring layer, FIG. 2 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. It is a graph for showing the effect of the invention. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2... Drain region, 3
... Source region, 4... Silicon thermal oxide film, 5...
- Gate electrode, 6... P+ type diffusion layer, 7... Polycrystalline silicon layer, 8... Wiring layer, 9... Field oxide film, 10... Passivation film, 11... Aluminum wiring layer.

Claims (1)

[Claims] 1. A semiconductor device characterized in that a polycrystalline silicon layer formed on a semiconductor substrate and a diffusion layer formed by impurity diffusion through this polycrystalline silicon layer are used as electrical wiring.