JPS5835372B2 - Electrostatic induction field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static induction field effect transistor (hereinafter referred to as SIT).
), it is related to the structure of
The purpose is to improve oscillation and amplification efficiency by increasing mutual conductance.

The operation and mechanism of conventional SIT is as follows.

The structure of a conventional SIT is shown in Figure 1.

In the figure, 5IT1 is a drain 2 made of an N-type low resistance semiconductor, an N-type high resistance layer 3, a north 4 made of an N-type low resistance semiconductor, a gate 5 made of a P-type low resistance semiconductor, a drain electrode 6, and a source electrode. 7, and Ge) are composed of 8 poles.

A drain bias power supply 9 is connected between the source 4 and the drain 20.
Therefore, a drain voltage is applied via the drain resistor 10.

When only the drain voltage is applied, electrons travel from the source 4 to the drain 2 through the high resistance layer 3, and a drain current flows.

On the other hand, the gate bias power supply 11 biases the gate junction 12 in the opposite direction, and when the gate voltage is applied, the depletion layer 13 expands from the gate junction 12 in the direction of the high resistance layer 3, causing a channel between the source 4 and the drain 20. 14 becomes narrower, making it difficult for electrons to travel.

Furthermore, when the gate bias is deepened, the channel 14 is pinched off by the depletion layer 13.

Here, the portion that is pinched off the earliest will be referred to as the pinch-off point.

When the channel 14 is pinched off, electrons cannot travel from the source 4 to the drain 2 unless the drain bias is increased, and the drain current hardly flows.

The potential energy distribution of electrons in this state is shown in FIGS. 2 and 3.

Figure 2 shows the potential energy distribution of electrons in a cross section from just below the source through the pinch-off point to the drain.The reason that electrons cannot travel from the source to the drain is that a potential barrier is formed and the pinch-off point This is because the potential energy of electrons near the point is high.

FIG. 3 shows the electron potential energy distribution in a cross section parallel to the main surface and passing through the Vincioff point.

In the above state, when the drain voltage is increased, the potential energy of electrons at the pinch-off point is lowered by electrostatic induction, allowing the electrons to cross the potential barrier at the pinch-off point and travel to the drain.

At this time, as shown in FIG. 3, the electrons reach the drain through the valley of potential energy near the center between the gates, that is, near the pinch-off point.

In the case of SIT, the relationship between drain voltage and drain current exhibits characteristics similar to those of a triode vacuum tube.

The above is an outline of the structure and operating mechanism of the SIT.

Generally, in order to improve the oscillation efficiency and amplification efficiency of the SIT, it is necessary to increase the mutual conductance (change in drain current/change in voltage) and to reduce the ineffective region.

In order to increase the transconductance, the gate region and It is necessary to narrow the spacing between the pinch-off points.

That is, it is necessary to make the gate interval as narrow as possible based on manufacturing technology.

However, in the conventional SIT, when the gate spacing is made as narrow as possible based on manufacturing technology, the level of specific resistance of the channel has an effect on the mutual conductance and the ineffective region as described below.

Figures 4 and 5 show SIT with high resistivity channel;
and drain current-drain voltage (I, -VD) characteristics of SIT with a low resistivity channel.

No. In other words, the gate voltage is VGo<1.
The relationship is VG11<1VG21<1VG31 (in the case of n-channel SIT, VG1 to 'VG3 are negative voltages, so the absolute values were compared).

Similarly, the shaded areas in FIGS. 4 and 5 are invalid areas.

This area not only does not contribute to the operation of the SIT, but also when the area becomes wide, the operating area becomes narrow, which becomes one of the factors that prevent high efficiency operation of 5ITO.

Further, for these SITs, the electron potential energy distribution in a cross section parallel to the main surface and passing through the pinch-off point is shown in FIG.

In Fig. 6, the diagonal lined area downward to the right and the shaded area downward to the left indicate the approximate width of the region where electrons flow in both SITs, and kT/q (where: Boltzmann's constant, T: absolute temperature) is calculated from the pinch-off point. , q: charge of one electron).

Note that here, the width of the region determined by kT/q will be referred to as the effective channel width.

In the case of an SIT with a high resistivity channel, the potential energy (potential barrier) of electrons at the pinch-off point as seen from the source is high, so when ■oo, the drain voltage required to start flowing the drain current becomes high, and the fourth As shown in the figure, there is a drawback that the invalid area becomes wider.

On the other hand, as shown in Fig. 6, the effective channel width (the lower left diagonal line) is wide, so the channel resistance is small.

−■. This has the advantage that the characteristics start up better and as a result, the mutual conductance becomes larger.

Next, in the case of SIT with a low resistivity channel, its ■.

−■. The characteristics, as shown in FIG. 5, do not pinch off in a region where the gate voltage is relatively low, so they exhibit voltage-controlled variable resistance characteristics, which has the advantage of narrowing the ineffective region.

On the other hand, as can be seen from FIG. 6, in the pinch-off state, the effective channel width (shaded area downward to the right) is narrow, so the channel resistance increases.

-■ This has the drawback that the rise of the o characteristic becomes poor, resulting in a decrease in mutual conductance.

In other words, in conventional SIT, if a high resistivity channel is used to widen the effective channel width, the ineffective region becomes wider, whereas if a low resistivity channel is used to narrow the ineffective region, the effective channel width becomes smaller. It had the disadvantage of having a contradictory relationship.

The present invention was made in order to alleviate such a trade-off relationship, and an object of the present invention is to provide a highly efficient SIT by providing a region having a specific resistance lower than that of the channel around the gate region. It is said that

An embodiment of the present invention is shown in FIG. 7 below.

The embodiment described here uses an N-type low resistance semiconductor as a first conductivity type semiconductor substrate, and a first conductivity type impurity selectively provided on the main surface of the substrate at a low concentration. an N-type high-resistance layer as a first region containing a P-type low-resistance semiconductor as a second region of a second conductivity type provided on the main surface of the first region of the base body; In an electrostatic induction field effect transistor using an N-type low resistance semiconductor as a third region containing a high concentration of the first conduction type impurity provided on the main surface of the first region, the first conduction type impurity is An N-type layer is used as a fourth region containing a relatively higher concentration than the base, and has a configuration that covers at least a portion of the second region in the base that faces the third region. .

In FIG. 7, 5IT21 includes a drain 22 made of an N-type low-resistance semiconductor, an N-type high-resistance layer 23, a source 24 made of an N-type low-resistance semiconductor, a gate 25 made of a P-type low-resistance semiconductor, and a gate 25 provided outside the gate 25. N-type layer 26, drain electrode 27, source electrode 28, and gate electrode 29
It consists of

A drain voltage is applied between the source 24 and the drain 220 by a drain bias power supply 30 via a drain resistor 31 .

Gate bias power supply 32 biases gate junction 33 in the opposite direction.

However, even if the gate bias power supply 32 is not applied, the depletion layer 34 expands due to the diffusion potential and the channel 35 is almost in a pinch-off state.

FIG. 8 shows a comparison of the electron potential energy distributions of the conventional SIT and the SIT according to the present invention.

In FIG. 8, the SIT according to the present invention differs from the conventional SIT in the electron potential distribution near the pinch-off point due to the influence of the N-type layer 26 provided on the outside of the gate 25, and after the pinch-off, the effective channel width decreases. It is wide, and moreover, the level at the pinch-off point is low when 'vGo'.

The results are shown in Figure 9 (thick solid line).

Since the -VD characteristic rises sharply and the drain voltage at the time when the drain current starts to flow becomes low, a highly efficient SIT with a large mutual conductance can be obtained.

Therefore, the oscillation efficiency and amplification efficiency of the SIT, that is, the electrostatic dielectric field effect transistor, can be improved.

Further, as shown in FIG. 10, the object of the present invention can also be achieved with an SIT having a structure in which the N-type layer is provided only on the side of the gate region facing the source.

Although the above description has been made with respect to a vertical junction type N-channel SIT, it is obvious that it can also be applied to a horizontal type, a Schottky barrier type, and a P-channel SIT.

[Brief explanation of drawings]

Fig. 1 shows the structure of a conventional SIT, Figs. 2 and 3 are graphs showing the electron potential energy distribution, and Fig. 4 shows the ID of the conventional high resistivity channel SIT.
-VD characteristic diagram, Figure 5 shows the conventional low resistivity channel SI
T's■. -VD characteristic diagram, FIG. 6 is a diagram showing a comparison of electron potential energy distributions for high resistivity channel SIT and low resistivity channel SIT, and FIG. 7 is a diagram showing the structure of SIT according to the present invention. Figure 8 is a diagram showing a comparison of the electron potential energy distribution of the conventional SIT and the SIT according to the present invention, and Figure 9 is a diagram showing the comparison of the electron potential energy distribution of the conventional SIT and the SIT of the present invention.
T and low resistivity channel SIT, and S according to the invention
■ of IT. -■ A comparison chart of o characteristics, FIG. 10, is a diagram showing another example. In FIG. 1, 1 is SIT, 2 is drain, 3 is high resistance layer, 4 is source, 5 is gate, 6 is drain electrode, 7
1 is a source electrode, 8 is a gate electrode, 9 is a drain bias power supply, 10 is a drain resistance, 11 is a gate bias power supply, 12 is a gate junction, 13 is a depletion layer, and 14 is a channel. In FIGS. 7 and 10, 21 is an S according to the present invention.
IT, 22 is a drain, 23 is a high resistance layer, 24 is a source, 25 is a gate, 26 is an N-type layer provided outside the gate 25, 2T is a drain electrode, 28 is a source electrode, 29
(game)! 30 is a drain bias power supply, 31 is a drain resistance, 32 is a gate bias power supply, 33 is a gate junction, 34 is a depletion layer, and 35 is a channel. The same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1 A semiconductor substrate of a first conductivity type, a first region containing a first conductivity type impurity at a low concentration selectively provided on the main surface of the substrate, and a first region containing a first conductivity type impurity at a low concentration on the main surface of the first region. A static induction field effect transistor having a second region of a second conductivity type provided and a third region containing a high concentration of impurity of the first conductivity type provided on the main surface of the first region. In the method, a fourth region containing the first conductivity type impurity at a relatively higher concentration than the substrate is configured to cover at least a portion of the second region in the substrate that faces the third region. An electrostatic induction field effect transistor featuring: