JPS5835411B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection device using volatile memory, which eliminates the need for a built-in battery for the memory circuit, and moreover ensures that the volatile memory receives a channel selection voltage after power is turned on. The purpose is to provide a channel selection device that can store information.

In a tuning device that stores and reads out the tuning voltage of an electronic tuner in the form of a binary signal in a digital memory, if EPROM, which is a non-volatile memory, is used as the digital memory, it is possible to receive each station sequentially when used at home. It is necessary to memorize the voltage, and the EPROM
Currently, it is not widely used because it is expensive and has reliability problems.

Also, in the case of EPROM, write. Even in MNOS, the erasing time is long at 100 m5eC each, and the time required for rewriting is also considerably long.

On the other hand, volatile memory requires 100 to 500 n for both writing and erasing.
Since it is sufficiently short at 5 ec, it is preferable to EPROM, but it has the disadvantage that it requires a constant supply of power, so a battery must be built into the receiver.

Therefore, the present invention aims to shorten the write time using a volatile memory, write every time the power is turned on, thereby eliminating the need for batteries and making the write operation more reliable. An example will be described with reference to the drawings.

In Fig. 1, 1 is an electronic tuner whose tuning frequency is controlled by applying DC voltage to a variable capacitance diode as a tuning element, 2 is a video intermediate frequency amplification circuit, 3 is a video detection circuit, and 6 is a synchronous separation and horizontal An oscillation AFC circuit, 7 is a deflection output circuit.

11 is a tuning voltage generation circuit for the tuner 1; 12 is a volatile memory that stores the tuning voltage as a 13-bit binary signal;
3 is a channel selection button that temporarily allows selection of 12 stations.

Note that 4 is a video signal output circuit, 5 is a color cathode ray tube, 8 is an audio carrier detection circuit, and 9 is a video carrier detection circuit.

1 to 7 are common to those of ordinary color television receivers.

10 is a local AFC time constant switching circuit of the AGC tuner.

14 is a tuning detection circuit, 15 is a search write control circuit of the present invention, 16 is a manual search switch, and 17 is a pulse generating circuit that generates a pulse output only once when the power switch is turned on.

The outline of the operation is as follows.

When the power switch is turned on, a pulse appears at the output of the pulse generation circuit 17 and drives the search write control circuit 15.
The volatile memory 12 and the tuning voltage generation circuit 11 are driven to change the tuning voltage of the tuner 1.

In the case of Japan, the VHF low band is first searched, so the video carrier of one channel is detected by the video carrier detection circuit 8 and transmitted to the tuning detection circuit 14.

The search write control circuit 15 uses the output of the tuning detection circuit 14.
The operation of the tuner 1 changes, the rate of change of the search voltage slows down, and the local frequency of the tuner 1 gradually increases.

When a voice carrier is detected by the voice carrier detection circuit 9, the search write control circuit 15 is controlled by the tuning detection circuit 14, and a binary signal corresponding to the current channel selection voltage is written into address 0 of the volatile memory 12. .

The above operation can be performed on VHF low band, high band and UH band.
Control voltages corresponding to receivable radio waves are sequentially written in the volatile memory 12 in the form of binary signals, and after the writing is completed, the binary signals of the contents of the memory address indicated by the channel selection button 13 are controlled by DC control. In addition to the voltage as a voltage, the desired radio wave is received by the tuner 1.

Next, automatic writing will be explained with reference to FIG.

First, if the time when the power switch is turned on or the search switch 16 is operated is 11, then at time t1, a pulse of the opposite polarity of φ1 in FIG. 3 is output from 16 or 17 in FIG. 2, and the NOR gate is activated. It is inverted at 18.

The output of the NOR gate 18 becomes φ1 in FIG.

This is transmitted to the flip-flop 21, and the flip-flop 21 is set.

When flip-flop 21 is set, its Q output goes low and gated oscillator 22 stops oscillating.

On the other hand, the output of the negative logic NOR gate 23 to which the Q output of the flip-flop 21 is added is the output of the flip-flop 2.
As shown in FIG. 3 φ2, since the Q output of 1 is at a high level between t1 and il1, it becomes high level and causes the gated oscillator 24 to oscillate.

The following description will be made assuming that the oscillation frequency of this oscillator 24 is 0.6 MHz for convenience.

25 counts the output pulses of this oscillator 24 13
This is a bit counter.

Since the CLR terminal of the counter 25 receives the Q output of the flip-flop 21 via the gate 27, the counter 25 does not perform a counting operation between t1 and tl1.

On the other hand, the output of the negative logic OR gate 26 which has the output of the NAND gate 31 as one input is connected to the write/read address circuit 20 and the write/read terminal of the volatile memory (16-power RAM) 12. There is.

Therefore, at the first bit of the output of the oscillator 24, the above
Since the NAND gate 31 is conductive, the contents of l10(1) to (16) are written to the volatile memory 12 at address oooo, as will be described later.

At this time, the output of the OR gate 28 to which the Q output of the flip-flop 21 is applied is at a high level, so the ANDN gate A to which the input of this OR gate 28 is applied
~29M is conductive and the other input of each gate is counter 25
Since the number of outputs is O, the outputs of 29A to 29M are 0.

In addition, since the three outputs of the band switching circuit 19 are O as described later, l10(1) to (16) of the volatile memory 12 are all O, and the 16-bit volatile memory 12 at address oooo
0 is written to.

Similarly, 0 is written to all memory elements of the volatile memory 12 16 times up to address 1111, and the contents of the volatile memory 12 are cleared.

At time tll, the address from the write/read address circuit 20 is ooo.

When the pulse indicating the return to is obtained, flip-flops 21 and 30 are reset.

When the flip-flop 21 is reset, its Q becomes high level and the gated oscillator 22 oscillates.

The oscillation frequency of the oscillator 22 is assumed to be I KHz.

The width T1 of one bit of the output of the oscillator 24 is 110.6ζ1
67μSeC, width T2 in 1 bit of IKHz
Since it is 1 m5ec, it becomes T2-600T1.

Now, when the output of the negative logic NOR gate 23 becomes low level at time 111, the oscillation of the oscillator 24 stops.

The pulse width of the output of the oscillator 22 is made narrower (16T, narrower) as shown in FIG.
Supply to the reset terminal of No.2.

When the flip-flop 32 is reset at <t21 as shown in FIGS. 3 and 4, its Q output becomes a high level as shown by φ4 in FIGS. 3 and 4, and Q becomes a low level.

Therefore, the output of gate 23 becomes high level and 24 oscillates again.

At this time, since the three inputs of the OR gate 27 are at a low level, the CLR input of the counter 25 becomes a low level, and the counter 25 counts the output of the oscillator 24.

33 is a 9-bit comparison circuit, and 34 is a 4-bit comparison circuit.As will be described later, only the output of the comparison circuit 33 is used except near the tuning point.

At t21, each output of volatile memory 12 is
Since the entire contents of 2 are O, the output is also O.

Note that since the output of the gate 26 remains at a high level, the volatile memory 12 is in a read state, and since addresses Ao-A3 are all O, 16 bits of address oooo are read out. All inputs of the comparison circuit 33 are zero.

As shown in FIG. 4, the output of the comparator circuit 33 is 1 until the counter 25 reaches 1 at time 125.

Therefore, the output of the comparison circuit 33 is transmitted to the J input of the flip-flop 32 via the AND gate 35 which receives the output of the comparison circuit 33 and further via the OR gate 37.

Since the output of the video carrier detection circuit 8 is at a low level, the AND gate 35 is turned on because the output of the inverter 36 is at a high level.

When 23 of the counter 25 changes from low to high at t21, 23
The AND gate 38 inputting the output of the inverter 3
It becomes conductive by the output of 6.

AND game) 38 and 39 are similar to the above-mentioned 29A to 29M, and conduct when the control input is high level, and when the control input is low level, the output becomes high impedance, and wired OR.
Can be combined.

Therefore, the output of the AND gate 38 is transmitted to the flip-flop 32 via the OR gate 140, and the flip-flop 32 is set when the 23 output of the counter 25 returns to O at 125, and the J input is 1 (K is Therefore, Q becomes 1 and Q becomes O.

When Q becomes 1, since both inputs of gate 23 are l, the output of gate 23 becomes 0 and oscillation of oscillator 24 stops.

At the same time, the monostable multi-bi break 41 is driven by the Q output of the flip-flop 32.

The output pulse width of the monostable multi-bibreak 41 is selected to be, for example, Boonse width.

The Q output of the monostable multi-bi break 41 passes through the OR gate 28 and is applied to the ANDN gates A to 29M, and the 13 outputs of the counter 25 are transmitted to the 13 /b of the volatile memory 12.

On the other hand, as will be described later, the output of the band switching circuit 19 at this time indicates the low band of vHF.■/□0.4)=11
■10(1,5)=■10 (16)0.

Therefore, it goes without saying that the tuner 1 is in a state of receiving the VHF low band.

The address at this time is <oooo as described later.

Therefore, the output of the counter 25 is 1 only for 23, and O to 0 for the others.
This is written to the volatile memory 12.

Reference numeral 42 designates a pulse generating circuit that clears the counter 25 after the output of the monostable multi-by-break 41, that is, the writing is completed, and is generated a little later than t25.

In this state, next φ3, that is, the output of the oscillator 22 is t3□
Wait until it is added to flip-flop 32.

At this time, the output voltage of the channel selection voltage generation circuit 11 is from t21 to t.
It is a DC voltage proportional to the width of the Q output pulse of the flip-flop 32 of No. 25.

At t3, when the flip-flop 32 is reset by φ3, the oscillator 24 oscillates again, and at time t3□ (shown in FIG. 4) when 16 outputs of the oscillator 24 have been counted, the output of the counter 25 (24 to 212) and the outputs l10(5) to l10(13) of the volatile memory 12 match, and the output of the comparator circuit 33 becomes high level, as shown at φ13 in FIG.

Therefore, the J input of the flip-flop 32 becomes high level through gates t-35 and 37, and the counter 25 outputs the signal at t35.
When the 25 output of 23 goes high, 23 changes from high to low and flip-flop 32 is set through gate 38.40.

At this time, the output of the counter 25 is 2420125=1.26
-O...... is written to the address oooo of the volatile memory 12 as described above.

In the following order, the output pulse of the oscillator 24 is set to 1 from the RAM output.
By counting 6 extra bits at a time, the output pulse width of the flip-flop 32 is widened, and the DC voltage generated by the channel selection voltage generation circuit 11 is changed.

The output of the video carrier detection circuit 9 at step 3 t4□, that is,
When the video carrier detection output becomes a high level and a video carrier is detected, a high level is transmitted to the J terminal of the flip-flop 43, the AND gate 44 becomes conductive, and the output of the AND gate 36 becomes a low level. is cut off (output is zero), and the output of the AND gate 38 becomes high impedance.

Therefore, the AND of comparators 33 and 34 is added to the J input of flip-flop 32 via AND gates 46 and 47.

That is, at t4□, the 24 to 212 outputs of the counter 25,
■/b(5) to a rib 5 of the volatile memory 12 match, and at this time, the 2° to 23 outputs of the counter 25 are zero, and I/Q(1
) to (4) are also zero.

(The previous write was the time when 23 of 25 went from high level to low level. The outputs of 23, 22, 21, 2 degrees were all O, and this was transmitted to l10 (1) to (4) of volatile memory 12. Therefore, the output of the comparison circuit 34 from 145 also detects a match and becomes high level.

Therefore, the output of AND gate 46 becomes high level.

This is because the Q output of the flip-flop 30 is at a low level, so the output of the inverter 48 is at a high level, and the AND gate 4
Since the output of the gate 4 is at a high level and the output of the OR gate 45 is at a high level, all three outputs of the AND gate 46 are at a high level.

Since the output of the video carrier detection circuit 9 is at a high level, the AND game'
- gate 4T also becomes conductive, and the J input of flip-flop 32 from l45 becomes high level through OR gate 37.

On the other hand, AND gate 38 is blocked and AND gate 39
conducts, so the next output of the oscillator 24 (after 1 bit)
Flip-flop 32 is set to .

FIG. 5 shows an enlarged view of FIG. 4. As is clear from the figure,
When the output of the video carrier detection circuit 9 becomes high level, t
4, ~t45 is the width of the previous φ4, 145~t4
6, that is, φ4 is increased by 1 bit.

That is, when the output of the video carrier detection circuit 9 is detected, the pulse width of the flip-flop 32 is widened by one bit.

As a supplementary note, a write pulse is generated after l46, writes 1 of the 2° output of the counter 25, and is then cleared, so that 1 is written to l10(1) of the volatile memory 12.

In the next cycle, the output of the comparison circuit 33 becomes high level at l45, but the output of the comparison circuit 34 becomes high level at l46, so φ4 is expanded by 1 bit.

That is, after the output of the video carrier detection circuit 9 appears, the pulse width of the flip-flop 32 increases by one bit.

Therefore, the direct current voltage of the channel selection voltage generation circuit 11 also increases by %, and the change in the local frequency of the tuner becomes smaller, making it easier to find the audio carrier.

After t4□, the pulse width of 32 becomes wider by ■ bits until the output of 8 appears.

When the output of the audio carrier detection circuit 8 becomes low level at l50, the flip-flop 43 becomes high level and the AND gate 50 becomes conductive.
The output of 0 is at a high level as φ8, and the falling edge of l56 generates a write pulse at l58.

Note that at l56, as described above, the write pulse of the output of the monostable multivibrator 41 is generated.

That is, the address oooo is written with the output pulse of the monostable multi-bi break 41, and the next address 0001 is written with φ9.

Details of these will be described later.

In the above explanation, after the voice carrier is detected, the output of the counter 25 is written after the pulse width of the 1-bit flip-flop 0 flip-flop 032 is further widened, but even when reading, the output is 1 bit wider than the content of the volatile memory 12, so there is no problem. .

As mentioned above, if the voltage is changed slowly until the audio carrier is detected, it is possible to keep the time constants of AGC and AFC the same as those of a normal television receiver.

By the means described above, first, the tuning frequencies of two stations (or one station) of the VHF low band are converted into binary signals in the volatile memory 1.
2.

The maximum value of the output voltage of the channel selection voltage generation circuit 11 is determined by the counter 2.
When counting 213 pulses in 5, the number of pulses is 8192.
If the voltage at this time is 32V and the three stations in the VHF band are spaced approximately at equal intervals, then they will be tuned every 2048 bits.

Therefore, the 3rd channel is around 6134 bits, but as mentioned above, the number of pulses is divided into 512 bits and 16 bits, and if you count φ3 about 384 times (384 x 16 bits), it will be 6314 bits, so up to the 3rd channel. The time required is 1.6ms (excluding writing) x 384=
It becomes 614m5eC.

The same goes for VHF high band writing, and assuming that 192 channels of 4 to 12 channels are equally spaced, /1°28
19.2 bits or 51.2x16 is 19 per channel
The number of bits is 2.

For UHF 153 bits 155 bits or 9.6
It becomes 6X16.

In UHF, a change of 6 MHz is covered by 155 bits, so one bit of output from the oscillator 24 is approximately 39 kHz.

The 4.5M band corresponds to approximately 116 bits. That is, if the time difference between the detection of the video carrier and the tuner DC control voltage is zero, the audio carrier will be detected by counting 116 φ3, which corresponds to 116×j−ζ116 m sec.

However, in reality, there is a delay of about several +103 m5ec, so there is no need to count as many as 116 φ3, and an audio carrier can be obtained by counting 50 to 60.

If you count 116 pieces and write 5 channels with IJHF, the sweep time will be approximately 512 x 1 m5eC, 5
The sum of X 116=580m3ec, that is, U in about 1.1 seconds
can be written.

Since the VHF high band is 6 MHz = 819.2 bits, the 4.5M band is 614 bits.

Therefore, tuning cannot be achieved unless approximately 550 φ3s are counted.

Therefore, to write 5 stations, the sweep time is 512 m5eC and 6
14×5=3.58 seconds are required.

Considering the VHF low band in the same way, 6M=20
48→4.5M1.536 bits, therefore 512m5e
c and 1.536 x 2 seconds are required, and the total time for UHF and VHF is 512 x 3 + 580 + 3.582 + 3.072
=8190m 5ecJ208.2 seconds are required.

As described above, all received radio waves can be preset in about 8.2 seconds without any special measures.

To read it next time, if you press the sixth button from the top at 13, the output of the channel selection button 13 will be 5 in binary, ie 0101, and the address of the volatile memory 12 will be A.

2A2=1, A1-A3-0.

If 10 channels of VHF were written in the sixth place from the top, the binary number indicating 6554 would be l10.
(1) to α3).

That is, 212, 211, 28, and 27°24 are 1, which is transmitted to the comparison circuits 33 and 34.

On the other hand, at the end of the search, the Q of the flip-flop 30 is at a high level, so the output of the OR gate 45 is at a high level, and during one cycle of φ3 in FIG.
It continues to increase up to 554, and the first time the output of the video carrier detection circuit 9 is detected and the AND gate 35 is cut off.
The flip-flop 32 is set at t46 in FIG. remains cut off, and when both the comparison circuits 33 and 34 become high level, that is, after 6554 pulses are detected, the J terminal of the flip-flop 32 becomes high level.

Therefore, a normal tuning voltage is obtained from the output of the tuning voltage generation circuit 11 from the second cycle of φ3 onwards.

The above explanation of the main parts of the operation is complete, but a supplementary explanation of the operation of each part will be given below.

First, address switching will be explained.

The contents of the write/read address circuit 20 are shown in FIG.

First, from time t1 to tll in FIG. 3, the Q of the flip-flop 21 is at a high level as shown by φ2, so NO
The ROR gate 20G4 force is at a low level and selector 2
The output of O8 becomes the A input.

On the other hand, the output of the OR gate 26 is the output 24, as shown in FIG.

The counter 20C counts every 1 bit of .

20C is a count release from tl, and the output of oscillator 24 is 1.
Up to 6 pieces are φ.

Count one bit at a time.

That is, since the Q of the flip-flop 21 is at a high level, the AND gate 20G5 becomes conductive, and the N
The output of the AND gate 31, ie, the output of the oscillator 24, is transmitted.

When counting 16, 24 becomes high level, the output of NAND gate 20G1 becomes low level, flip-flop 21 is cleared, and flip-flop 30 is also cleared.

This time is 111. The Q of the flip-flop 30 is shown at φ5 in FIG.

Note that if writing into the volatile memory 12 requires time, a delay circuit may be inserted between the output of the gate 26 and the counter 20C.

Next, when the Q of the flip-flop 31 becomes high level φ, the selector 20S outputs the A input, and the flip-flop 2
Since the bean number 1 is at a high level, the AND game 120G6 becomes conductive.

Until synchronization is achieved, the gate 2 is stored in the volatile memory 12 as described above.
After continuing writing with the output of 6 and detecting the audio carrier,
φ8 in FIG. 3 appears at the output of the AND gate 50, and l56
The monostable multivibrake 20M1 triggers the trigger groove 2.
The output of 0M1 is transmitted to counter 20C.

On the other hand, at 156, the output of the gate 26 is transmitted to the volatile memory 12 via the gate 20G3, so the output of the counter 25 is first written at address oooo, and the counter 20C becomes 0001. Monostable multi-bi break 20 at the end of M1 to monostable multi-bi break 20
M2 is triggered and the same content is written to address ooo i.

Next, when φ3 comes, the address 0 is sent to the comparator circuit 33 in FIG.
The contents of 001 are read out, and the pulse width increases by 16 bits from there.

Similarly, when all writing is completed and the flip-flop 31 is set, the selector selects the B input.

Also, the output of the inverter 20G9 becomes low level, and the NAND
The gate 1-2008 is cut off and becomes a high bell, and the volatile memory 12 is always in a read state.

Next, band switching will be explained.

FIG. 7 shows the contents of the band switching circuit 19, t1 to tl
During the clearing period of 1, the Q of the flip-flop 21 is applied to the negative logic OR gate 19G10, and the flip-flop 1
Both 9FA and 19FB are cleared, and the negative logic NOR gate 19G1 outputs Ill and AND gate-1.
19G2 and 19G3 are output "O" and the write pulse is inverted by the inverter 1908, so 100 is input to the volatile memory 12.
That is, the low band of VHF is written.

Note that 19G5 to 19Gγ are the same AN as 29A to 29M.
This is the D gate.

Next, in the search state after tll, the NOR gate 20G
Since the output of the tuner 2 is at a low level as described above, the output of the tuner 19S becomes the A input, and the tuner 1 receives the VHF low band.

When the upper end of the VHF low band is reached, the counter 25
13 appears, and the counter 25 is cleared via the buffer amplifier 49 and OR gate 27, so 21
The third output is a narrow width pulse.

At the end of this pulse, flip-flop 19FA is set, Q becomes 1, Q becomes O, and AND gate 19G2
Only then, the output becomes "1", and the next output becomes VHF high band.

When the 213 output appears again, 19FB is set, and only the output of AND game I-1903 becomes high level to receive UHF.

When the output of AND gate 119G3 is "1", that is, UH
When 213 output appears at F, NAND gate-419G
The output of 4 becomes negative, setting the flip-flop 30 and clearing the flip-flops 19FA and 19FB, thus completing the writing.

During reading, the AND gates 19G5 to 19G7 become high impedance, and the gate 19S outputs the B input, so that the tuner 1 receives the I/O signal from the volatile memory 12.

(14) to (L6) are transmitted.

Next, voltage generation proportional to the pulse width will be explained.

As shown in FIG. 8, the output of the flip-flop 32 is transmitted to a switching transistor 52 via a resistor 51.

53 is a load of the transistor 52 and is a load of the transistor 52.
This resistor determines the base bias of 5.

When the transistor 52 becomes conductive for the Q output of the flip-flop 32, that is, the period φ4 in FIG. 3, the collector potential decreases and the transistor 55 becomes conductive.

However, resistors 53 and 5 are connected so that the transistor 55 does not become saturated.
Decide on the value of 4.

At this time, a charge proportional to the pulse width is stored in the capacitor 56, and the potential thereof is shown in FIG. 9A.

Considering the vicinity of tn, the previous charge is discharged by the field effect transistor 58, and thereafter charging starts from tm, and the pulse width is expanded by tn5 to to6 (16 bits or 1 bit) from the previous time, and the both ends of the capacitor 56 are expanded by that amount. The potential of increases.

On the other hand, if the potential drop of the diode 57 is ignored for the capacitor 59, the voltage is ■.

, are stored and t.

■ at 5. -1 or more, the diode 57 becomes conductive,
Current also flows into the capacitor 59, and the potential of the capacitor 59 rises to vn.

At to6, the transistors 52 and 55 are turned off.At this time, the output of the gate 26 triggers the mono-multi-by-break 66, and the field effect transistor 58 conducts for a short time, so that the capacitor 56 is no longer charged.

If this is repeated, the potential of the capacitor 59 continues to rise.

61 is a field effect transistor with high impedance that takes out the potential of the capacitor 59; 62 is a source resistance; 63 is an integrating resistor; and 64 is an integrating capacitor.

On the other hand, the transistor 60 is turned on for a short time by the output of the mono-multi-by-break 67 at the time of band switching and at the start of writing, and discharges the charge in the capacitor 59.

Next, when reading data from the volatile memory 12, the channel selection button 13 is operated, so the switching of the channel selection button 13 is detected, the capacitor 59 is discharged, and the potential proportional to the output of the flip-flop 32 is changed to 56. , 59.

The output of the flip-flop 32 is obtained with the same width at intervals of φ3, the potentials of the capacitors 56 and 59 are constant, and the tuner 1
A control voltage corresponding to the data in the volatile memory 12 is supplied to the device, and a designated radio wave is received.

As described above, according to the present invention, all receivable channels can be written in a short time of about 8 seconds each time the power switch is turned on, so there is no need for the receiver to preset it, and volatile memory can be used. Therefore, it is low cost and does not require a built-in battery.

Further, in the present invention, a flip-flop that is inverted by the first gated oscillator, a second gated oscillator that operates while this flip-flop is inverted, and an output of this second gated oscillator are counted. The circuit includes a counter and a search write circuit that writes the output of the counter to a volatile memory and returns the flip-flop when both a video carrier and an audio carrier are detected. By generating the tuning voltage accordingly, it is possible to easily operate the tuning voltage according to the counter output and apply it to the tuner without using a complicated -A conversion circuit.

Furthermore, since the vicinity of the tuning point is slowly swept, it has the advantage that the AFC time constant of the AGC tuner can be used at its normal value.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a channel selection device according to an embodiment of the present invention, FIG. 2 is a specific block diagram of main parts of the device,
FIGS. 3, 4, and 5 are time charts for explaining the device, and FIGS. 6 and 7. FIG. 8 is a more specific block diagram of a part of the device,
FIG. 9 is a waveform diagram for explaining the device. 1... Tuner, 12... Volatile memory, 15... Search write control circuit, 17...
...Pulse generation circuit, 13...Tuition selection button,
8...Audio carrier detection circuit, 9...
Counter, 33, 34... Comparison circuit, 24, 2
2...Oscillator, 21, 32...Flip-flop.

Claims (1)

[Claims] 1. A tuner using a variable capacitance diode as a tuning element, a tuning voltage generation circuit that generates a DC voltage corresponding to each channel and supplies this DC voltage to the variable capacitance diode of the tuner, and a volatile memory that stores binary signals, a first gated oscillator that starts operating each time the power is turned on or a manual switch is operated, a flip-flop that is inverted by the output of this gated oscillator, and this flip-flop that is inverted. a second gated oscillator that operates during a period of time, a counter that creates the binary signal by counting the output of the second gated oscillator, and a video carrier and an audio carrier of the received television signal. a search write circuit that writes the count output of the counter to the volatile memory and resets the flip-flop when both are detected; In addition, the search write control circuit includes a means for significantly changing the pulse width of the output of the flip-flop at a constant cycle, and a constant cycle. and a means for changing the pulse width in a small width at a constant period, and switching the pulse width from a means for changing the pulse width significantly at a constant cycle to a means for changing the pulse width in a small width at a constant cycle when a video carrier is detected in the received signal of the tuner. Tuning device.