JPS5845858B2 - Synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency synthesizer that prevents malfunction of a counter that divides the oscillation signal of a voltage controlled oscillator.

Oscillators used in transceivers with multiple channels, such as transceivers, need to oscillate many different frequency signals, but in recent years, such oscillators have been developed using controlled signals obtained by dividing the oscillation signal of a voltage controlled oscillator and crystal oscillators. A control signal is obtained by comparing the standard reference signal obtained from the oscillation signal with a comparator such as a phase detector, and the control signal controls the voltage controlled oscillator to achieve the desired oscillation frequency in an equilibrium state. A frequency synthesizer is used.

In such a frequency synthesizer, in order to obtain an oscillation frequency output signal compatible with multiple channels, a program counter consisting of an MO8 type transistor is used as a frequency dividing means for the oscillation signal from the voltage controlled oscillator. If the output frequency of the voltage controlled oscillator becomes abnormally high, such as when the MOS
) When the operating limit of the Run Sister is exceeded and the program counter malfunctions, the output signal is lower than the frequency obtained by normal frequency division, and the output signal becomes lower than the divided output of the oscillation signal of the crystal oscillator. A malfunction state in which the control signal from the voltage-controlled oscillator acts to further increase the oscillation frequency of the voltage-controlled oscillator, the feedback effect as a system is lost, and an output signal with a frequency fixed at its upper limit frequency is extracted from the voltage-controlled oscillator. become.

In order to eliminate this drawback, the present invention applies a reference signal obtained by dividing the output signal of the program counter and the output of the crystal oscillator to the phase comparator under normal operating conditions to obtain a control signal. When the voltage-controlled oscillator reaches the maximum allowable limit value or exceeds it and malfunctions, a signal with a frequency much higher than the output signal from the program counter is applied in place of the output signal from the program counter. To provide a frequency synthesizer which prevents malfunction by obtaining a control signal that drastically lowers the oscillation frequency of a program counter and thereby controlling a voltage controlled oscillator to forcibly return it to a stable operating area of a program counter.

Furthermore, the present invention is not limited to the MO8 type program counter;
The present invention provides a frequency synthesizer that effectively prevents malfunction even in a frequency synthesizer in which the operating frequency range of a counter that divides the output of the voltage controlled oscillator is narrower than that of the voltage controlled oscillator.

The present invention will be explained below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a voltage controlled oscillator whose oscillation frequency is changed depending on the magnitude of the applied control signal.
It is taken out.

The output signal of the voltage controlled oscillator 1 is supplied to a first mixer 3, where it is mixed with the output signal from the first crystal oscillator 4 to obtain an output signal at the output terminal fR.

In the transmitter/receiver, the output signal from the output terminal fT is used as a carrier wave signal during transmission, and the output signal from the output terminal fR is used as a local oscillation signal of the mixing stage during reception.

Furthermore, the output signal from the voltage controlled oscillator 1 is supplied to a second mixer 5, where it is mixed with the signal from the second crystal oscillator 6.

7 is a reference counter that uses the T/R signal from the T/R switching circuit 8 to make the frequency division ratio different during transmission and reception, and divides the oscillation frequency of the first crystal oscillator 4 to maintain a constant value depending on each case. Generates a frequency reference signal.

9 is a program counter, and channel designation circuit 10
The frequency division ratio is switched to a frequency division ratio corresponding to each channel of the transmitter/receiver, and similarly to the above, the T/R switching circuit 8 controls the frequency division ratio to be different between the button at the time of transmission and the time of reception.

Therefore, the program counter 9 divides the output signal of the second mixer 5 to generate a controlled signal that approximates the frequency of the reference signal.

11 is the first . Second AND circuits 12, 13, the first
．． A gate circuit consisting of an inverter circuit 14 and an OR circuit 15 connected between the second AND circuits 12 and 13. The input terminals of the second AND circuit 12 and 13 are connected directly or via the inverter circuit 14 to the operating limit detector 16, and the other input terminals of the first AND circuit 12 are connected to the controlled signal output of the program counter 9. The other input terminal of the second AND circuit 13 is the reference counter 7.
It is connected to the stage before the final stage.

Further, the operating limit detector 16 includes a reference counter 7 and a program counter 9 as shown in FIG.
One-shot multivibrator connected to = 17,
1B, the one-shot multivibrator-17, Ia
A pair of MO8 type transistors 19, 20 that are turned on and off by the output signal of the MO8 type transistor 19,
When the capacitor 21 is charged and discharged by turning on and off the capacitor 20 and the charging pressure of the capacitor 21 reaches a predetermined value,
It consists of a Schmitt circuit 22 that generates pulses.

Since the frequency of the signal supplied from the program counter 9 to the one-shot multivibrator 18 during normal operation is selected to be greater than the frequency of the signal supplied from the reference counter 7 to the one-shot multivibrator 17, During that time, the charge discharged from the capacitor 21 while the MO8 type transistor 19 is on is greater than the charge charged in the capacitor 21 while the MO8 type transistor 20 is on, so the charging voltage of the capacitor 21 is determined by the Schmitt circuit. 22, but the program counter 9 malfunctions and the frequency of its output signal drops extremely, becoming lower than the frequency of the signal from the reference counter 7. Since the electric charge charged to the capacitor 21 is larger than the electric field discharged from the capacitor 21 while the MO8 type transistor 19 is on, the charging voltage of the capacitor 20 is larger than the operating voltage of the Schmitt circuit 22, and the output signal is arise.

That is, this point becomes the detection point of the limit detector.

This situation is illustrated by waveform A in Figure 3, and waveform opening is M.
Waveform C indicates the on time of the O8 type transistor 20.
The on-time of the transistor 19 is shown.

A comparator 23 compares the frequencies from the gate circuit 11 and the reference counter 7, and when the frequency of the signal from the gate circuit 11 is higher than the frequency of the signal from the reference counter 7, it generates a positive signal according to the frequency difference. , conversely, when it is low, it produces a negative signal.

24 is a low-pass filter that filters the output signal detected by the comparator 23, and the low-pass filter 24 supplies a DC voltage to the controlled oscillator 1 according to the positive or negative signal from the comparator 23, and controls its oscillation. Controls the frequency to lower or raise it, forming a feedback loop.

Next, the operation of the present invention will be explained.

(1) A case will be described in which the present frequency synthesizer is used as a local oscillation signal generator for a transceiver.

In this case, the reception frequency of the transceiver is 26.965MHz ~
27.255MHz, and the intermediate frequency is 10.69
It is set to 5MHz.

Therefore, the output terminal fR has 37.66 MHz depending on the receiving frequency.
It is necessary to obtain an output signal of ~37.95MHz.

By the way, the output signal of the output terminal fR is obtained by mixing the first crystal oscillator 4 and the voltage controlled oscillator 1.
The crystal oscillator 4 has an oscillation frequency of 10.24MH
z is constant, the control voltage of the voltage controlled oscillator 1 may be controlled so that the oscillation frequency of the voltage controlled oscillator 1 varies from 27.42 MHz to 27.71 MHz.

The method will be explained below.

Assume that all transceivers are receiving a 26.965 MHz signal.

In order to obtain an intermediate frequency signal of 10.695 MHz from the received signal, the frequency of the signal supplied from the output terminal fR needs to be 37.660 MHz.

For this purpose, the oscillation frequency of voltage controlled oscillator 1 is 27.4
Must be 2MHz.

If the voltage controlled oscillator 1 is correctly oscillating 27.42 MHz, its oscillation output signal is mixed with the 25.76 MHz oscillation signal of the second crystal oscillator 6 in the second mixer 5, and the difference between these frequencies is Generates a certain 1.66MHz signal.

The signal is frequency-divided by the program counter 9.

At this time, the frequency division ratio of the program counter 9 is set to 1/166 because the T/R switching circuit 8 is set to the R side and the channel designation circuit 10 is switched according to the receiving channel.
It is being done.

Therefore, the frequency of the controlled signal divided by the program counter 9 becomes 10 KHz.

On the other hand, at this time, the frequency division ratio of the reference counter 7 is 1/
Since it is set to 1024, reference counter 7
A reference signal of 10 KHz can be obtained.

This frequency remains unchanged as long as the T/R switching circuit 8 is on the R side.

Also, at this time, since the frequency of the signal from the program counter 9 applied to the operating limit detector 16 is higher than the frequency of the signal from the reference counter 7, the operating limit detector 16 does not output an output, and the controlled signal from the program counter 9 is supplied to the comparator 23 through the first AND circuit 12 and the OR circuit 15.

In this case, if the frequency and wave number oscillated by the voltage controlled oscillator 1 are as described above (27, 42 MHz), the comparator 2
The frequencies of the signals supplied to the voltage controlled oscillator 1 are both equal to 10 KHz, and no control signal in either the positive or negative direction is generated by the comparator 23. Therefore, no control signal is applied to the voltage controlled oscillator 1, and the frequency of the voltage controlled oscillator 1 is maintained in a balanced state. continues to oscillate.

By the way, due to changes in voltage or temperature, the voltage controlled oscillator 1
When the oscillation frequency of the comparator 230 changes, the output frequency of the second mixer 5 changes accordingly, so the output frequency of the program counter 9 also changes, causing a frequency difference in the input signal of the comparator 230.

Thereby, a control signal is generated at the output of the comparator 23 according to the frequency difference, and the oscillation frequency of the voltage controlled oscillator 1 is corrected.

In this way, when the fluctuation in the frequency of the voltage controlled oscillator 10 is small, it can be sufficiently corrected, but if the frequency of the voltage controlled oscillator 1 changes to an abnormally high level due to noise during switch switching, etc., the program counter 9 is configured. MO8
If the frequency limit of the type transistor is exceeded, the program counter 9 may miscount or stop completely.

As a result, the frequency of the signal supplied from the program counter 9 to the operating limit detector 16 may become extremely low.
Or if it runs out, the operating limit detector 16
The charging voltage of the capacitor 21 inside becomes high, and a signal is generated from the Schott circuit 22.

That is, when the detection point of the operation limit detector is reached, the signal is supplied to the second AND circuit 13 in the gate circuit 11, and the second
The AND circuit 13 is turned on and the first AND circuit 12 is turned off.

Therefore, a high frequency signal from the reference counter 7 passes through the gate circuit 11 and is applied to the comparator 23.

Therefore, the frequency difference between the input signals applied to the comparator 23 is large, and the fact that the input frequency of the program counter 9 has been increased is emphasized, resulting in a larger positive control signal than the comparator 23.

The control signal lowers the oscillation frequency of the voltage controlled oscillator 1 to near the lower limit of its stable operation range, so that the voltage controlled oscillator frequency exceeds the operating limit of the program counter 9 and loses its feedback function. There is no.

When the channel designation circuit 10 is switched in conjunction with the switching of the receiving channel of the transmitter/receiver, the frequency division ratio of the program counter 9 is switched, so that the frequency from the program counter 9 varies from the frequency of 10 KHz.

The variation is taken out as a positive or negative control signal by the comparator 23 to control the oscillation frequency of the voltage controlled oscillator 1 to reach an equilibrium state without any positive or negative control signal, and the output terminal fR corresponds to the receiving channel. Generates a local oscillator signal.

(2) A case will be described in which the present frequency synthesizer is used as a carrier signal generator of a transmitter/receiver.

In this case, since the output signal of the output terminal fT becomes the carrier wave of the first transceiver, the frequency of the output signal of the output terminal fT must be 26.965 to 27.255 MHz.

Therefore, the oscillation frequency of the voltage controlled oscillator 1 must also be the same.

Therefore, the T/R switching circuit 8 is set to the T side, and the channel designation circuit 10 is switched to the highest frequency channel, for example.

Then, the division ratio of program counter 9 is 1/241.
becomes.

In this case, if voltage controlled oscillator 1 correctly outputs 27.255
If oscillating at MHz, the second crystal oscillator 5
Since the oscillation frequency of is <25.76MHz as before, the oscillation frequency of the output signal of the second mixer 5 is 1.495MHz.
Hz, so the frequency of the controlled signal from the program counter 9 is 5 KHz.

Also, since the frequency division ratio of the reference counter 7 is set to 1/2048 by the T/R switching circuit, the frequency of the output signal of the reference counter 7 is also 5 KHz, so no control signal is generated from the comparator 23. .

However, when the frequency of the voltage controlled oscillator 10 fluctuates, the frequency of the output signal of the program counter 9 deviates from 5 KHz, so a frequency difference occurs in the input signal applied to the comparator 23 through the gate circuit 11, and a corresponding control signal is generated. Correctly correct the oscillation frequency of the voltage controlled oscillator 1.

Also, when the oscillation frequency of the voltage controlled oscillator 1 fluctuates abnormally, a signal is generated from the operation limit detector 16 as described above.
Since the gate circuit 11 is switched and a signal with a higher frequency than the reference counter 7 is supplied to the comparator 23, a larger control signal than the comparator 23 is obtained and the voltage controlled oscillator 1
Correct the oscillation frequency.

To further switch channels, channel designation circuit 1
0 and changing the frequency division ratio of the program counter 9 in the same manner as described above.

Above, we have described in detail the case of using an operation limit detector that activates when the frequency of the program counter exceeds the maximum allowable limit value and malfunctions, but the detection point is set at a frequency slightly lower than the maximum allowable limit value of the program counter. In exactly the same way as described above, when the input frequency to the program counter reaches the detection point, the output signal of the operating limit detector is By forcibly switching the signal from the program counter to the comparator to a signal with a higher frequency than the reference signal when the limit value is exceeded, the frequency is always operated within a stable operating range. Synthesizer can be changed.

Furthermore, when the allowable operating frequency of the program counter has the highest value, such as when using MOS dynadic logic for the program counter, an operating limit detector that emits an output signal when the allowable operating frequency reaches a slightly higher value than the allowable lower limit value is installed. By using the output signal, the signal from the program counter to the comparator is forcibly switched to a lower frequency than the reference signal, and the frequency of the voltage controlled oscillator is raised in the stability region 1 of the program counter, thereby preventing malfunction. You can get a frequency synthesizer.

As described above, in the frequency synthesizer of the present invention, when the oscillation frequency of the voltage controlled oscillator reaches near the upper or lower limit of the operation of the counter that divides the oscillation signal of the voltage controlled oscillator, the input is applied from the counter to the comparator. Since the signal is forced to switch to a higher or lower frequency than the reference signal, a large control signal is obtained from the comparator and pulls the voltage controlled oscillator back out of its stable operating region.

Therefore, the voltage controlled oscillator always operates stably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the frequency synthesizer of the present invention,
FIG. 2 is a circuit diagram showing one implementation of the operating limit detector used in the present invention, and FIG. 3 is a waveform diagram of each part of FIG. 2. 1... Voltage controlled oscillator, 2... Buffer fR... Output terminal, fT... Output terminal, 3... First mixer , 4... 1st
Local oscillator, 5...Second mixer, 6...
・Second local oscillator, 7...Reference counter, 8...T/R switching circuit, 9...
Program counter, 10...Channel switching circuit, 11...Gate circuit, 16...
- Operating limit detector, 23... Comparator.

Claims (1)

[Claims] 1. A counter that divides the oscillation signal of a voltage controlled oscillator, a reference signal source that generates a reference signal having a reference frequency, and the output signal frequencies of the counter and reference signal source are compared and the phase difference or frequency difference is determined. a comparator that generates a corresponding control signal, and a detection means having a detection point near the operating limit of the counter, the detection means detecting that the oscillation frequency of the voltage controlled oscillator reaches the detection point, Forcibly switching the signal supplied from the counter to the comparator to a predetermined frequency signal, and forcibly correcting the oscillation frequency of the voltage controlled oscillator to a stable operation region of the counter using the control signal from the comparator. A frequency synthesizer featuring