JPS5846851B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate type semiconductor device, and particularly to a MOS IC having a silicon gate structure.

Insulated gate semiconductor devices have a structure in which the surface charge of the semiconductor is controlled by a gate electrode via an insulator.
In particular, the characteristics of the semiconductor surface are important.

The inventor analyzed the leakage defects that tend to occur due to variations in the semiconductor surface characteristics, and found that the leakage defects were mainly caused by contamination during the aluminum vapor deposition process for forming electrodes and wiring.

The dirt is particularly large in the bonding pad area.

That is, the thermally oxidized SiO2 film 2 covering the silicon substrate 1
Upper membrane type Upper membrane type Upper aluminum bonding pad 3
In the vicinity of pad 3 and internal interconnections (not shown)
During aluminum evaporation to form the aluminum 3, it becomes contaminated by positive ions such as Na+ ions, and the contaminated ions enter the oxide@2, thus creating an inversion layer 4 on the surface of the substrate 1, resulting in flattening of that part. . . . The band voltage V falls, and the threshold voltage VthB fluctuates (see FIG. 1).

In FIG. 1, 5 is a phosphorous silicate glass (PSG) film covering the oxide film 2, and 6 is a CVD 5in2 film formed on the substrate 1 in the same amount as the pad 3.

Therefore, in order to find out what kind of structure is best to use to prevent such fluctuations in th, the following (A) to [
VF when the aluminum pad 3 is contaminated in each case.
I checked B.

(A) Same as in Fig. 1 above, but with CVD SiO
The ends of the two membranes 6 do not reach above the aluminum pads 3.

[FIG. 2 A''l VFB=-50V0 (B) A aluminum pad 3 is formed on the upper surface of the PSG film 5 covering the thermally oxidized 5i02 film 2.

[Figure 2 B''] vFB=-6V (C) Same as Figure 1 above, but with aluminum
The PSG film 5 is not formed under the periphery of the pad 30.

[Figure 2C] VFB=-12vrIjr Thermal oxidation s
A polycrystalline silicon layer 7 is formed above the iOJ Z and below the aluminum pad 3.

[Figure 2D) VFB=-4v0 (5) Same as above, but with aluminum pad 3
A PSG film 5 is interposed between the polycrystalline silicon 7 and the polycrystalline silicon 7.

[FIG. 2E], VFB=OVIVI is a parameter for the degree of contamination, and from these results it can be seen that the above case E can prevent contamination from the bonding pad 3 most efficiently.

The present invention was born from the above experimental results, and its purpose is to prevent contamination from the aluminum bonding pad 3 as described above and to stabilize device characteristics.

The gist of the present invention for achieving the above object is to provide a first insulating film formed on a semiconductor surface, a polycrystalline silicon layer selectively formed on the first insulating film, and a polycrystalline silicon layer selectively formed on the first insulating film. a second insulating film doped with phosphorus formed on the silicon layer and the first insulating film; and a second insulating film doped with phosphorus formed on the silicon layer and the first insulating film;
A semiconductor device is characterized in that it has a bonding pad formed on an insulating film.

In this case, it is necessary to provide a layer containing phosphorus between the aluminum pad 3 and the first insulating film 2, thereby preventing surface inversion caused by contaminant ions entering from the aluminum pad 3. can do.

Therefore, the second insulating film 5 and/or the polycrystalline silicon 7 are doped with phosphorus.

Hereinafter, a specific manufacturing method for obtaining the structure of the present invention will be explained.

FIG. 3 a' to e show C-MOS (Complementary Metal-oxide
A process diagram when applied to an e-semiconductor is shown.

(a) N-type silicon substrate (<100>, 2Ωcrn
) 11, and of the thermally oxidized 5i02 film (8500X thickness) 12 on the substrate 11, portions corresponding to the source, drain, and gate portions are selectively removed.

(b) By heat-treating the substrate 11, a SiO□ film (0.1 to 0.2 am thick) for forming a gate insulating film is formed.
Further, polycrystalline silicon films (0.4 to 0.5 μm thick) for forming gate electrodes are formed thereon by the CVD method, and then gates 9a and 9b are formed by photoetching the silicon films.

At this time, the polycrystalline silicon 17 in the portion where the bonding pad will be formed is left on the thermally oxidized 5i02 film 12.

(c) On the substrate 11, a CvD SiO2 film (3000 nm
By diffusing boron using the (X thickness) 10a as a mask, a P+ source S and drain D are formed.

(d) Contrary to (c), the CvDSIO2 film (30
00 hole thickness) 10b as a mask, phosphorus is diffused to form an N+ source S' and a drain D'.

At this time, the polycrystalline silicon 17, which is the essential part of the present invention, is also doped with phosphorus.

(e) PS is applied to the entire upper surface of the substrate 11 by CVD method.
After forming a G film (9,000 mm thick) 15 and selectively removing the contact portion of the film 15, the entire surface-deposited aluminum (13,500 mm thick) is photoetched to form bonding pads 13 and sources. , drain, and gate electrodes are formed, and then a PSG film (5000 thick) 16 is formed so that only the aluminum pad 13 portion of the upper surface of the substrate 11 is exposed.

As a result, the same bonding as in FIG. 2E above is performed...
A pad configuration is obtained.

Further, FIGS. 4a to 4d show processing steps when the present invention is applied to a MOS having a P-channel type silicon gate structure.

(a) Thermal oxidation 5i02 of the upper surface of the N-type silicon substrate 21
Of these, portions corresponding to the source, drain, and gate portions are selectively removed, and a gate 9c is formed in the same manner as in step (b) of the C-MO8.

At this time, on the thermally oxidized 5i02 film 22, bonding...
The polycrystalline silicon 27 in the area where the pad will be formed is left, but the silicon 27 is made into P type by boron diffusion to form the P+ source S and drain D.

Accordingly, in the present invention, in order to make the silicon 27 N-type, the silicon 27 is doped with phosphorus before proceeding to the next step, for example, during the N+ diffusion for Garderifuging.

(b) PS is applied to the entire upper surface of the substrate 21 by CVD method.
After forming the G film 25, the contact portion of the film 25 is selectively removed.

(C) After depositing aluminum on the entire surface, the bonding pad 23 and the source,
Drain and gate electrodes are formed.

(d) Al□Nium pad 2 of the above board 21
A PSG film 26 is formed so that only three portions are exposed.

Note that in the case of an N-channel MOS, when forming the source and drain, the polycrystalline silicon under the bonding pad is also doped with phosphorus at the same time, so it is clear that the present invention can be easily applied. Probably.

As described above, according to the insulated gate semiconductor device of the present invention, the aluminum bonding pads 3, 13.2
3. Protective film treated with phosphorus under 3 (PSG film 5, 15, 25
, polycrystalline silicon 7°17.27) is arranged, it is possible to prevent surface contamination from the pad part and stabilize the device characteristics, and the above protective film protects the underlying part of the wire during bonding. It also has the effect of

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining problems in conventional devices of this type, FIGS. 3a to 3e are processing process diagrams when the present invention is applied to a C-MOS, and FIGS. 4a to 4d are processing process diagrams when the present invention is applied to a MOS having a P-channel type silicon gate structure. 1.11.21...Silicon substrate, 2.12.22.
...Thermal e-oxidized SiO2 film, 3,13.23...Aluminum bonding...pad, 5,15.25
...PSG film, 6,16,26...PSG film, 7.
17°27...Polycrystalline silicon.

Claims (1)

[Claims] 1 A first insulating film formed on a semiconductor surface, and a first insulating film formed on a semiconductor surface;
a polycrystalline silicon layer selectively formed on the insulating film of
A second insulating film doped with phosphorus formed on the polycrystalline silicon layer and the first insulating film, and a bonding pad formed on the second insulating film on the polycrystalline silicon layer. A semiconductor device comprising: