JPS5853515B2 - Silicon gate structure and transistor structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate type semiconductor device such as an MO8 type integrated circuit.

Among insulated gate semiconductor devices, N-channel silicon gate field effect transistors are highly integrated and high-speed operation MOSFETs.
Although it is suitable for 8-type integrated circuits, defects may occur in the insulated gate film due to the introduction of impurities from phosphorous oxides such as chlorine phosphorus oxide and phosphorus pentoxide in the phosphorus diffusion process when forming the N-type region. This is a reliability issue.

As a result of analysis, the occurrence of this defect was considered to be due to the diffusion of phosphorus oxide into polycrystalline silicon and the intrusion of phosphorus oxide along the silicon grain boundaries, causing the phosphorus oxide to come into direct contact with the 5I02 insulated gate film.

Although the 5i02 film provides an extremely good diffusion barrier against phosphorus atoms, it has poor barrier properties against phosphorous oxides, and defects that penetrate through the thin gate insulating film occur during the heat treatment process.

The occurrence of such defects causes this type of device to have a reliability problem in that its initial characteristics deteriorate over time.

An object of the present invention is to provide a method for manufacturing a highly reliable N-channel silicon gate field effect transistor.

According to this invention, after selectively depositing a gate insulating film and a polycrystalline silicon layer on the main surface of a P-type silicon substrate, phosphorus is diffused into the substrate around the polycrystalline silicon layer to form an N-type region. A method for manufacturing a silicon gate field effect transistor, characterized in that, before the phosphorus diffusion, a phosphorous oxide blocking layer of preferably 50 Å or more is interposed on the surface of the polycrystalline silicon layer. is obtained.

The manufacturing method of the present invention prevents phosphorus oxide from directly invading the polycrystalline silicon layer by using the phosphorus oxide blocking layer, so phosphorus oxide-based defects do not occur in the gate insulating film, resulting in extremely high reliability. It is possible to manufacture silicon gate type transistors with high efficiencies.

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1F show cross-sectional views of a transistor at each step in an embodiment of the present invention.

This transistor has about 1000 Si
A 5in2 surface protection film 13 with a thickness of 1.0μ is formed as an insulating coating on the insulating gate film 12 of 0.02 and the inactive region around this gate film. A polycrystalline silicon layer 14 with a thickness of about 0.5 μm and a silicon oxide film 15 with a thickness of 200 μm are selectively formed.

(Figure 1B). This polycrystalline silicon layer 14 is grown in a vapor phase by decomposing silane (SiH4) in a nitrogen atmosphere without any additives, and is then chemically etched after a silicon nitride film is grown.

Next, as shown in FIG. 1C, a gate film 12, a silicon layer 14
, and using the silicon nitride film 15 as a diffusion mask, phosphorus pentoxide or chlorine phosphorus oxide is applied to the substrate surface on both sides at approximately 1000°C.
to perform phosphorus diffusion.

Through this diffusion process, N-type regions 16 and 17 are formed on the substrate surface, and a silicon nitride film 15 is formed on the polycrystalline silicon layer 14.
Metallic phosphorus enters through.

Next, the silicon nitride film 15 used as a barrier to direct contact between phosphorus oxide and polycrystalline silicon during phosphorus diffusion is removed, and phosphorus is forced into the film by a thermal oxidation process in a steam atmosphere at about 1000°C.

The sample after the oxidation process has a junction depth of 2 as shown in the first diagram.
N-type regions 161 and 171 of μ, layer resistance 38/hole are formed, and about 4
000 S io 2 film 18 is grown.

Thereafter, the silicon layer 14 and the N-type regions 161, 1 are etched by selective etching as in the case of a normal silicon gate transistor.
Openings are provided on the upper surface of the aluminum electrode 71 (FIG. 1E), and aluminum gate electrodes G1, drain electrodes, source electrodes S, and lead-out electrodes SB from the base are provided, which extend from these openings and adhere to the surface protection film 13. (Figure 1F).

FIG. 2 is a characteristic diagram showing the operation and effect of one embodiment shown in FIGS. 1A to 1F, in which the horizontal axis shows the thickness t of the silicon nitride film deposited on the polycrystalline silicon layer, and the left vertical The axis shows the gate defect generation rate η, and the right vertical axis shows the layer resistance ρS of the polycrystalline silicon layer.

The gate area of the sample was 2.5 mm2, and the phosphorus diffusion process was from a P2O5SiO2 system using phosphorus pentoxide.

In the figure, the layer resistance ρS and failure rate η shown by the solid line are for a sample in which a silicon nitride film is directly provided on the surface of a polycrystalline silicon layer, and the broken line is for a sample in which a 400 S r 02 film is interposed between the two. It is something that

For both samples, the defect rate η, η1 was reduced by protecting the polycrystalline silicon layer with a silicon nitride film of 50 Å or more and performing phosphorus diffusion.
We show that it is possible to reduce

It is recognized that the upper limit of the silicon nitride film thickness is about 1oooλ because the layer resistances ρS and ρs1 increase as the film thickness increases, making it difficult to obtain conductivity as a gate electrode.

As shown in this figure, according to the present invention, the defective rate is extremely reduced, and a method for manufacturing a highly reliable N-channel silicon gate transistor is provided.

Furthermore, since the nitride film that protects the polycrystalline silicon avoids contact between phosphorous oxide and silicon during phosphorus diffusion and introduces silicon metal phosphorus through contact, a stable oxide film such as Al2O3 can be used instead.

Furthermore, interposing SiO2 or another insulating film between the silicon layer and the protective film is effective in facilitating manufacturing.

[Brief explanation of the drawing]

1A to 1F are cross-sectional views explaining each process of an embodiment of the present invention, and FIG. 2 is a characteristic diagram showing the effects of the present invention. In the figure, 11 is a P-type silicon monomer. crystal substrate,
12 is a gate insulating film, 14 is a polycrystalline silicon layer, and 15 is a silicon nitride film.

Claims (1)

[Claims] 1 Obtained by selectively depositing a gate insulating film and a polycrystalline silicon layer on the main surface of a P-type silicon substrate, and then diffusing phosphorus into the substrate around the polycrystalline silicon layer to form an N-type region. The method for manufacturing a transistor is characterized in that, before the phosphorus diffusion, a layer is provided on the surface of the polycrystalline silicon layer to which no impurities are added, which blocks phosphorus oxide but allows phosphorus to pass through so as to obtain a predetermined layer resistance. A method for manufacturing silicon gate field effect transistors.