JPS5848931B2 - Adder of digital differential analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an adder for a digital differential analyzer, and particularly relates to expanding the number of inputs of the adder and improving the calculation speed.

In recent years, digital differential analyzers have been put into practical use, allowing them to calculate differential equations and calculate and control continuous quantities such as trajectories and figures more accurately than analog computers.

This digital differential analyzer (Digital Dif
ferential analyzer) uses a coded numerical signal as an input variable instead of a voltage, and outputs the finite increment of this input variable over time as a quantized numerical value, and uses an integrator and an adder. The operating principle is as follows.

That is, the operating principle of the integrator can be determined by generating an implicit function such that x+y-z=o using the piecewise quadrature method.

Figure 1 shows a block diagram of an adder in a conventional serial differential analyzer (hereinafter referred to as DDA), and the addition of quadratic increments △Yo and △Y1, which are input variables, is performed as follows. It will be done.

First, the adder circuit 1 adds the increment values of the secondary increments ΔYo and ΔY1, and then the adder circuit 3 adds the resulting ΣΔY and the value of the Y register 2.

This result is stored in the Y register 2 again as ZY.

At this time, the value of the addition result of the Y register 2 is stored in the buffer 4 as an output.

Therefore, even though the output value of Y register 2 should be zero at this point, the input value still remains in Y register 2, and this value must be erased when the output is sent out.

Conventional DDA handles this operation through software processing, that is,
The adder was connected in such a way as to provide negative feedback to itself.

However, this method has the drawback that the relationship between input and output is delayed by one period, and one of the input terminals of the adder is occupied for negative feedback.

Therefore, the present invention has been made to solve these drawbacks, and its purpose is to expand the number of inputs to the adder and improve the calculation speed.

In order to achieve such an object, the DDA adder according to the present invention performs negative feedback in...-ware, and adds the input variable and the negative feedback value within a predetermined calculation time. be.

The present invention will be explained below using the drawings.

FIG. 2 is a block diagram showing an embodiment of the DDA adder according to the present invention, and the same parts as in FIG. 1 are denoted by the same symbols (
·ing.

In the same figure, the adder is input variable quadratic increment △Y
o, △Y1, △Y2; an adder circuit 3 that adds the sum of the quadratic increment sum Σ△Y and the content stored in the Y register or the content of the Y register and the negative feedback value; A Y register 2 that stores the addition result, a polarity determination circuit 5 that determines the polarity of the contents stored in the Y register represented by the most significant bit of the Y register 2, and an inversion circuit that inverts the output of the polarity determination circuit 5. 6, an adder circuit 7 for adding the contents of the Y register 2 and the output of the inverting circuit 6, that is, a negative feedback value, and a selector 8 that allows the output of the adder circuit I to pass only when the calculation mode is the adder mode, The addition result, ie, the implicit function ΔZ, is stored in the buffer memory 4.

The operation of the DDA adder configured in 5 will be described below.

First, before the quadratic increments ΔYo, ΔY1, and ΔY2 are supplied to the adder circuit 1, the addition mode instructs the selector 8 to determine the addition route of the negative feedback value.

Thereafter, when the addition data of the quadratic increments ΔYo, ΔY1, and ΔY2 are given to the adder circuit 1, the adder circuit 1 calculates the sum ΣΔY.

Next, the content of the Y register 2 and the negative feedback value based on the polarity determination result of this content are added in the adder circuit 7, and the result and ΣΔY are added in the adder circuit 3.

At this time, since the contents of the Y register 2 are zero, the negative feedback value is also zero, and the addition result of the adder circuit 7 is zero.

Therefore, in the first calculation cycle, ΣΔY is stored in the Y register 2.

When Σ△Y is stored in the Y register 2, the polarity judgment circuit 5 outputs +1 if the value is positive and -1 if the value is negative based on this Σ△Y.
If it is 1 or zero, a zero determination signal is output.

Suppose that Σ△Y at this time, that is, the contents of Y register 2, are
If it indicates a positive value, a +1 determination signal is output.

This determination signal is applied to the buffer memory 5 and stored therein, and the polarity of the judgment signal is inverted and applied to the adder circuit I.

As a result, the adder circuit I outputs the addition result of Σ△Y1,
It is supplied to the adder circuit 3.

At this time, since the output of the adder circuit 1 is already in the inhibited state, the output shows "0".

Therefore, the adder circuit 3 supplies the addition result of Σ△Y-1 to the Y register 2, and the Y register 2 receives the Σ
The addition result of the new content obtained by subtracting 1 from ΔY is stored.

By repeating similar operations, the contents of Y register 2 will eventually become zero.

Therefore, when the contents of the Y register 2 become zero, that is, when the negative feedback value becomes zero, the implicit function ΔZ is stored in the buffer memory 4.

In this way, according to this embodiment, since the generation of the implicit function is performed by hardware, the negative feedback value can be added immediately after storing the sum of quadratic increments ΣΔY in the Y register.

That is, the calculation speed of the adder can be improved.

At the same time, substantial additional manpower can be expanded.

Furthermore, since the addition of the negative feedback value is controlled by the selector, it is easy to use it as an integrator without adding any other hardware, as in the conventional case.

As explained above, the DDA adder according to the present invention uses hardware to perform negative feedback based on the result of addition of quadratic increments, which was conventionally performed by software processing.
It is possible to improve the calculation speed of the adder and to substantially expand the number of addition inputs.

Furthermore, since the increase in hardware can be reduced compared to the increase in memory capacity that occurs as a result of performing negative feedback through software processing, it has excellent effects such as being able to provide an inexpensive DDA.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional DDA adder, Figure 2 is a block diagram showing a conventional DDA adder;
The figure is a block diagram showing an adder of a DDA according to the present invention. 1, 3, 7...Addition circuit, 2...Y register, 4...Buffer memory, 5...
・Polarity inversion circuit, 6... Inversion circuit, 8...
··selector.

Claims (1)

[Claims] 1 Addition circuit and register that add and store the increase in the human input variable, and determine whether the addition result of the increase in the input variable stored in this register is in the positive, negative, or zero region, and if it is positive, +1 , and a negative feedback addition circuit which adds the inverted outputs of the judgment outputs -1, +1, and zero, which are -1 if negative and zero if zero, to the initial addition result.