JPS5849055B2 - In-phase detection circuit for AM/PM stereo signal demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a configuration of an in-phase detection circuit for a stereo signal receiver, and more particularly to an in-phase detection circuit for a compatible quadrature AM stereo signal that is compatible with stereo and monaural receivers.

Compatible quadrature P as a stereo signal
There is an AM stereo signal based on the M system, but the AM stereo signal es is generally expressed by the following equation.

Here, L(t) and R(t) are left and right channel signals, ωC is the angular frequency of the carrier signal, and k is the modulation degree.

In other words, the compatible quadrature AM stereo signal shown by equations (1) and (2) above consists of a signal obtained by modulating the amplitude of the carrier signal cosωct with a signal corresponding to the sum of both channel signals, and the phase of the carrier signal. 90 against
It includes a signal obtained by combining the amplitude of the carrier signal cos (ωct+π/2) with a zero phase shift and a signal modulated by the difference between the two channel signals.

Then, so that this stereo signal can be received even in a monaural receiver, the level of the combined signal is modulated by cosφ as shown in equation (1) and then transmitted.

An example of the AM/PM stereo signal demodulation circuit shown by the above equations (1) and (2) is described in detail in Japanese Patent Application Laid-open No. 141502/1983.

That is, the IF signal is input to a phase detection circuit of a PLL (phase sevenfold loop) circuit via a limiter circuit.

The output of the VCO (voltage controlled oscillator) of the PLL circuit uses a frequency divider or the like to obtain a signal that is in phase with the input IP signal and has a phase difference of 900 degrees.

Here, the input signal is input to the phase detection circuit as described above, and simultaneously input to the PM demodulation circuit for demodulating the difference signal to demodulate the orthogonal component of the carrier signal, that is, the difference signal between the left and right channels.

Also, the signal in phase with the carrier wave created by the frequency divider of the PLL circuit becomes the input of the common mode detection circuit, and the output of the limiter circuit simultaneously becomes the input of this common mode detection circuit, so (1)
The cosφ term in the equation is detected and input to the divider circuit.

The output component of the previous PM demodulation circuit is (L(t)-R(t
)) Since cosφ, this division circuit reduces cosφ
The precept is removed and the difference signal is output to the next stage.
input to the TSx circuit.

A sum signal that has been subjected to envelope detection is also separately input to the matrix circuit, and is separated into left and right channel signals together with the difference signal.

Here, as an in-phase detection circuit to obtain the precept of cosφ,
A multiplication circuit using a differential amplifier is used.

That is, a signal e' (s) obtained by limiting the amplitude of the IP signal between the bases of a pair of differential transistors by a limiter circuit.
is applied, the carrier signal (cosωct) and the in-phase signal are applied to the base of the transistor that constitutes the current source of the differential amplifier, the product output of both is obtained from the collector output of one of the differential transistors, and the output is The low range is c due to the wave device.
The structure is such that a certain fraction of osφ is derived and used as an input signal to the division circuit.

However, in the N configuration, the V of the current source transistor
Since there is a level shift due to BE (base emitter voltage), there is a drawback that the current supplied to the differential transistor is not proportional to cosωct, which is the base input of the current source transistor.

Furthermore, even if the base power e'(s) of the differential transistor can take positive and negative polarities, it can only take positive polarity as the base input of the current source transistor, so the product output is a half-wave rectified waveform output. Therefore, a full-wave rectified waveform output of the cosφ component cannot be obtained, and as a result, demodulation without complete distortion cannot be performed.

The object of the present invention is to provide the above-mentioned compatible quadrature
It is an object of the present invention to provide an in-phase detection circuit capable of obtaining a cosφ signal, which is a phase modulation component of a carrier wave of an AM7PM stereo signal, in a complete waveform.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 shows a block diagram of a demodulation circuit for a compatible black latcher AM/PM stereo signal.

The input IF signal e, shown by equations (1.) and (2), is envelope-detected by the AM demodulation circuit 1 and then (L+R
) signal is obtained and input to the matrix circuit 4.

Furthermore, it is input to the PM demodulation circuit 2 and (L-R)cosφ
I get a signal.

This signal is converted into (LR) by the division circuit 3, and the left and right channel signals are reproduced by the matrix circuit 4 using the equal sum and difference signals.

The division signal cosφ in the division circuit 3 uses a signal obtained by a PLL circuit.

That is, the input signal es is input to a 900 phase detector (quadrature phase detector) 5 via a limiter 18, and its phase is compared with the output signal of the VCO 6.

The output of this comparator 5 is used as a control voltage for the VCO 6 via the LPE 7.

Also, the output of CO6 is applied to the in-phase detector 8 for phase comparison with the output e/8 of the limiter 18, but at this time V
Since the output of CO6 is out of phase by 900 degrees with respect to e/5, it is shifted by 90 degrees by phase shifter 9.

Therefore, the output of the in-phase detector 8 becomes a signal component indicating cosφ, and this cosφ is used as the division signal of the division circuit 3.

In addition, the signal cosφ is passed through a smoothing filter to the control circuit section 1.
0 to drive the lock indicator 11 to light up, and also send a control signal for muting to the control output terminal 19.
It is possible to mute the device outside the lock band of the PLL circuit by outputting the signal to a suitable muting circuit and controlling an appropriate muting circuit.

The present invention is an improvement on the in-phase detector 8 described above, and has the advantage that the control circuit 10 can be easily configured using the output of the detector 8.

FIG. 2 is a specific circuit diagram of the in-phase detector 8 and the control circuit 10 according to an embodiment of the present invention.

The IF input signal is <t+, e3 shown by equation (2), which can be expressed as follows.Therefore, the input signal e5 has a carrier wave that undergoes phase modulation with a phase φ that corresponds to the information of the left and right channel signals. After passing through the limiter 18, the signal e5 becomes a signal e/, which is proportional to cos (ωct+φ).
is applied to the input terminal 20 in FIG.

This signal becomes the base input of a first differential circuit having transistors Q5 and Q6 whose emitters are commonly connected through a compres- ing capacitor C2.

The bases of both transistors Q5 and Q6 are connected to the resistors R3 and 2 with a predetermined bias generated from a bias circuit (not shown).
Applied via R4.

The collector of the transistor Q5 is connected to the common emitter connection point of the transistors Ql and Q2 forming the second differential circuit, and the collector of the transistor Q6 is connected to the common connection point of the emitters of the transistors Q1 and Q2 forming the third differential circuit. Connected to the emitter common connection point.

A bias from a bias circuit (not shown) is applied to the bases of these transistors Q, -Q4 via resistors R1, R2.

The base inputs of these second and third differential circuits include the first
c which is the output of the 900 phase shifter 9 of the PLL circuit shown in the figure.
osωct, that is, a signal in phase with the carrier wave is input to the input terminal 21
is applied through the capacitor C1.

The collectors of transistors Q1 and Q3 are commonly connected to output point a and are also connected to positive power supply Vcc via load resistor R5.

The collectors of transistors Q2 and Q4 are commonly connected at output point a' and connected to the positive power supply Vc via a load resistor R'.
connected to c.

*? Furthermore, a transistor Q13 whose emitters are commonly connected has a base input of the signal between output points a and a'.
A fourth differential circuit is constituted by rQ7, and a series connection circuit of a resistor R6 and a diode D is provided as a collector load of the transistor Q7, and a capacitor C3 is connected in parallel to this series connection circuit.

A steady state bias to diode D is supplied by resistor R7.

The collector output of transistor Q7 is input to transistor Q8 that constitutes an emitter follower, and emitter resistor R
The outputs from both ends of 8 are input to the smoothing capacitor C4.

The output of the smoothing capacitor C4 is input to a current mirror circuit consisting of transistors Q1, Q, and 2 through a series connection circuit of resistors R, , R, and 6, and is inputted from the collector output terminal 22 of the transistor Q12 to the common-mode detection circuit. An output signal is derived.

Further, the output of the smoothing capacitor C4 becomes an input to the control signal generating circuit 10 (FIG. 1) via a resistor R.

The control signal generation circuit 10 is a lock indicator LE.
A transistor Q9 has a collector load D11, and an amplifier consisting of resistors R, 2, R, 4 and a transistor Q1o is further connected to the collector output of the transistor Q9.

A mute ink signal is derived from the collector output terminal 19 of.

In this configuration, assuming that the current of the constant current source of the first differential circuit is E1, the output of the multiplier circuit of the first to third differential circuits, that is, the output Ao1 of the output point a, is expressed by the following equation.

Here, R is the resistance of the load resistors R5 and R', k is Boltzmann's constant, q is the electron density, T is the absolute temperature, and cosω
ct, cos (aict+@li sore sore c
osωct and cos(ωct+φ) indicate a certain amount of the opposite phase.

By transforming equation (3), the following equation is obtained.

As is clear from the above equation (4), out of the output of the multiplier circuit, co
Since s (2ωct+φ) is a signal component having a frequency approximately twice that of the carrier wave signal ωct, the LPF (low frequency i
It becomes possible to derive only the cos φ component by removing it using a wave filter.

For this purpose, a selection means for selectively deriving the cosφ component is provided by the fourth differential circuit and its load, which is the capacitor C3 and the emitter follower Q8.

The value of the capacitor C3 connected to the load of the fourth differential circuit is selected to remove the cos(2ωctφ) component.

As a result, an output Av2 expressed by the following equation is obtained at the collector output of the transistor Q7.

Here, ■E2 is the constant current value of the fourth differential circuit, and R6 is the value of the load resistor R6.

Note that the second term component in equation (5) is a voltage generated by the DC bias current and has a constant value, and can be ignored by making IE2 small.

Note that the diode D is an emitter follower transistor Q8.
The transistor Q13 operates in class A mode, and also has a function of temperature compensation effect with the transistor Q13.

Therefore, the output of the emitter follower becomes an output proportional to COSφ, and after being smoothed by the smoothing capacitor C4,
Current value ■ by current mirror circuit.

It is converted into cosφ and derived as output 22.

This output is used as the division input of the division circuit 3.

Further, the smoothed output is introduced into the control circuit 10 to drive the lock indicator 11, and the muting circuit (
(not shown) serves as a muting control signal.

As described above, according to the present invention, since the multiplication circuit is configured as a so-called double-balanced product circuit, a full-wave rectified output is obtained as the output, and the drawbacks of conventional product circuits can be eliminated. , therefore, cos
The φ signal component can be obtained without distortion.

Furthermore, this output can be used to perform a lock indicator or muting operation.

In the above embodiment, the input terminals 20 are connected to e'5-c.
os(ωct+φ) to e1cosω to the input terminal 21
Although ct is applied, it is of course possible to apply e to the input terminal 20 and e/5 to the input terminal 21, respectively.

In addition, in FIG. 2, a low-pass filter is configured by smoothing capacitors C4, C and resistor R1, but
The low-pass filter can also be configured using a well-known active filter including an active element, thereby making it possible to improve the filter characteristics.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a compatible quadrature AM stereo demodulation circuit, and FIG. 2 is a block diagram of an in-phase detection circuit and a control signal generation circuit according to an embodiment of the present invention. Explanation of symbols of main parts 8...In-phase detection circuit,
Q1 to Q7 1 Q13'...Transistors forming a differential circuit.

Claims (1)

[Claims] 1 e5=({1+k(L(t)+R(t))}co
sωct+k(L(t) -R(t)cos(ωct
+π/2)]0COSφ, φ=jan−' k {L(t) −R(t
) )/('1+k {L(t)+R(t))) (L(t) and R(t) are the first and second channel signals, respectively, ωC is the angular frequency of the carrier signal, and k is the modulation This is an in-phase detection circuit in a demodulation circuit for an AM/PM stereo signal (with a degree of a differential circuit having first and second transistors, and a first differential circuit having a first and second transistor, and
8) are applied to the inputs of the second differential circuit, and the second differential circuit has an emitter connected to the first differential circuit.
a third and a fourth commonly connected to the collector of the transistor;
The third differential circuit includes fifth and sixth transistors whose emitters are commonly connected to the collector of the second transistor, and whose bases are connected to each other, and whose bases are connected to each other. The bases of the fifth transistors are commonly connected to each other, and the signal derived from between the collector common connection point of the third and fifth transistors and the collector common connection point of the fourth and sixth transistors is An in-phase detection circuit characterized in that a cosφ precept is selectively outputted by a selection means. 2. The selection means includes a fourth differential circuit whose bases are connected to a common collector connection point of the third and fifth transistors and to a common collector connection point of the fourth and sixth transistors, and whose emitters are commonly connected. 2. The in-phase detection circuit according to claim 1, further comprising a low-frequency wave circuit connected to the output of said fourth differential circuit.