JPS6253978B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lock indicator drive circuit, and more particularly to a lock status control circuit for a PLL (phase locked loop) circuit in a demodulation section of a compatible quadrature AM stereo signal compatible with stereo and monaural receivers. The present invention relates to a lock indicator drive circuit that shows a lock indicator.

As a stereo signal, there is an AM stereo signal based on the compatible quadrature PM system, and such AM stereo signal e _s is generally expressed by the following equation.

es=[{1+k(L(t)+R(t))}cosωct+
k{L(t)-R(t)}cos(ωct+π/2)]・
cosφ...(1) φ=tan ^-1 k{L(t)-R(t)}/[1+k
{L(t)+R(t)}] ...(2) Here, L(t) and R(t) are the left and right channel signals, ωc is the angular frequency of the carrier signal, and k is the modulation degree.

In other words, the compatible quadrature AM stereo signal shown by equations (1) and (2) above consists of a signal in which the amplitude of the carrier signal cosωct is modulated by a signal corresponding to the sum of both channel signals, and a signal in which the amplitude of the carrier signal cosωct is modulated by a signal corresponding to the sum of both channel signals, and the phase of the carrier signal. The carrier signal cos (ωct+
π/2) amplitude modulated with a signal corresponding to the difference between both channel signals. Then, so that this stereo signal can be received even in a monaural receiver, the level of the composite signal is modulated by cosφ as shown in equation (1) and then transmitted.

An example of the AM/PM stereo signal demodulation circuit shown by the above equations (1) and (2) is described in detail in Japanese Patent Laid-Open Publication No. 141502/1983. That is, the IF signal is input to the phase detection circuit of the PLL circuit via the limiter circuit. PLL circuit VCO (voltage controlled oscillator)
The output of the input IF signal uses a frequency divider or the like to obtain a signal that is in phase with the input IF signal and has a 90° phase difference. Here, the input signal is input to the phase detection circuit as described above, and simultaneously input to the PM demodulation circuit for demodulating the difference signal to demodulate the orthogonal component of the carrier signal, that is, the difference signal between the left and right channels. In addition, the signal in phase with the carrier wave created by the frequency divider of the PLL circuit becomes the input of the common mode detection circuit, and the output of the limiter circuit simultaneously becomes the input of this common mode detection circuit.
The cosφ term is detected and input to the divider circuit. The output component of the previous PM demodulation circuit is {L(t)-R
(t)} cosφ, so this division circuit reduces cosφ
The components are removed and a difference signal is output and input to the next stage matrix circuit. A sum signal separately subjected to envelope detection is also input to the matrix circuit, and is separated into left and right channel signals together with the difference signal.

In such a demodulation method, when the PLL circuit locks in and out when the receiver is detuned, the beat component between the carrier wave of the input signal _es and the output signal of the VCO is added to the output audio signals L and R as large noise. appear. In order to remove such noise, muting the output audio signal containing noise outside the lock range of the PLL circuit will prevent the receiver from going out of tune when there is a silent section in the broadcast program being received. As a result, there is a risk that the output audio signal may be mistaken as having been muted. In order to prevent such erroneous recognition from occurring, it is conceivable to provide a lock indicator and light the lock indicator when the PLL circuit is in the lock state. For this purpose, the lock indicator may be driven using the output cosφ of the common-mode detection circuit, but it is necessary to derive a signal that accurately corresponds to the cosφ signal component from the output of the common-mode detection circuit.

However, as a common-mode detection circuit, a signal e _s ', which is an IF signal whose amplitude is limited by a limiter circuit, is applied between the bases of a pair of differential transistors, and a carrier signal (cosωct) is applied to the bases of the transistors that constitute the current source of the differential amplifier. The configuration is such that the product output of both signals is obtained from the collector output of one of the differential transistors, and the cosφ component is derived from the output through a low-pass filter.

In such a configuration, V _BE of the current source transistor
Since there is a level shift due to (base-emitter voltage), the current supplied to the differential transistor is the base input of the current source transistor.
There is a drawback that it is not proportional to cosωct. In addition, even if the base input e _s ' of the differential transistor can take positive or negative polarity, it can only take positive polarity as the base input of the current source transistor, so the product output is a half-wave rectified waveform output, and therefore the cosφ component The drawback is that a full-wave rectified output cannot be obtained, resulting in an erroneous indication of the lock indicator.

The object of the invention is to provide a compatible quadrature
It is an object of the present invention to provide a lock indicator drive circuit capable of driving a lock indicator in accurate response to a cosφ signal which is a phase modulation component of a carrier wave of an AA/PM stereo signal.

The lock indicator driving circuit according to the present invention comprises:
A double-balanced product circuit is connected to act as a multiplier in the AM/PM stereo signal demodulation circuit, and a selection means selectively outputs the cosφ component from the output of the product circuit. The lock indicator is driven in response.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

Figure 1 shows the compatible quadrature AM/
A block diagram of a PM stereo signal demodulation circuit is shown.

The input IF signal e _s shown by equations (1) and (2) is envelope-detected by the AM demodulation circuit 1 (L+R).
A signal is obtained and input to the matrix circuit 4. Furthermore
It is also input to the PM demodulation circuit 2 to obtain a (LR) cosφ signal. This signal is divided by the division circuit 3 (L
-R), the left and right channel signals are respectively reproduced by the matrix circuit 4 using these equal sum and difference signals.

The division signal cosφ in the division circuit 3 uses a signal obtained by a PLL circuit. That is, the input signal e _s is input to a 90° phase detector (quadrature phase detector) 5 via a limiter 18, and its phase is compared with the output signal of the VCO 6. The output of this comparator 5 is used as a control voltage for the VCO 6 via the LPF 7. The output of the VCO 6 is detected by the in-phase detector 8 for phase comparison with the output e _s ' of the limiter 18, but at this time the output of the VCO 6 is e
Since the phase is shifted by 90 degrees with respect to _s ', it is shifted by 90 degrees by the phase shifter 9. Therefore, the common mode detector 8
The output of becomes the signal component indicating cosφ, and this cosφ
is used as the division signal of the division circuit 3. Also the signal
cosφ is input to the control circuit section 10 through a smoothing filter to light up the lock indicator 11, and a control signal for muting is output to the control output terminal 19 to control an appropriate muting circuit to adjust the lock band of the PLL circuit. It is possible to mute the device outside.

In the present invention, the in-phase detector 8 and the control circuit section 10 are used as the lock indicator drive circuit, and the lock indicator 11 lights up when the PLL circuit is in the locked state.

FIG. 2 is a specific circuit diagram of an embodiment of the present invention. The IF input signal is e _s shown by equations (1) and (2), in other words, e _s = {1+k(L+R)} ² −k ² (L−R)
²・cos(ωct+φ) Therefore, the input signal e _s becomes a signal whose carrier wave is phase modulated with the phase φ according to the information of the left and right channel signals, and the signal e _s
After passing through the limiter 18, it is applied to the input terminal 20 in FIG. 2 as a signal e _s ' proportional to cos(ωct+φ). The signal is a coupling capacitor
Via C ₂ , it becomes the base input of a first differential circuit having transistors Q ₅ and Q ₆ whose emitters are commonly connected. A predetermined bias generated by a bias circuit (not shown) is applied to the bases of both transistors Q ₅ and Q ₆ via resistors R ₃ and R ₄ .

The collector of transistor Q ₅ is connected to the common connection point of the emitters of transistors Q ₁ and Q ₂ that constitute the second differential circuit, and the collector of transistor Q ₆ is connected to the common connection point of the emitters of transistors Q 1 and Q 2 that constitute the second differential circuit.
Connected to the emitter common connection point of Q ₃ and Q ₄ . A bias from a bias circuit (not shown) is connected to the base of these transistors Q ₁ to _{Q 4} through a resistor.
It is applied via R ₁ and R ₂ . The base inputs of these second and third differential circuits are connected to cosω, which is the output of the 90° phase shifter 9 of the PLL circuit shown in FIG.
ct, that is, a signal in phase with the carrier wave is applied from the input terminal 21 via the capacitor _C1 .

The collectors of transistors Q ₁ and Q ₃ are commonly connected to the output point a, and are also connected to the positive power supply Vcc via a load resistor R ₅ . The collectors of transistors Q ₂ and Q ₄ are commonly connected at an output point a' and are also connected to the positive power supply Vcc via a load resistor R' ₅ .

Furthermore, transistors Q ₁₃ and Q ₇ whose emitters are commonly connected each have a base input of the signal between output points a and a'.
A fourth differential circuit is constructed, and a series connection circuit of a resistor R ₆ and a diode D is provided as the collector load of the transistor Q ₇ , and a capacitor C ₃ is connected in parallel to this series connection circuit. . Steady bias to diode D is resistor R ₇
Supplied by The collector output of transistor _Q7 is the transistor that constitutes the emitter follower.
The output from both ends of _the emitter resistor _R8 is input to the smoothing capacitor _C4 . The output of the smoothing capacitor C ₄ is input to a current mirror circuit consisting of transistors Q _{11 and Q 12 via a series connection circuit of resistors R 15 and R 16} , and is inputted from the collector output terminal 22 of the transistor Q ₁₂ to the common mode detection circuit. An output signal is derived.

Further, the output of the smoothing capacitor _C4 becomes an input to the control signal generation circuit 10 (FIG. 1) via a resistor _R9 . The control signal generation circuit 10 has a transistor _Q3 whose collector load is an LED 11 which is a lock indicator, and further has a resistor at its collector output.
An amplifier consisting of R ₁₂ , R ₁₄ and transistor Q ₁₀ is connected to derive a muting control signal from the collector output terminal 19 of transistor Q ₁₀ .

In such a configuration, assuming that the current of the constant current source of the first differential circuit is I _E1 , the output of the multiplier circuit of the first to third differential circuits, that is, the output A of the output point a
_v1 is the following formula.

Here, R ₅ is the resistance of the load resistors R ₅ and R' ₅ , k is Boltzmann's constant, q is the electron density, T is the absolute temperature,
, (+) are each cosωc
t,
Indicates the negative phase component of cos(ωct+φ).

By transforming equation (3), the following equation is obtained.

As is clear from the above equation, among the outputs of the multiplier circuit,
Since cos(2ωct+φ) is a signal component having a frequency approximately twice that of the carrier signal ωct, it is possible to remove it using an LPF (low pass filter) and derive only the cosφ component.

For this purpose, the fourth differential circuit and its loads, ie, capacitor C ₃ and emitter follower Q ₈ , are used.
A selection means for selectively deriving the cosφ component is configured. Select the value of the capacitor _C3 connected to the load of the fourth differential circuit to obtain cos(2ωct+φ)
Try to remove the ingredients. As a result, an output A _v2 expressed by the following equation is obtained at the collector output of the transistor _Q7 .

Here, I _E2 is the constant current value of the fourth differential circuit, R ₆
is the value of the load resistance _R6 . Note that the second term component in equation (5) is a voltage generated by the DC bias current and has a constant value, and can be ignored by making I _E2 small. Note that the diode D operates the emitter follower transistor _Q8 in class A operation, and also has a function of temperature compensation effect with the transistor _Q8 .

Therefore, the output of the emitter follower becomes an output proportional to cosφ, and after being smoothed by the smoothing capacitor _C4 , the current value I o is changed by the current mirror circuit.
It is converted into cosφ and derived as output 22. This output is used as the division input of the division circuit 3.

Furthermore, the smoothed output is introduced into the control circuit 10.
Therefore, when the PLL circuit is in the lock state, a signal proportional to cosφ is generated at the output of the common mode detector 8, so that the transistor _Q9 becomes conductive and the lock indicator 11 lights up. Further, when the PLL circuit is out of the locked state, no signal appears at the output of the common mode detector 8, so the transistor _Q9 becomes non-conductive and the lock indicator 11 turns off.

According to the circuit shown in FIG. 2, since the multiplication circuit is configured as a so-called double-balanced product circuit, a full-wave rectified output can be obtained as the output, and the drawbacks of the conventional product circuit can be eliminated. Therefore, the cosφ signal component can be obtained without distortion.
Therefore, a signal that accurately corresponds to the cosφ signal is supplied to the base of the transistor _Q9 of the control circuit 10, and the lock indicator 11 is driven without error in exact accordance with the lock state of the PLL circuit.

In addition, in the above-mentioned embodiment, the input terminal 20
es′=cos(ωct+φ) to other input terminal 21 e ₁ =
cosωct was applied, but on the contrary, e ₁ was applied to the input terminal 20.
Of course, it is also possible to apply e _s ' to 21 and 21, respectively. In addition, although a low-pass filter is configured by smoothing capacitors C ₄ and C ₅ and resistor R ₁₅ in FIG. 2, the low-pass filter can also be configured using a well-known active filter including an active element. It is possible to improve filter characteristics.

As detailed above, the lock indicator drive circuit according to the present invention connects a double-balanced product circuit so as to act as a multiplier in the AM/PM stereo signal demodulation circuit, and selects the cosφ component from the output of this product circuit. Since the configuration is such that the lock indicator is driven in response to the selected output, the in-phase detection output (cosφ) can be obtained without distortion, and the lock state of the PLL circuit can be incorrectly displayed. This means that it can be performed stably without any problems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a compatible quadrature AM stereo demodulation circuit, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. Explanation of symbols of main parts, 8...In-phase detection circuit,
DESCRIPTION OF SYMBOLS 10...Control circuit, 11...Lock indicator, _Q1 ,~ _Q7 , _Q13 ...Differential transistor.

Claims (1)

[Claims] 1 es=[{1+k(L(t)+R(t))}cosωct
+k{L(t)-R(t)cos(ωct+π/2)]・
cosφ, φ=tan ^-1 k{L(t)-R(t)}/[1+k
{L(t)+R(t)}] (L(t) and R(t) are the first and second
Channel signal, ωc is each frequency of carrier signal, k
This is a lock indicator driving circuit for displaying the lock state of a phase locked loop circuit in an AM/PM stereo signal demodulation circuit where the modulation signal es is the modulation degree (or the carrier signal is the modulation degree). a first differential circuit having first and second transistors having their emitters connected in common, the in-phase signal (or a signal corresponding to the modulation signal es) being applied to the input; a second differential circuit having a third and a fourth transistor whose emitters are connected in common to the collector of the first transistor; and the in-phase signal (or a signal according to the modulation signal es) is applied to the input. and a third differential circuit including fifth and sixth transistors whose emitters are commonly connected to the collectors of the second transistors, and a common connection point between the collectors of the third and fifth transistors and the fourth and sixth transistors. a fourth differential circuit having seventh and eighth transistors whose emitters are commonly connected, a signal derived from between the collector and the common connection point is applied to the input; and a collector output of the eighth transistor is applied to the input. the bases of the third and sixth transistors and the bases of the fourth and fifth transistors are respectively commonly connected, and the emitter follower transistor is connected as a collector load of the eighth transistor. 8th
It has a series connection circuit consisting of a resistor and a diode connected in series between the collector of the transistor and a predetermined reference potential point, and a capacitor connected in parallel to the series connection circuit, and is responsive to the output of the emitter follower transistor. A lock indicator drive circuit, characterized in that it drives the lock indicator.