JPS5849056B2 - Muting control signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a muting control signal generation circuit, and more particularly to a muting control signal generation circuit using a compatible quadrature AM stereo signal demodulation section that is compatible with stereo and monaural receivers.

As a stereo signal, there is an AM stereo signal based on the compatible quadrature PM system, and this AM stereo signal e is generally expressed by the following equation.

Here, L(t) and R(t) are left and right channel signals, ωC is the angular frequency of the carrier signal, and k is the modulation degree.

In other words, the compatible quadrature AM stereo signal shown by equations (1) and (2) above consists of a signal obtained by modulating the amplitude of the carrier signal cos(l)ct with a signal corresponding to the sum of both channel signals, and the corresponding Carrier signal cos(ωct+π/2) whose phase is shifted by 90° with respect to the phase of the carrier signal
It includes a signal obtained by modulating the amplitude of the channel signal with a signal corresponding to the difference between the two channel signals.

Then, so that this stereo signal can be received even in a monaural receiver, the level of the composite signal is modulated by cosφ as shown in equation (1) and then transmitted.

An example of the AM/PM stereo signal demodulation circuit shown by the above equations (1) and (2) is given in Japanese Patent Application Laid-Open No. 52-1415.
It is detailed in Publication No. 02.

That is, the IP signal is input to a phase detection circuit of a PLL (phase locked loop) circuit via a limiter circuit.

The output of the VCO (voltage controlled oscillator) of the PLL circuit uses a frequency divider or the like to obtain a signal that is in phase with the input IP signal having a 90° phase difference.

Here, the input signal is input to the phase detection circuit as described above, and at the same time is input to the PM demodulation circuit for demodulating the difference signal to demodulate the orthogonal signal of the carrier signal, that is, the difference signal between the left and right channels.

Also, the signal in phase with the carrier wave created by the frequency divider of the PLL circuit becomes the input of the common mode detection circuit, and the output of the limit circuit simultaneously becomes the input of this common mode detection circuit, so (1)
The cosφ term in the equation is detected and input to the divider circuit.

The output of the previous PM demodulation circuit is (L(t)-R(t
) } Since cosφ, this division circuit reduces cos
The φ component is removed, and a difference signal is output and input to the next stage matrix circuit.

Separately, the envelope-detected sum signal is also input to the matrix circuit, and is separated into left and right channel signals together with the difference signal.

In such a demodulation method, when the PLL circuit locks in and locks out, the carrier wave of the input signal e5 and
A beat component with the CO output signal appears as large noise in the output audio signals L and H.

In order to remove such noise, a method can be considered in which a so-called muting circuit is used in the lock range of the PLL circuit to mute output audio and signals containing noise.

For this purpose, the output cosφ of the common mode detection circuit of the PLL circuit is
Although it is sufficient to operate a predetermined muting circuit using the in-phase detection circuit, it is necessary to derive a signal that accurately corresponds to the cosφ signal component from the output of the in-phase detection circuit.

However, as a common-mode detection circuit, a signal e/5, which is an IF signal whose amplitude is limited by a limiter circuit, is applied between the bases of a pair of differential transistors, and a carrier signal ( cosωct
), the product output of both signals is obtained from the collector output of one of the differential transistors, and the cosφ component is derived from this output via a low-band p-wave generator.

In the structure, there is a level shift due to the VBE (base-emitter voltage) of the current source transistor, so
There is a drawback that the current supplied to the differential transistor is not proportional to cosωct, which is the base input of the current source transistor.

In addition, even if the base power e/5 of the differential transistor can take positive or negative polarity, it can only take positive polarity as the base input of the current source transistor, so the product output is a half-wave rectified waveform output, so the cosφ component There is a drawback that a full-wave rectified output cannot be obtained, and as a result, the muting circuit malfunctions.

The purpose of the present invention is to provide a compatible quadrature AM/P
cosφ, which is the phase modulation component of the carrier wave of the M stereo signal
It is an object of the present invention to provide a muting control signal generation circuit that generates a muting control signal that accurately corresponds to a signal.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 shows a block diagram of a compatible quadrature AM/PM stereo signal demodulation circuit.

The input IF signal e5 shown by formula (1), C2) is A
Envelope detection is performed by M demodulation circuit 1 (L+R)
A signal is obtained and input to the matrix circuit 4.

Furthermore, it is input to the PM demodulation circuit 2 to obtain a (LR) cosφ signal.

This signal is converted into (LR) by the division circuit 3, and the left and right channel signals are reproduced by the matrix circuit 4 using the equal sum and difference signals.

The division signal cosφ in the division circuit 3 uses a signal obtained by a PLL circuit.

That is, the input signal e is inputted to a 90° phase detector (quadrature phase detector) 5 via a limiter 18, and is compared in phase with the output signal of the VCO 6.

The output of this comparator 5 is used as a control voltage for the VCO 6 via an LPF 7.

Further, the output of the VCO 6 is applied to the in-phase detector 8 for phase comparison with the output e/5 of the limiter 18;
Since the output of O6 is out of phase by 90 degrees with respect to e/, it is shifted by 900 degrees by the phase shifter 9.

Therefore, the output of the in-phase detector 8 becomes a signal component indicating cosφ, and this cosφ is used as the division signal of the division circuit 3.

In addition, the signal cosφ is passed through a smoothing filter to the control circuit section 1.
0 to drive the lock indicator 11 to light up, and also send a control signal for muting to the control output terminal 19.
It is possible to mute the device outside the lock band of the PLL circuit by outputting it to and controlling an appropriate muting circuit.

In the present invention, the in-phase detector 8 and the control circuit section 10 are used as the muting control signal generation circuit, and the P
This allows a muting signal to be accurately generated at the control terminal 19 outside the lock band of the LL circuit.

FIG. 2 is a specific circuit diagram of an embodiment of the present invention.

The IP input signal is e, which is shown by equations (1) and (2), and can be expressed as follows.Therefore, the input signal e, has a carrier wave phase with a phase φ according to the information of the left and right channel signals. This becomes a modulated signal, and after passing through the limiter 18, the signal eS is applied to the input terminal 20 in FIG. 2 as a signal e/, which is proportional to cos(ωct+φ).

The signal becomes the base input of a first differential circuit having transistors Q5 and Q6 whose emitters are commonly connected through a coupling capacitor C2.

The bases of both transistors Q5 and Q6 are connected to a resistor R3 by a predetermined bias generated from a bias circuit (not shown).
, R4.

The collector of the transistor Q5 is connected to the common connection point of the emitters of the transistors Q1 and Q2 that constitute the second differential circuit, and the collector of the transistor Q6 is connected to the common connection point of the emitters of the transistors Q1 and Q2 that constitute the second differential circuit. is connected to the emitter common connection point.

A bias from a bias circuit (not shown) is applied to the bases of these transistors Q and Q4 via resistors R+ and R2.

The base inputs of these second and third differential circuits include the first
○ is the output of the 900 phase shifter 9 of the PLL circuit shown in the figure.
cosωct, that is, a signal in phase with the carrier wave is input to input terminal 2.
1 through the capacitor C.

The collectors of transistors Q1 and Q3 are connected to the output terminal a? are connected in common to the positive power supply Vc through the load resistor R,
connected to c.

The collectors of transistors Q2 and Q4 are commonly connected at output point a' and connected to the positive power supply Vc via load resistor R'5.
connected to c.

Furthermore, a fourth differential circuit is constituted by a transistor Q13"lQ7 whose emitters are commonly connected and whose base input is a signal between output points a and a'. A resistor R6 and a diode D are used as collector loads of the transistor Q7. A series connection circuit is provided, and a capacitor C3 is connected in parallel to this series connection circuit.

A steady bias to diode D is supplied from the center of the resistor.

The collector output of transistor Q7 is input to transistor Q8 which constitutes an emitter follower, and emitter resistor R
The outputs from both ends of 8 are input to the smoothing capacitor C4.

The output of the smoothing capacitor C4 is input to a current mirror circuit consisting of transistors Qn r Q+2 via a series connection circuit of resistors R, , R, 6,
The output signal of the in-phase detection circuit is derived from the collector output terminal 22 of No. 2.

Further, the output of the smoothing capacitor C4 becomes an input to the control circuit 10 (FIG. 1) via the resistor R0.

The control circuit 10 has a transistor Q9 whose collector load is an LED 11 which is a lock indicator, and further has resistors R1, R, 4 and a transistor Q at its collector output.
A control output circuit consisting of +o is connected, and a muting control signal is derived from the collector output terminal 19 of transistor Q1o.

In this structure, assuming that the current of the constant current source of the first differential circuit is IE1, the output of the multiplier circuit of the first to third differential circuits, that is, the output Av of the output point a, is expressed by the following equation.

Here, R is the resistance of the load resistances R and R', k is the Holtzmann constant, q is the electron density, T is the absolute temperature, and cosω
ct and cos (ωct+φ) are each cosω
ct, *D indicates the opposite phase of cos (ωct+φ).

By transforming equation (3), the following equation is obtained.

As is clear from the above equation (4), among the outputs of the multiplication path, Co
Since S(2ωct+φ) is a signal having a frequency approximately twice that of the carrier wave signal ωct, it is possible to remove it using an LPF (low frequency filter) and derive only the cosφ component.

To this end, the fourth differential circuit and its load, the capacitor C3 and the emitter follower Q8, constitute a selection means for selectively deriving the cosφ component.

The value of the capacitor C3 connected to the load of the fourth differential circuit is selected to remove the cos(2ωct+φ) component.

As a result, an output Av2 expressed by the following equation is obtained at the collector output of the transistor Q7.

? In \, E2 is the constant current value of the fourth differential circuit, and R6 is the value of the load resistor R6.

Note that the second term component of equation (5) is a voltage generated by the DC bias current and has a constant value, and can be ignored by making 6 small.

Note that the diode D is an emitter follower transistor Q8.
It operates in class A mode, and also has a function of temperature compensation effect with transistor Q13°.

Therefore, the output of the emitter follower becomes an output proportional to COSφ, and after being smoothed by the smoothing capacitor C4,
Current value ■ by current mirror circuit.

It is converted into cosφ and derived as output 22.

This output is used as the division input of the division circuit 3.

Furthermore, the smoothed output is introduced into a control circuit 10 to drive a lock indicator 11 and also serves as a muting control signal for a muting circuit (not shown).

According to the circuit shown in Fig. 2, the multiplication circuit is configured as a so-called double-balanced product circuit.
A full-wave rectified output is obtained as the output, which eliminates the drawbacks of conventional product circuits.Therefore, the cosφ signal component can be obtained without distortion, and the control output terminal 19 of the control circuit 10 can accurately match the COSφ signal. The corresponding output will be obtained.

In the above embodiment, the input terminals 20 are connected to e'5-c.
os(ωct+φ) to the pond input terminal 21 as e1=co
sωct was applied, but conversely, e1 and 2 were applied to the input terminal 20.
Of course, it is also possible to apply e/5 to 1 and e/5, respectively.

In addition, in FIG. 2, a low-pass filter is constructed by smoothing capacitors C, , C and resistor R15, but
The low-pass filter can also be constructed using a well-known active filter including active elements, thereby making it possible to improve the filter characteristics.

FIG. 3 shows a division circuit of a stereo demodulation circuit using the muting control signal obtained according to the present invention. An example of a circuit in which a muting operation is performed is shown below.

The input signal e's applied to the input terminal 12 is the output of the PM demodulation circuit 2, and is represented by (LR)·cosφ.

This input signal e's is applied to the base of transistor Q14 via coupling capacitor C6.

The emitters of transistors Q14 and QI5 are commonly connected to form a differential circuit, and differential transistor Q+4
+ A predetermined bias from a bias circuit (not shown) is applied to the base of Q15 via resistors R1 and R18, respectively.

Further, the bases and collectors of diode-configured transistors Qra and Q17 are connected to the bases of the differential transistors Q14 and Q45, respectively, and the emitters of both transistors Q16 and Q1 are commonly connected to the current source 13. .

The current value of this current source 13 is ■.

−cosφ, and the current component is proportional to the output of the in-phase detector 8 in FIG.

The collectors of the differential transistors QI4, Q, and 5 are connected to the power supply Vcc via load resistors RIg and R2o, respectively, and to output terminals 14 and 15 via capacitors C7 and C8.

Furthermore, the common emitter connection point of the differential transistors Q14 and Q15 is connected to the transistor Ql as a switching means.
g' and a resistor R2, it is connected to the current source 16 of the differential circuit 3.

Further, between the collector of the transistor Q14 and the current source 16, and between the collector of the transistor Q15 and the current source 16, a transistor Q19 and a resistor I{22 as switching means, and a transistor Q20 and a resistor R23 are connected, respectively. ing.

The base electrodes of the transistors Q19 and Q20 are connected in common and a bias voltage from the base bias circuit 23 is applied.

Further, a bias voltage from a base bias voltage 24 is applied to the base electrode of the transistor Q18.

The bias circuit 23 includes a resistor R24. From R2 and R26? The bias circuit 24 includes resistors R2, R28 and R2.
It is composed of 9.

A bias circuit 2 is connected to the base electrode of the transistor Q18'.
Control circuit 10 (second
(see figure) are connected.

That is, the collector output terminal 19 of the output transistor Q10 of the control circuit 10 shown in FIG. 2 is the resistor R2.

and connected to the base of the switching transistor Q18 via R3o.

Note that the switch sw1 is a manual switch.

In such a configuration, when the PLL circuit is in a locked state, a signal proportional to cosφ is generated at the output of the in-phase detector 8.

At this time, the transistor Q9 of the control circuit 10 is turned on, the lock indicator 11 lights up, and the transistor Q1o is turned off.

Therefore, in this state, if the base bias of transistor Q, 8° is set to be a bit higher than the common base bias of transistors Q19°, Q20, transistor Q18 will be on, and transistors Q19 and Q2o will be off. .

Therefore, the current ■E of the constant current source 16 is supplied to the divider circuit 3 including the differential circuit, and it becomes active, and the input signal e'5
=(LR)·cOsφ is the current of the current source 13 ■.

Complementary output divided by cosφ, i.e. (L-R)
and (LR) signals are output to the output terminals 14 and 15, and the division circuit 3 is in a normal operating state.

Since the division operation in this case is well known, its explanation will be omitted.

Next, when the PLL circuit is out of the locked state, no signal appears at the output of the in-phase detector 8.

At this time, the transistor Q9 of the control circuit 10 becomes non-conductive, the lock indicator goes out, and the transistor Q1o turns on.

Therefore, the base bias of transistor Q18 decreases, transistor Q18° turns off, and conversely transistors Q19 and Q20 turn on.

Therefore, the current o of the current source 16 is the same as that of the transistor Q, regardless of the on/off states of the transistors Q14 and Q15.

, Q15 from both collectors of the transistor QlO s Q
2o'.

Therefore, the division circuit 3 including the differential circuit becomes inactive and a so-called muting operation becomes possible.

In this case, the DC potential of the collector terminals of transistors QI4 and Q15' becomes a constant value, that is, R19.■E/2R2o.IE/2, regardless of the muting operation.

Therefore, since the potential of the output terminal is changed by the mute ink operation, noise generation can be suppressed.

Incidentally, the capacitors C and CtO are provided to give the earring circuits 24 and 23 a time constant to enable smooth switching during the muting release operation.

Further, by making the switching transistor Q18 have a multi-collector structure, the sum of the collector currents of the other switching transistor Q19 r Q20 and the collector current of the transistor Q18 are both equal to <(IEJ).

Now, let us consider the amount of attenuation of the muting operation when the divider circuit 3 having a differential circuit is in an inactive state, that is, in a muting state.

■For simplicity in this case.

-COSφ20, first, when muting is off, that is, in active operation, and the resistance values of load resistors R19 and R2o are both R, the gain G of the differential circuit is given by the following equation.

kTIBRq G = R/ {-/-} = 1.1.■Eq22kT Here, k is Boltzmann's constant, q is electron density, and T is absolute temperature, respectively.

That is, it can be seen that the gain of the differential circuit is proportional to the current E of the constant current source 16.

Next, during muting operation, all the current flowing through transistor Q18 is commutated to transistors Q19' and Q20, so the current ■E in the above equation (here) becomes zero, and theoretically the input signal is completely attenuated. It can be seen that muting operation is possible.

As detailed above, according to the muting control signal generation circuit of the present invention, the in-phase detection output (cosφ) is generated without distortion, so an accurate muting control signal can be generated using the output signal, thereby preventing malfunctions. This enables stable mi-coating operation with no friction.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a compatible quadrature AM stereo demodulation circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is a case where a muting operation is performed by the output of the circuit shown in Fig. 2. FIG. Explanation of symbols of main parts 8... Common mode detector, 10
...Control circuit, Q1 to Q7, Q13...
・Differential 1・Ran resistor.

Claims (1)

[Claims] 1 es=({1+k(L(t)+R(t)))co
sωct+k(L(t)-R(t)) cos(ω
ct+π/2) ) 0cosφ,φ=tan-1
k {L(t)-R(t))/(1 +k(
L(t)+R(t)} ) (In addition, L(t), R(
t) are the first and second channel signals, ωC is the angular frequency of the carrier signal, and k is the degree of modulation. a first differential circuit having first and second transistors to which a signal corresponding to the carrier signal (or the in-phase signal with the carrier signal) is applied and whose emitters are commonly connected; The modulation signal e
, a signal corresponding to the first transistor) is applied to the input of the second and third differential circuits, and the second differential circuit includes third and fourth differential circuits whose emitters are commonly connected to the collector of the first transistor. The third differential circuit includes a fifth transistor whose emitter is commonly connected to the collector of the second transistor.
and a sixth transistor, the bases of the third and sixth transistors and the bases of the fourth and fifth transistors are connected in common, respectively, and the collectors of the third and fifth transistors are connected in common at a common connection point. and a common connection point of the collectors of the fourth and sixth transistors. A muting control signal generation circuit characterized in that: