JPH0761003B2 - Timing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a clock circuit that counts clock signals by a counting means such as a counter circuit and measures a certain time interval.

(Prior Art) FIG. 3 is a circuit diagram of a conventional timing circuit. In the figure,
11 counts the clock signals to determine n from d1 to dn
It is a binary counter that outputs a bit count signal CO. The clock signal to the binary counter 11 is output from the AND gate 12. The AND gate 12 is supplied with the master clock signal MCP and the control signal CNT output from the latch circuit 13. The latch circuit 13 is supplied with a start signal SRT for starting timing, a stop signal STP for stopping and the master clock signal MCP, and the latch circuit 13 outputs a start signal SRT and a stop signal STP, respectively. The level of the control signal CNT is set by latching in synchronization with the falling edge of the clock signal MCP.

In such a configuration, after the start signal SRT rises to the "1" level, the control signal CNT is set to the "1" level in synchronization with the fall of the clock signal MCP. As a result, the AND gate 12 is opened and the clock signal MCP is supplied to the binary counter 11. The binary counter 11 sequentially counts clock signals every time the clock signal MCP falls. Next, after the stop signal STP rises to the "1" level, the control signal CNT is set to the "0" level in synchronization with the fall of the clock signal MCP. As a result, the AND gate 12 is closed and the supply of the clock signal MCP to the binary counter 11 is stopped. Then, the time interval from the supply of the start signal SRT to the supply of the stop signal STP is output from the binary counter 11 as an n-bit count signal CO. After that, the reset signal RS is supplied to the binary counter 11 to reset the counting state.

By the way, the binary counter 11 is usually constructed by connecting a plurality of synchronous or asynchronous T-type flip-flop circuits in cascade. Therefore, there is an upper limit to the frequency of the clock signal that can be counted. Therefore, it is difficult to perform timekeeping with high accuracy by counting clock signals with high frequencies. Therefore, the T that constitutes the binary counter 11 is
It is conceivable to increase the operating current of the type flip-flop circuit to raise the upper limit of the countable frequency, but there is a problem in that the consumption current increases. Further, if the frequency of the clock signal is increased, the current consumption of the oscillator may increase and the oscillation may become unstable.

(Problems to be Solved by the Invention) As described above, in the conventional timing circuit, the frequency of the clock signal must be raised to perform highly accurate timing, and as a result, the current consumption increases. .

The present invention has been made in consideration of the above circumstances, and an object thereof is to increase the frequency of a clock signal without increasing the frequency.
Therefore, it is an object of the present invention to provide a time counting circuit capable of highly accurate time counting without increasing current consumption.

[Configuration of the Invention] (Means for Solving the Problems) A timing circuit according to the present invention latches a timing start signal and a timing stop signal in synchronization with a transition of a clock signal from a first level to a second level. However, a clock control signal generating means for generating a clock control signal of a flow corresponding to the clock period, an output control means for controlling the output of the clock signal based on the clock control signal, and a clock signal output from the output control means. Counting means for outputting an n-bit counting signal, and a D-type counting means for latching the clock stop signal in synchronization with the transition of the clock signal from the second level to the first level. 1 flip-flop circuit, a signal inverting circuit that inverts the output of the first flip-flop circuit, and a transition of the clock stop signal from the first level to the second level of the clock signal And a logic circuit for obtaining a logical sum signal of the output of the signal inverting circuit and the output of the second flip-flop circuit, which latches in synchronization with Depending on the determination means for determining whether the time point supplied to the clock control signal generation means is before or after the transition time of the clock signal from the second level to the first level, and the determination output by the determination means, The second counting means outputs a counting signal 1 bit lower than the least significant bit signal of the n-bit counting signal of the first counting means.

(Operation) In the time counting circuit of the present invention, another 1-bit counting signal is added to the n-bit counting signal obtained by the counting means for counting the clock signal. Then, it is determined whether the time point at which the clock stop signal is supplied is before or after the time point just in the middle of one cycle of the clock signal. If this is before, the count signal of the added bit is set to "1". "I try to set it to a level. As a result, even when a clock signal having the same frequency as that of the conventional case is counted, the number of bits of the count signal is increased as compared with the conventional case, whereby the clock can be clocked with higher accuracy than before without increasing the frequency of the clock signal. .

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of the clock circuit of the present invention. In the figure, 11 is a binary counter that outputs an n-bit count signal consisting of d2 to dn + 1 by counting clock signals. A clock signal for counting is supplied from the AND gate 12 to the binary counter 11. The AND gate 12 has a master clock signal
The control signal CNT output from the MCP and latch circuit 13 is supplied. The latch circuit 13 is supplied with a start signal SRT for starting timing, a stop signal STP for stopping and the master clock signal MCP, and the latch circuit 13 has a start signal SRT and a stop signal STP, respectively. Is latched in synchronization with the fall of the clock signal MCP to set the level of the control signal CNT.

14 is a judgment circuit. This determination circuit 14 uses the stop signal ST
This determination circuit 14 determines whether the timing at which P rises to the "1" level is before or after the timing at which the signal MCP, which is the middle of one cycle of the master clock signal MCP, rises. The signal DJ is supplied to the trigger terminal (T terminal) of the T-type flip-flop circuit 15. And from this flip-flop circuit 15,
A signal d1 which is one bit lower than the least significant bit signal d2 of the n-bit count signal output from the binary counter 11.
Is output from the Q terminal. The flip-flop circuit 15 and the reset terminal (R
The reset signal RS is supplied to the (terminal) to reset the count state.

Therefore, in the case of the circuit of this embodiment, the counting signal CO is d1 to d1 +
This is (n + 1) bits of n, which is one bit more than the conventional one.

The decision circuit 14 is composed of two D-type flip-flop circuits 21 and 22, two inverters 23 and 24, and a NOR gate 25 as shown in the figure. Then, the stop signal is used as input data of the flip-flop circuits 21 and 22.
STP is supplied, the master clock signal MCP is supplied as a synchronization signal to one flip-flop circuit 21 via the inverter 23, and the master clock signal MCP is directly supplied to the other flip-flop circuit 22. There is. The output Q1 of the flip-flop circuit 21 is supplied to one input terminal of the NOR gate 25 via the inverter 24, and the output Q2 of the flip-flop circuit 22 is directly supplied to the other input terminal of the NOR gate 25.
The output of the NOR gate 25 is supplied to the flip-flop circuit 15 as the determination signal DJ.

Next, the operation of the clock circuit configured as described above will be described. First,
When the start signal SRT rises to the "1" level, the control signal CNT, which is the output of the latch circuit 13, is next set to the "1" level in synchronization with the fall of the clock signal MCP. As a result, the AND gate 12 is opened and the clock signal MCP is supplied to the binary counter 11. After this, the binary counter 11
Every time the clock signal MCP falls, the clock signal is sequentially counted, and the n-bit count signal composed of d2 to dn + 1 is sequentially increased. Next, when the stop signal STP rises to the "1" level, the control signal CNT is set to the "0" level in synchronization with the fall of the clock signal MCP. As a result, the AND gate 12 is closed and the supply of the clock signal MCP to the binary counter 11 is stopped. Then, the time interval from the supply of the start signal SRT to the next supply of the stop signal STP is output from the binary counter 11 as an n-bit count signal. Such an operation is similar to that of the conventional circuit.

By the way, the n-bit count signal obtained by the binary counter 11 has a maximum count error of one cycle of the clock signal MCP depending on the timing when the stop signal STO rises to the "1" level. That is, the maximum error occurs when the stop signal STP rises to the "1" level immediately after the clock signal MCP falls to the "0" level.

Therefore, in the circuit of this embodiment, one bit of the flip-flop circuit 15 is added to the n-bit count signal of the binary counter 11 as the count signal CO, and the level of the added 1-bit count signal is determined by the determination circuit 14. Judgment signal DJ
The number of bits of the counting signal CO is increased without increasing the frequency of the master clock signal MCP, and the accuracy of the counting signal CO is improved by setting the frequency of the master clock signal MCP.

That is, as shown by the solid line in the timing chart of FIG. 2, the timing at which the stop signal STP rises is before the timing just in the middle of one cycle of the clock signal MCP, that is, at the time t1, the signal MCP changes from "1" level to " If it falls to 0 level and then rises to "1" level before rising from "0" level to "1" level at time t2 thereafter, the flip-flop circuit 22 in the decision circuit 14
Takes in the input data, that is, the stop signal STP in synchronization with the rising edge of the master clock signal MCP, so that its output signal Q2 rises to "1" level after time t2 as shown by the solid line in the figure. On the other hand, the flip-flop circuit 21 in the determination circuit 14 receives the master clock signal MC via the inverter 23.
Since P is supplied, this flip-flop circuit 2
1 is the stop signal ST in synchronization with the falling edge of the clock signal MCP
Capture P. Therefore, the output signal Q1 of the flip-flop circuit 21 rises to the "1" level after the fall of the signal MCP at the time t3.

Here, the output of the NOR gate 25 to which the inverted signal of the signal Q1 and the signal Q2 are supplied, DJ is kept at "0" level as shown by the solid line in the figure. Therefore, in this case, this judgment signal
The T-type flip-flop circuit 15 to which DJ is supplied is not triggered, and its output is the least significant bit signal d1 of the count signal CO.
Is set to "0" level.

On the other hand, when the timing at which the stop signal STP rises is after the timing exactly in the middle of one cycle of the clock signal MCP, that is, between the times t2 and t3, the flip-flop circuit in the decision circuit 14 is shown. 22 output signals
Q2 rises to the "1" level after the signal MCP rises to the "1" level at time t4 as indicated by the broken line in the figure.
On the other hand, the flip-flop circuit 21 rises to "1" level after the clock signal MCP falls to "0" level at time t3.

In this case, the output of the NOR gate 25 has the DJ level "1" during the period from the time t3 to the time t4 as shown by the broken line in the figure. Therefore, in this case, the T-type flip-flop circuit 15 to which the determination signal DJ is supplied is triggered and the least significant bit signal d1 of the output count signal CO is set to the "1" level.

Thus, the output signal d1 of the flip-flop circuit 15, which is the least significant bit signal of the count signal CO, is the master clock signal.
Since the signal corresponds to the time for half a cycle of the MCP, it is possible to measure time with higher accuracy than the conventional clock circuit. That is, the time measurement error in this case can be set to the maximum half cycle time of the master clock signal MCP, and it is not necessary to increase the frequency of the clock signal as in the conventional case. Therefore, the disadvantages such as increase in current consumption of the oscillator and instability of oscillation do not occur.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the above embodiment, the case where the binary counter 11 counts in synchronization with the falling edge of the clock signal and the latch circuit 13 latches the signal in synchronization with the falling edge of the clock signal has been explained. Alternatively, a type of counting or latching in synchronization with the rising edge of the clock signal may be used. Further, in this case, the configuration of the determination circuit 14 is changed so as to obtain the determination signal DJ by taking the logical product of the output signal Q1 of the flip-flop circuit 21 and the inverted signal of the output signal Q2 of the flip-flop circuit 22. There is a need.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a time counting circuit capable of highly accurate time counting without increasing the frequency of the clock signal, and thus without increasing the current consumption. it can.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the clock circuit of the present invention, and FIG. 2 is a timing chart of the embodiment circuit,
FIG. 3 is a circuit diagram of a conventional circuit. 11 …… Binary counter, 12 …… And gate, 13 ……
Latch circuit, 14 ... Judgment circuit, 15 ... T-type flip-flop circuit.

Claims (1)

[Claims] 1. A timekeeping device for latching a timekeeping start signal and a timekeeping stop signal in synchronization with a transition of a clock signal from a first level to a second level, and generating a timekeeping control signal of a length corresponding to a time period. Control signal generating means, output control means for controlling output of the clock signal based on the clock control signal, and first coefficient for outputting clock signal output from the output control means to output n-bit count signal A D-type first flip-flop circuit for latching the clock stop signal in synchronization with the transition of the clock signal from the second level to the first level, and an output of the first flip-flop circuit. A signal inverting circuit for inverting, and a D-type second flip-flop circuit for latching the clock stop signal in synchronization with the transition of the clock signal from the first level to the second level. And output and the second of said signal inverting circuit
A logic circuit for obtaining a logical sum signal with the output of the flip-flop circuit, and the time at which the clock stop signal is supplied to the clock control signal generating means changes from the second level of the clock signal to the first level. Depending on the determination means for determining whether it is before or after the transition time, and in accordance with the determination output from the determination means, a count signal 1 bit lower than the least significant bit signal of the n-bit count signal of the first coefficient means is output. And a second counting means for outputting.