JPS5849953B2 - address buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to address buffer circuits, and is particularly directed to address buffer circuits for semiconductor memory devices.

As an address buffer circuit for a semiconductor memory circuit, one that uses a dynamic flip-flop circuit as shown in FIG. 4 to achieve high-speed operation is known (Japanese Patent Publication No. 49-96640).

In this circuit, an insulated gate field effect transistor (hereinafter referred to as MISFET) QQ is TTL (Tran
It is a transfer gate when converting from the slstor Transistor Logic level to the MISFET logic level, and it transfers the address input signal Ai to the switching MISFET of the dynamic flip-flop.
It is transmitted to Q5 and the gate of MISFET Q8 of the output circuit.

MIS that acts as a load for the above flip-flop circuit
FETQ2 and Qa supply current to a pair of outputs A and A when both chip selection signal CE and clock pulse ψ become '1' (explained in case of n-channel MISFET below high level), and input signal Ai The values of the outputs A and A of the flip-flop circuit are defined according to the following.

MISFETQ6 that constitutes the output circuit. Q8 is the output A of the flip-flop circuit.

One of them turns on in response to A and selects a predetermined decoder.

Also, MIFETQ7. Q, is when no chip is selected (0-“
1'') to specify both the outputs ai and ai.

In the address buffer circuit configured as described above, the chip selection signal CE is used as a power source for the flip-flop circuit.

Correspondingly, a direct current flows through one of the inverter circuits (Q2°Q4) or (Qa, Q5) constituting the flip-flop circuit.

Since this direct current is relatively large, a driver circuit using a bipolar transistor with a large current capacity is required as a pulse generation circuit for forming this chip selection signal.

Therefore, this address buffer circuit is difficult to handle in terms of system implementation.

Furthermore, when the chip selection signal CE is 'o' (earth level), the input signal Ai is '1' (high level), and the clock pulse ψ is '1', the MII
Input current flows through SFETQl and Q2.

Since several address buffer circuits are usually provided in one semiconductor memory device, a large amount of current is consumed as a whole.

When a memory system is constituted by a plurality of such semiconductor memory devices, an even larger current is consumed as a whole, which is not preferable.

Furthermore, when driving a selected word line, one of the output circuits that should output a low level performs an undesirable operation in which the series-connected MISFETs Qa-Q7 or Q8pQ that constitute it are both turned off.

In other words, the output of the output circuit becomes floating.

Therefore, the level of the decoder that receives the output of the output circuit will fluctuate due to noise or capacitive coupling, etc.
There is a risk that the circuit may malfunction.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide an address buffer circuit that reduces the current of the input circuit and prevents the output from becoming a floating level. .

Hereinafter, the present invention will be specifically explained with reference to the drawings along with examples.

FIG. 1 is a circuit diagram showing an example of an address buffer circuit according to the present invention.

In the figure, a signal CE' synchronized with a chip selection signal CE is applied to the gates of MISFETs Q2 and Q3, which act as loads for a dynamic flip-flop circuit composed of MISFETs Q2 to Q5.

Fixed voltage on the drains of MISFETQ2 and Q3■
is supplied.

D MISF” which is one input of the flip-flop circuit
Transfer gate MISFE is installed at the gate of ETQ5.
Address input signal Ai is applied via TQ.

The output circuit has the following configuration to prevent each output from becoming floating when selecting a chip.

That is, MISFETQ6. The output A of the flip-flop circuit is supplied to the gate of MISFETQ6 of one inverter circuit consisting of Q7, and MISFETQ8
．． The above MISFE of the other inverter circuit consisting of Q9
'The gate of FQ8 is the output A of the flip-flop circuit.
is supplied.

MISFETQ7 that constitutes one of the above inverter circuits
The gate of the other inverter circuit (Q8. Q9
') is supplied to the gate of the MISFET Q9 which constitutes the other impark circuit (and the output ') of the one inverter circuit Q6fi Q?') is supplied to the gate of the MISFET Q9 constituting the other impark circuit.

Switching MI that constitutes the above flip-flop circuit
SFETQ+, Q5 and MISFETQ7 on the reference potential (earth level) side that constitutes the impark circuit. Q9
is a signal C that becomes “1” (high level) when no chip is selected.
MISFETQ, o-Q, , where E is supplied to the gate
3 are connected in parallel.

Accordingly, the outputs A, A of the flip-flop circuit and the outputs ai, ai of the output circuit are both set to 'O' at the time of chip selection.

In addition, MISFETQ6 and Q which constitute the above output circuit
As shown in the figure, the drain of No. 8 is connected to a fixed voltage power supply V.
DD or chip selection signal CE (+ when selecting chip)
1111) is supplied.

In this embodiment, focusing on the fact that the flip-flop circuit in the semiconductor memory device only needs to send out its output signal for 30 to 40 ns from the time of chip selection, the loads MISFETs Q2 and Q3 are driven by 1. A signal CE' for this purpose is formed by a circuit as shown in FIG.

The circuit shown in FIG. 2 is constructed to satisfy the following logical expression (1).

CB' - CE ・(ai + ai) (
1) In the previous stage circuit in Fig. 2, the load MIS
Switching MISFETQ, connected in series to FETQ, 4, and connected in parallel to each other.

Output signals ai and ai of the output circuits are supplied to Q16, respectively.

The output of this previous stage circuit connects the subsequent stage load MISFETQ.
, □ are driven, and the MISs are connected in parallel with each other and in series with the load MISFETQ, , 7.
FETQ18. Q19 is the same as the previous stage circuit, output signal ai
, ai.

Furthermore, a chip selection signal CE is supplied to the drain of MISFETQ9□ that constitutes the circuit at the subsequent stage.

The operating waveforms of the circuit configured above are shown in FIG.

As shown in FIG. 3, in response to chip selection signal CE, output a1. ] has a time delay determined by the flip-flop circuit and the output circuit, so the output CE' of the circuit in FIG. 2 is ai or 2i after CE becomes 1''.
The signal becomes "1'' until it becomes "1".

Only the minimum necessary current consumption is allowed to flow through the dynamic flip-flop circuit driven by the signal CB', and the power consumption of the circuit is reduced.

By the way, MISFETQ2. When Q3 is driven by chip selection signal CB instead of signal CE', the pulse width is 1.
00 to 150 nS, the DC current consumption when using the signal CB' is less than half.

To configure a dynamic flip-flop circuit,
Load MISFETQ2. Q3 is driven by signal CE'.

Therefore, no current flows between the input terminal Ai and the CE' terminal, and since the fixed power supply voltage VDl is supplied, no reverse current flows from the input terminal Ai to the power supply terminal DD.

Further, the signal CE' for dynamic driving is applied to the load MISFETQ2. Since it is applied to the gate of Q3, the current capacity can be made small.

In addition, between the outputs, the paths are complementary switching MISF
ETQ6. Output signal ai by Q7 (Qa, QQ)
, ai, the respective outputs ai and □ will not be floating.

When the chip is not selected, MISFETQto-Qta is turned on by the signal CE which becomes 1'' at that time.
The output line of the flip-flop circuit is grounded.

As a result, the initial value of the refrigeration 1f0f circuit is determined before its operation, and it operates in accordance with the input signal Ai.

In the above explanation, MISFET is an n-channel MISFET.
Although the case using FET has been explained, the present invention is not limited to this.
A similar configuration can be achieved using a P-channel MISFET.

In this case, it is necessary to reverse the polarity of the power supply voltage.

In addition, the load MISFETQ2 of the flip-flop circuit
, Q3 may be driven by the chip selection signal CB.

However, in this case, care must be taken that more direct current is consumed than necessary.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an address buffer circuit showing an example of the present invention, FIG. 2 is a circuit diagram of a pulse forming circuit according to the present invention,
FIG. 3 is an operational waveform diagram of the circuit of FIG. 2, and FIG. 4 is a circuit diagram of a conventional address buffer circuit. Q1~Q13...MISFET.

Claims (1)

[Claims] 1. A first pair of MISFETs whose gates and drains are cross-connected to each other, and a first pair of loads connected between the respective drains of the pair of MISFETs and a power supply terminal. a first flip-flop circuit comprising a MISFBT and outputting a complementary signal corresponding to an address signal to the drains of the first pair of MISFETs, and a second pair of MISFETs whose gates and drains are cross-connected to each other.
and a second flip-flop circuit comprising a pair of load elements therefor and outputting a complementary signal responsive to the complementary signal supplied from the first flip-flop circuit to the drains of the second pair of MISFETs. , the first flip-flop circuit has a control signal obtained based on the chip selection signal that connects the first pair of load MISFETs.
An address buffer circuit characterized in that the operation of the address buffer circuit is suppressed by supplying a signal to the gate of the address buffer circuit. 2. The address buffer circuit according to claim 1, wherein the control signal has a pulse width shorter than that of the chip selection signal.