JPS5849952B2 - address buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to address buffer circuits, and is particularly directed to address buffer circuits for semiconductor memory devices.

As an address buffer circuit for a semiconductor memory circuit, one that uses a dynamic flip-flop circuit as shown in FIG. 4 to achieve high-speed operation is known (Japanese Patent Publication No. 49-96640).

In this circuit, the insulated gate field effect transistor (hereinafter referred to as MI 5FET) Ql is TTL (Tra
nsistor Transistor Logic
) level to the MISFET logic level, and is a transfer gate when converting the address input signal Ai to the MISFET switching MISFET of a dynamic type flip-flop.
It is transmitted to Q5 and the gate of MISFETQs in the output circuit.

M I acting as a load of the above flip-flop circuit
S F E T Q2 t Qs is such that the chip selection signal CE and clock pulse φ are both 1" (high level or below n
(described in the case of a channel MISFET), current is supplied to the pair of outputs A and A, and the values of the outputs A and A of the flip-flop circuit are defined according to the input signal Ai.

MISFETQ6 that constitutes the output circuit. One of Q8 turns on according to the outputs A and A of the flip-flop circuit,
Select a given decoder.

Also, when MISFETQ7゜Q9 is not selected (CE
= "l"), and both the outputs ai and ai are set to "0".

In the address buffer circuit configured as above, the chip selection signal CE is the electrode output signal ai of the flip-flop circuit.
, ai.

Further, a chip selection signal CE is supplied to the drain of MISFETQ17 that constitutes the circuit at the subsequent stage.

The operating waveforms of the circuit configured above are shown in FIG.

As shown in FIG. 3, the outputs al and al have a time delay determined by the flip-flop circuit and the output circuit with respect to the chip selection signal CE, so the output CE of the circuit in FIG. ai or a after becoming 1″
Until i becomes 11 or 94? The signal becomes +111.

In the dynamic flip-flop circuit driven by this signal CE', only the necessary minimum current consumption flows, and the power consumption of the circuit can be reduced.

By the way, when MISFETQ2゜Q3 is driven by chip selection signal CE instead of signal CE', the pulse width is 1.
00 to 150 ns, the DC current consumption when using the signal CE' is less than half.

In the above dynamic flip-flop circuit, the load MISFETQ2. Since Q3 is driven by the signal CE', no current flows between the input terminal Ai and the CE' terminal.

Also, MISFETQ2. Since the fixed power supply voltage VDD is supplied to the drain of Q3, no current flows backward from the input terminal Ai to the power supply terminal VDD.

Furthermore, since the signal CE' for dynamic driving is applied to the gates of the loads MI 5FET Q2 and Q3, the current capacity thereof can be reduced.

The output circuit is a complementary switching MISFETQ6
．． Output signals ai, ai by Q7 (Q8.Q9)
Since each output ai is configured to form
, ai will never be floating.

When the chip is not selected, the MI5FETs QIO and Qll are turned on by the signal CE which becomes 1'' at that time, so the outputs A and A of the flip-flop circuit are maintained at 0'''.

As a result, the flip-flop circuit has an initial value determined before its operation, and operates according to the input signal Ai.

Similarly, when the chip is not selected, MISFETQ12
, Q13 is also turned on, so the output ai of the output circuit is
ai is also maintained at O''.

By keeping the outputs ai and ai at 0'', MI
Positive feedback operation between SFETs Q7 and Q9 is stopped.

Therefore, when the chip is selected again,
Outputs al and al are changed to a level corresponding to input address signal Ai at a relatively high speed.

The illustrated address buffer circuit is composed of a first-stage flip-flop circuit and an output circuit that receives the output of this flip-flop circuit and is essentially a flip-flop circuit. In response, complementary signals ai, ai of appropriate level and relatively high speed are formed.

That is, the first stage flip-flop circuit in the address buffer circuit includes MISFETQ4 and Q5 provided between the pair of output points and the grounding point of the circuit, and the gates of these MISFETQ4 and Q5.・
By having a positive feedback path that cross-connects the drains to each other, it outputs complementary signals A and A that are relatively high-speed in response to the input address signal Ai and have a level appropriate for the next stage circuit. It becomes possible to do so.

The next stage circuit, that is, the output circuit is MISFETQ7
, Q9 and these MISFETQ7. Having a positive feedback path that cross-connects Q9 to each other forms complementary signals ai, ai that are relatively fast and brought to appropriate levels for inputs A, A.

As shown in FIG. 1, the flip-flop circuit and the output circuit of the flip-flop circuit structure that receives the output thereof have the following characteristics.

That is, the first stage flip-flop circuit receives the signal CE'
Immediately after being activated by
and A are not set to a good high level or a good low level.

Complementary signals A and A are connected to MISFETQ4. The levels are then changed to appropriate levels depending on the operation of the circuit consisting of Q5 and its positive feedback path.

If MISFETQ7 and Q9 are removed from the output circuit of FIG. 1, that is, the output circuit of FIG.
If the configuration is similar to the conventional circuit shown in the figure, the signal level of the output signals ai and ai that should be set to low level is not good immediately after the una operation starts as described above in the first stage flip-flop circuit. level signal A or A
This will result in a slight lift.

That is, the signal level of the output signals ai and ai that should be set to a low level is no longer set to a sufficiently low level.

On the other hand, MISFETQ as shown in FIG.
7. In the output circuit with Q9, MISFETQ
By the positive feedback operation of the circuit including the feedback of the signal ai to the gate of MISFET Q9 and the feedback of the signal ai to the gate of MISFETQ9, the signal that should be at a low level among the signals ai and ai is brought to a good low level. Ru.

Accordingly, the address buffer circuit with the configuration shown in FIG.
This enables reliable operation of the decoder circuit that receives the output.

In the address buffer circuit of FIG. 1, the output circuit is
M I S FET Q6. The structure is such that only the gates of Q and 8 receive signals A and A, respectively, and only a relatively light capacitive load is formed on the first stage flip-flop circuit.

Therefore, the output circuit allows the output signals A, A of the first stage flip-flop circuit to change at high speed.

The illustrated output circuit consists of a series-connected load MISFET, e.g., Q6, and a drive MISFET, e.g., Q6, connected in series.
Since the MISFETs 7 and 7 are configured to operate in a complementary manner, both of the series-connected MISFETs are prevented from being constantly turned on, resulting in low power consumption.

The illustrated output circuit also loads the signals A, A
Since the configuration is received by F E T Qs and Q6, each can be configured with a small number of circuit elements.

In the above explanation, MISFET is an n-channel MISFET.
Although the case using FET has been explained, the present invention is not limited to this.
A similar configuration can be made using a p-channel MISFET.

In this case, it is necessary to reverse the polarity of the power supply voltage.

In addition, the load MISFETQ2 of the flip-flop circuit
, Q3 may be driven by the chip selection signal CE.

However, in this case, care must be taken that more direct current is consumed than necessary.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an address buffer circuit showing an example of the present invention, FIG. 2 is a circuit diagram of a pulse forming circuit according to the present invention,
FIG. 3 is an operational waveform diagram of the circuit of FIG. 2, and FIG. 4 is a circuit diagram of a conventional address buffer circuit. Q, ~Q13-・-・-MI S FET.

Claims (1)

[Claims] 1. First and second Ml5FETs whose gates and drains are cross-connected to each other, a third Ml5FET whose drain-source path is connected between the drain of the first MISFET and a power supply terminal, and the second Ml5FET. A fourth Ml5FET having a drain-source path connected between the drain of the first . 2nd Ml5F
5th connected in parallel to ET. a sixth Ml5FET, and supplies address signals complementary to each other to the gates of the third and fourth Ml5FETs, and also supplies the gates of the fifth and fourth Ml5FETs.
An operation control signal is supplied to the gate of the sixth Ml5FET, and the first. An address buffer circuit characterized in that a complementary signal is obtained from the drain of a second Ml5FET. 2. First and second Ml5FETs whose gates and drains are cross-connected to each other, a third Ml5FET whose drain-source path is connected between the drain of the first MISFET and the power supply terminal, and the drain of the second Ml5FET and the power supply terminal. and a fourth Ml5FET having a drain-source path connected between the first and second transistors, respectively. 2nd Ml5
The 5th one connected in parallel to the FET. The third. The complementary signal of the flip-flop circuit is supplied to the gate of the fourth M15FET, and the fifth M15FET is supplied with the complementary signal of the flip-flop circuit. An operation control signal is supplied to the gate of the sixth Ml5FET, and the first and second Ml5FETs
An address buffer circuit characterized in that a complementary signal is obtained from the drain of an ET.