JPS597158B2 - address buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to address buffer circuits, and is particularly directed to address buffer circuits for semiconductor memory devices.

As an address buffer circuit for a semiconductor memory circuit, one that uses a dynamic flip-flop circuit as shown in FIG. The gated field effect transistor (hereinafter referred to as MISFET) Q1 is a TTL (Transistor Transistor).
storLogic) level to MISFET logic level, and is a transfer gate when converting the address input signal Ai to the dynamic flip-flop switching MISFETO5 and the output circuit MISFE
Inform the gate of TQ8.

MIS that acts as a load for the above flip-flop circuit
For FETQ2 and Q3, chip selection signal CE and clock pulse φ are both "1" (high level or below n channel M
ISEFT), current is supplied to the pair of outputs A and A, and the values of the outputs A and A of the flip-flop circuit are defined according to the input signal Ai. One of the MlSFETs Q6 and Q8 constituting the output circuit is turned on in response to the outputs A and A of the flip-flop circuit to select a predetermined decoder. MISFETs Q7 and Q8 are turned on when the chip is not selected (CE = "1") and specify the outputs ai and ai as "o".In the address buffer circuit configured as above, the chip selection signal CE is connected to the flip-flop One of the inverter circuits Q2 that constitutes the flip-flop circuit is used as a power source for the flip-flop circuit.
, Q4 or through Q3 and Q5. Since this direct current is relatively large, a driver circuit using a bipolar transistor with a large current capacity is required as a pulse generation circuit for forming this chip selection signal. Therefore, this address buffer circuit is difficult to handle in terms of system implementation. Also, the chip selection signal CE is 40゜(
When the input signal Ai is at 1 (high level) and the clock pulse φ is 61, M
Input current flows through ISFETQl and Q2.

Since ten or more address buffer circuits are normally provided in one semiconductor memory device, a large amount of current is consumed as a whole. When a memory system is configured with a plurality of such semiconductor memory devices, it consumes a larger amount of current as a whole, which is undesirable.Furthermore, when driving a selected word line, one of the output circuits that should output a low level performs an undesirable operation in which the series-connected MISFETs Q6, Q7 or Q8, Q9 constituting it both become 0FF.

In other words, the output of the output circuit becomes floating. Therefore, the level of the decoder receiving the output of the output circuit fluctuates due to noise or capacitive coupling, and there is a risk that the circuit may malfunction. The purpose of the present invention is to
An object of the present invention is to provide an address buffer circuit which can prevent an output from floating, can set its level appropriately, and can operate at high speed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to embodiments and drawings.

FIG. 1 is a circuit diagram showing an example of an address buffer circuit according to the present invention.

In the figure, a signal CE synchronized with a chip selection signal CE is applied to the gates of MISFETs Q2 and Q3, which act as loads for a dynamic flip-flop circuit composed of MISFETs Q2 to Q5.

A fixed voltage V is applied to the drains of MISFETQ2 and Q3. O
is supplied. An address input signal Ai is applied to the gate of MISFETQ5, which is one input of the flip-flop circuit, via a transfer gate MISFETQl.

The output circuit has the following configuration to prevent each output from floating when selecting a chip. That is, the output A of the flip-flop circuit is supplied to the gate of the MISFET Q6 of one inverter circuit consisting of MISFETs Q5 and Q7, and the MISFET
The output A of the flip-flop circuit is supplied to the gate of the M[S light Q8 of the other inverter circuit consisting of FETs Q8 and Q. The output Ai of the other inverter circuit Q8, Q9 is supplied to the gate of the MISFET Q7 constituting the one inverter circuit, and the output Ai of the MISFET Q, constituting the other inverter circuit, is supplied to the gate of the MISFET Q7, which constitutes the other inverter circuit. An output revision is provided. Switching MISFET Q4, Q that constitutes the above flip-flop circuit, and MISFET Q7, Q on the reference potential (earth level) side that constitutes the inverter circuit.
, is a MISFET QlO-Ql3 whose gate is supplied with a signal σ which becomes 6-bit (high level (C)) when the chip is not selected.
are connected in parallel. Correspondingly, the outputs A and X of the flip-flop circuit and the output Ai of the output circuit are both set to 80 degrees when the chip is not selected. Note that, as shown in the figure, the drains of MISFETs Q6 and Q8 constituting the above output circuit are connected to a fixed power supply voltage V.

O or chip selection signal CE (“r” when selecting a chip)
In this embodiment, we focus on the fact that the flip-flop circuit in the semiconductor memory device only needs to send out its output signal for 30 to 40 ns from the time of chip selection. MISFET
A signal CE' for driving Q2 and Q3 is formed by a circuit as shown in FIG. The circuit in Figure 2 is expressed by the following formula (1)
O2, which is configured to satisfy the logical formula of
In the circuit at the front stage in the figure, the load MISFETQ
Output signals Al and al of the output circuit are respectively supplied to switching MISFETs Ql6 and Ql6 which are connected in series to I4 and in parallel with each other.

The output of this previous stage circuit connects the subsequent stage load MISFETQ.
MISFET Ql7 is driven, and the MISFs are connected in parallel to each other and connected in series to the load MISFET Ql7.
ETQl8,Ql, same as the previous stage circuit, output signal Ai,
Driven by 7 guns. Further, a chip selection signal CE is supplied to the drain of MISFET Ql7 that constitutes the circuit at the subsequent stage. The operating waveforms of the circuit configured above are shown in FIG.

As shown in FIG. 3, since the output Ai,i〒 has a time delay determined by the flip-flop circuit and the output circuit with respect to the chip selection signal CE, the output CE' of the circuit of FIG. The signal becomes "11" after CE becomes 61 and until Ai or Ai becomes "1". Only the minimum necessary current consumption is allowed to flow through the dynamic flip-flop circuit driven by this signal CE', thereby reducing the power consumption of the circuit.

By the way, if MISFE'RQ2 and Q8 are driven by the chip selection signal CE instead of the signal CE', the pulse width is 100 to 150 ns, so the signal CE! The DC current consumption is less than half when using . In the above dynamic flip-flop circuit, its load MISFET
Since Q2 and Q3 are driven by the signal CE', no current flows between the input terminal Al and the CE' terminal.

Furthermore, since the fixed power supply voltage 00 is supplied to the drains of MISFETQ2 and Q3, no current flows backward from the input terminal Ai to the power supply terminal DD. Furthermore, the signal CE' for dynamic driving is applied to the load MISF.
Since it is applied to the gates of ETQ2 and Q3, its current capacity can be reduced. The output circuit consists of complementary switching MISFETs Q6, Q7 (Q8,
Since the output signal Ai, 7 is formed by the output signals Ai, 7, the respective outputs do not float.

When the chip is not selected, the MISFETs QlO-Ql3 are turned on by the signal CE which becomes "1" at that time.
The flip-flop circuit is reset.

As a result, the flip-flop circuit has its initial value determined before its operation, and can operate in response to the newly supplied input signal Ai. The illustrated address buffer circuit is composed of a first-stage flip-flop circuit and an output circuit that receives the output of this flip-flop circuit and is essentially a flip-flop circuit. In response, a complementary signal Ai at an appropriate level and at a relatively high speed is generated.
, forming 7 blocks.

That is, the first-stage flip-flop circuit in the address buffer circuit has MISFETs Q4 and Q5 provided between the pair of output points and the grounding point of the circuit, and the gates and drains of these MISFETs Q4 and Q6 that are connected to each other by cross-connecting them. By having a positive feedback path connected to the input address signal Ai, the complementary signal A is relatively fast in response to the input address signal Ai and is brought to an appropriate level for the next stage circuit.
, A can be output.

The next stage circuit, that is, the output circuit is MISFETQ7,
By having a positive feedback path that cross-connects MISFETs Q, Q, and these MISFETs Q7, Q9, a complementary signal Ai, which is relatively high-speed and at an appropriate level for inputs A and A, is formed. do.

As shown in FIG. 1, the flip-flop circuit and the output circuit of the flip-flop circuit structure that receives the output thereof have the following characteristics.

That is, the first stage flip-flop circuit receives the signal CE7.
Immediately after being activated, the complementary signal A. 15A is not set to a good high level or a good low level.

The complementary signals A<15A are then changed to appropriate levels depending on the operation of the circuit consisting of MISFETs Q4 and Q5 and their positive feedback paths. If MISFETs Q7 and Q are removed from the output circuit of FIG. 1, that is, if the output circuit of FIG. 1 has the same configuration as the conventional circuit of FIG. The signal level that should be set to low level is slightly raised by the signal A or X, which is at an unfavorable level immediately after the first stage flip-flop circuit starts operating as described above. That is, the output signals Ai and A
The signal level of i that should be set to a low level is no longer set to a sufficiently low level. On the other hand, the first
In the output circuit equipped with MISFETQ7, Q as shown in the figure, the positive feedback operation of the circuit including the feedback of the signal Ai to the gate of MISFETQ7 and the feedback of the signal to the gate of MISFETQ9, Signals Ai and Ai
Among them, the signals that should be at low level are set at a good low level. Accordingly, the address buffer circuit having the configuration shown in FIG. 1 enables reliable operation of the decoder circuit receiving its output. In the address buffer circuit shown in FIG. 1, the output circuit is configured to receive signals A and X only at the gates of MISFETs Q6 and Q8, respectively.
Only a relatively light capacitive load is configured for the flip-flop circuit of the second stage.

Therefore, the output circuit receives the output signals A, 7l. enables high-speed changes in The illustrated output circuit has a configuration in which a series-connected load MISFET, e.g., Q6, and a drive MISFET, e.g., 9, connected in series are operated in a complementary manner.
It is avoided that both ISFETs are constantly turned on, resulting in low power consumption.

The illustrated output circuit also connects the signals A,'A to the load MISFE.
Since it is configured by TQ3 and Q6, it can be configured with a small number of circuit elements. In the above explanation, MISFET is n-channel MISFET.
Although a case has been described in which a p-channel MISFET is used, the present invention is not limited to this, and a similar configuration can be made using a p-channel MISFET.

In this case, it is necessary to reverse the polarity of the power supply voltage. In addition, the load MISFETQ2, Q3 of the flip-flop circuit
may be driven by the chip selection signal CE.

However, in this case, care must be taken that more direct current is consumed than necessary.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram of an address buffer circuit showing an example of the present invention, FIG. 2 is a circuit diagram of a pulse forming circuit according to the present invention,
FIG. 3 is an operating waveform diagram of the circuit of FIG. 2, and FIG. 4 is a circuit diagram of a conventional address buffer circuit.

Claims (1)

[Claims] 1. A first flip-flop circuit that forms a first complementary signal A, @A@ by receiving an address input signal Ai; By receiving the first complementary signal A, @ to the first and second output terminals.
and an output circuit that outputs second complementary signals ai, @ai@ corresponding to A@, the output circuit has gates and drains cross-connected to each other, and outputs the second complementary signals ai, @ai@ from each drain. A pair of M from which @ai@ is output
An address buffer circuit comprising a second flip-flop circuit equipped with an ISFET. 2. The output circuit includes a pair of MISFETs whose drains are connected to the first and second output terminals and whose gates and drains are cross-connected to each other, and between the first and second output terminals and the power supply terminal. Claim 1, characterized in that the MISFET is comprised of a pair of MISFETs whose drain and source paths are connected to each other and whose respective gates are supplied with complementary outputs of the first flip-flop circuit. Address buffer circuit.