JPS5851285B2 - sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence controller equipped with a function to monitor input/output elements, and its purpose is to monitor input/output elements without using advanced equipment such as a computer and without having an interrupt function. To provide a sequence controller that can monitor online.

With the development of sequence controllers that utilize computer technology, it has become possible to quickly and reliably discover faults in controlled objects using this sequence controller as an intermediary.

However, in the past, there was a problem that the equipment was outdated and expensive because it required the use of a high-end computer, and online monitoring was only possible with a sequence controller that had an interrupt function. Ta.

The present invention was proposed in view of such problems, and even if a conventional sequence controller does not have an interrupt function, it is possible to connect input/output elements online without using a high-end machine by simply adding a simple device. It is characterized by being able to perform monitoring.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the entire sequence controller implementing the present invention, in which 1 is a main memory circuit such as a core memory that stores sequence control data of sequence cycles programmed in advance, and 2 is a main memory circuit. 1 is a program counter that specifies a memory address and sequentially reads predetermined control data; 3 is a memory data register that stores the control data read from the memory address specified by program counter 2; and 4 is a memory data register 3. An instruction register 5 to which control data stored in the instruction register 4 is set via a data bus DB is a memory gate that controls setting of the control data to the instruction register 4.

The instruction word used as the control data is composed of an operation section that indicates the type of instruction, and an address section that specifies an address such as an address of an internal input/output element, a memory address of the main memory circuit 1, etc., which will be described later.

The types of commands include an input/output test command that determines the on-off state of an internal input/output element, an output command that turns on or off an output element among internal input/output elements based on the determination result, and an output command that turns on or off an output element among the internal input/output elements based on the determination result. There are jump commands that cause a jump, and special commands used in monitoring programs.

Table 1 shows the types of command words and their meanings.

Reference numeral 6 denotes an instruction decoder which decodes the operation part of the control data set in the instruction register 4 and issues various command signals.

Reference numeral 10 indicates an external input element 10a1, such as a limit switch or a push button switch, which is turned on and off by checking the operation of each operating element of the controlled device such as a machine tool, and an external input element 10a1 that instructs the operation of each operating element of the controlled device. On-
This is a group of elements connected to the outside, including an external output element 10b such as an output IJ-, a solenoid, etc., which is turned off.

Numeral internal input elements 11a are paired with each external input element 10a and convert the on-off operating state of the external input element 10a into an electrical signal form at an internal level of the sequence controller, and each external output element 10b. A large number of output elements that form a pair and turn on and off the external output element 10b by receiving internal level output signals, and other output elements that do not directly exchange signals with the external input/output element group 10 but receive internal level output signals. This is an internal input/output element group consisting of a large number of internal output elements 11b such as operating timer elements, relay elements, and dummy elements.

Reference numeral 12 denotes an internal input/output element 11a at an address specified by the control data from among the internal input/output element group 11.

Input selector 12a that selects 11b, output selector 1
2b, and the on-off state of the selected internal input/output elements 11a and 11b is H" when it is on, and +1 L IJ when it is off.
In particular, if the control data is an output command, the output signal sent from the test flag circuit 14 via the line OT is the internal output element selected by the output selector 12b. 11b.

The test flag circuit 14 receives various command signals decoded by the instruction decoder 6, and if the command signals are input/output test commands, the test flag circuit 14 receives the command signals from the internal input/output elements 11a, 11b input via the line IT. −
It determines whether the off signal satisfies the test command condition and stores the result, and if the command signal is an output command, it outputs an on-off output signal based on the stored determination result on the line. It is designed to be output to OT.

Reference numeral 15 denotes a control pulse generation circuit that generates control pulses for timing the execution of each command, and in this example, control pulses OP, CL1 to CL6 as shown in FIG. 3 are periodically generated. - The command ◆ is executed in one cycle period from when this control pulse OP is issued until when CL6 is issued.

16 is a control circuit for the main memory circuit 1; 17 is a gate at a memory address specified by the program counter 2; 18 is a save register that stores the memory address of the program counter 2 when a jump instruction is given; and 19-23 are This is a gate that is opened and closed by the control pulse to execute a predetermined command.

Reference numeral 100 denotes a monitoring circuit which forms the main part of the present invention, and a functional block diagram of this circuit 100 is shown in FIG.

First, to conceptually explain the function performed by this monitoring circuit 100, a group of input conditions including one output element for controlling this is taken as an operation unit, and the presence or absence of an abnormality is determined for each operation unit. Based on this determination result, each input condition of the operation unit with the abnormality is examined in order on-line and stored in the monitor storage device 200, and this stored result is read and displayed off-line.

The operator is able to decipher the displayed content and find out the fault condition that caused the abnormality.

Here, the monitor program is divided so that it can monitor the input conditions for each operation unit and find failure conditions in the input conditions, and the operation that is determined to be abnormal by the discrimination program that determines whether there is an abnormality in each operation unit. A monitor program corresponding to the unit is selected, and the above-mentioned monitoring is performed.

In FIG. 7, 200 is a monitor storage device for storing monitoring results, 210 is a memory address switching circuit, and 220 is a first
control means.

The first control means 220 issues a monitor start command (switch 10
6) is given, the sequence control is switched to execution of a determination program that determines the presence or absence of an abnormality for each operation unit.

Reference numeral 230 denotes a second control means, which enables the monitor storage device 200 and the memory address switching circuit 210 when it is determined that there is an abnormality in any operation unit by executing a determination program, and determines that there is an abnormality. The input test circuit 120 executes the monitor program for the determined operation unit.
The monitoring results given by the above are sequentially stored in the storage device 200.

Furthermore, when the monitor program ends, the memory device 200 and the memory address switching circuit 210 are disabled and the sequence control is returned to.

This achieves online monitoring without stopping scanning.

Reference numeral 240 denotes an abnormal circuit number display device, in which an abnormal circuit number corresponding to the operation unit determined as abnormal by the discrimination program is set and displayed.

250 is a display circuit for displaying the monitoring results stored in the storage device 200, which is displayed by manually switching the storage address switching circuit 210.

The operator will be able to read this and find the cause of the abnormality.

Next, details of each of the above-mentioned functional blocks will be explained with reference to FIG. 2.

The monitor storage device 200 is shown as a storage circuit 130, and the storage address switching circuit 210 is shown as a sequential counter 115.

The first control means 220 corresponds to the push button switch 106 and the D flip-flop 109, and by closing the switch 106, a command to start monitoring is given, and the D flip-flop 109 is set.

This set signal (Q terminal output) is applied to address 3770 of the input selector 12a.

As a result, the sequence control program (o
Subsequently to addresses 0300 and 0300 (addresses ooo to 0277), the determination program for addresses 0300 and below is executed, and the presence or absence of an abnormality is determined for each operation unit.

If there is an abnormality in the startup circuit, the abnormal circuit number oooi is set in the register 101 by the command at address 0304 and displayed on the display 103 as the abnormal circuit address display device 240, and the command at address 0305 is set to 4>5ON3770. flag 107 is set.

The operand 3770 of this instruction selects the address 3770 of the output selector 12b in FIG. It will be set.

When flag 107 is set, gates 13 and 118 are opened, enabling storage circuit 130 and sequential counter 115.

By executing the startup circuit monitor program at addresses 0306 to 0316 in FIG.
20, the signals as the monitoring results are sequentially stored in the storage circuit 130.
is memorized.

End of the monitor program, ie 10F of address 0317
The flag 107 is reset by 3770, and the next address command 4>JMPOOOO returns to the sequence control program to continue scanning.

By resetting the flag 107, the sequential counter 115 can be manually incremented by the switch 105, and the monitor result can be read out and displayed on the display 134 as the display circuit 250.

Note that 111 is a light emitting diode for displaying a monitoring start command that lights up when the flip-flop 109 is set, and the Q terminal output of the flip-flop 109 is inputted through the inverter 112.

A memory address display 119 externally displays the contents of the sequential counter 115, and the contents of the sequential counter 115 are inputted thereto.

Reference numeral 120 denotes an input/output test circuit that tests whether the on-off states of the input/output elements 10a and 10b satisfy the conditions of the input/output test command. Internal input/output elements 11a, 11 being sent out on TNA and line IT
b on-off signal is input, test command 4>TFA is input to the AND gate 122, and the line IF
The on-off signals of the internal input/output elements 11a and 11b sent above are inputted via the inverter 123, and the outputs of both ant gates 121 and 122 are sent to the or gate 1.
24.

Therefore, if the conditions of the test command are satisfied, ゛′H′
; If the condition is not satisfied, an L'' signal is output as the determination result.

134 is input through the output inverter 136 of the data output terminal Do-out of the memory circuit 130, and a light-emitting diode 135 for an OK display that lights up when the output of the data output terminal Dout is H''; Terminal Dou
The output of t is input, and this output terminal Dout
It is composed of a light emitting diode 137 for displaying NG, which lights up when the output is °゛L''.

Next, the operation of the sequence controller configured as described above will be explained with reference to FIGS. 3 to 5. The content of the program counter 2 is incremented by 1 by the control signal UPI generated when the control pulse CL6 is generated, and the control pulse C.L.
The gate 17 is activated by the control signal MST generated when 2 occurs.
is opened, and the control data at the memory address specified by the program counter 2 is read out and stored in the memory data register 3.

And the control signal G generated when the control pulse CL3 is generated
The memory gate 3 is opened by M, and the control pulse C
The instruction register 4 is opened by the control signal 5GISR generated when L3 is generated, and the control data stored in the memory data register 3 is set in the instruction register 4.

When the control data is set in the instruction register 4 in this way, the address signal set in the address field is sent onto the line AD, and the internal input/output elements 11a and 11b at the address specified by the address signal are turned on/off. However, when it is on, it is sent out as an "HD signal", and when it is off, it is sent out on line IT as an "L" signal.

The control data set in the instruction register 4 is changed according to the program every time the control pulse CL3 occurs, and therefore the address signal sent on the line AD and the on-off signal sent on the line IT are changed by the control pulse. It will be updated every time CL3 occurs.

By controlling each circuit in this manner, the program shown in FIG. 5 is executed.

In executing this program, memory addresses 1 to 277
When the execution of the sequence control program stored in
0 is read out, and the test flag circuit 14 determines whether the flip-flop 109 of the monitoring circuit 100 is set or not.

Therefore, if the flip-flop 109 is in the reset state, the control data JMNOOOO at the memory address 301 is executed to jump to the memory address 0, and the sequence control program is executed again, but the monitoring program is not executed.

When the operator desires to perform monitoring, the operator presses the push button switch 106 for external command to start monitoring and sets the flip-flop 109.

When the flip-flop 109 is set, the light emitting diode 111 for a monitoring start command is turned on.

Further, the push button switch 104 for clearing the sequential counter is pressed to set the content of the sequential counter 115 to O.

If the flip-flop 109 is set, the program does not jump to memory address O, but moves to address 302 and thereafter, and the discrimination program is executed.

In the determination program, the starting circuit is first checked.

That is, the control data TFAO100 at memory address 302
is read out and activated, and the on-off state of the internal input/output element CR1 corresponding to IJ-CRI is detected by the test flag circuit 14.
Judgment will be made.

Starting relay CR1 is a relay that is always on during normal operation, so if it is off, there is an abnormality in the starting circuit.

Next, control data JMNO321 at memory address 303 is executed.

Therefore, if relay CR1 is off, that is, if the starting circuit is abnormal, the control data AB at the next memory address 304
NOOOI is read and monitoring of the startup circuit begins.

As a result, control data A is generated at the time when control pulse CL5 is generated.
Address part 0001 of BNOOOI 5 register 101
is set, and the abnormal circuit number display 103 displays 厘1, which means that the starting circuit is abnormal.

Next, the control data 5ON3770 at the memory address 305 is read out, so that the flip-flop 1, which is the monitoring start flag circuit, is activated at the time when the control pulse CL5 is generated.
07 is set.

When the flip-flop 107 is set, the control pulse C
At the time of occurrence of L6, the content of the counter 115 is sequentially incremented by 5+1 and becomes 1.

By reading the control data TNAOOOI at the next memory address 306, the test command +TNA and the on/off state of the internal input/output element LS2 at input/output address 1 are input to the test circuit 120, and whether the internal input/output element LS2 is on or not is input to the test circuit 120. For example, the test circuit 120 outputs an "H" signal, and if it is off, a °L" signal is output.

This output is then written to memory address 1 of the storage circuit 130 by the generation of the control pulse CL4.

The control pulse CL6 generated after that causes the counter 1 to
The contents of 15 are increased by +1 to become 2.

Next, the control data TFAOOOO2 at memory address 307 is read, and the test command 4>TFA and the on-off state of internal input/output element LS3 at input/output address 2 are input to the test circuit 120. If it is off, the test circuit 120 sends a °゛H''H'' signal,
If it is on, the °“Ln signal is output.

This output is then written to memory address 2 of the storage circuit 130 by the generation of the control pulse CL4.

Then, the content of the sequential counter 115 is incremented by +1 to 3 by the control pulse CL6.

In this way, the control data from address 306 to address 316 is read, and if the contacts making up the starting circuit are normally closed contacts, test command + TNA is used, and if they are normally closed contacts, test command + TFA is applied to those contacts. The test circuit determines the on-off state of each internal input/output element LS2 to CR2 corresponding to
are stored in each memory address 1 to 9.

When the control data TNAO101 at memory address 316 is executed and the determination of all internal input/output elements corresponding to each contact forming the startup circuit is completed, the control data TNAO101 at memory address 316 is executed.
The control data 5OF 3770 is read out, and the flip-flop 107, which is an internal input/output element specified by the address field 3770, is reset.

When flip-flop 107 is reset, flip-flop 109 is also reset immediately.

As a result, neither the sequential counter 115 nor the storage circuit 130 will operate from this point forward, and the monitoring results for each operation can be effectively stored and held.

When control data JMPOOOO of the next memory address 320 is read out, it jumps to memory address 0.

This ends the monitoring and the sequence control program is executed again.

Note that by resetting the flip-flop 109, the light emitting diode 111 is turned off and the operator is notified that the monitoring has ended.

On the other hand, if the starting relay CR1 is on, that is, if the starting circuit is normal, the control data JMNO321 at the memory address 303 is executed to check the cycle circuit that jumps to the memory address 321 and advances to unit)I.

In other words, the control data TFA0200 at memory address 321
, control data TFA0176 at memory address 322, and control data TFA0177 at memory address 323 are sequentially executed.

In this case, the unit advance cycle circuit is abnormal only when all of the internal input/output elements at input/output addresses 200, 176, and 177 are off, and otherwise normal.

Therefore, input/output addresses 200 and 176. If all 177 internal input/output elements are off, the next memory address 324
After execution of the control data JMNO340, the control data ABNOOO2 of the memory 325 is read out and monitoring of the unit advance cycle circuit is started.

In this case, the abnormal circuit number display 103 displays A2, which means that the unit advance cycle circuit is abnormal.

On the other hand, if any one of the internal input/output elements at input/output addresses 200, 176, and 177 is on, after the control data 0340 at memory address 324 is executed,
After jumping 40 degrees, the next circuit is checked.

The program is executed in this way, and the presence or absence of an abnormality is determined for each operation unit.The on-off state of each internal input/output element corresponding to the input conditions that make up the operation unit that has an abnormality is determined, and the determination result is is stored in the memory circuit 130, and if there is no abnormality in any circuit, the memory address 3
By executing the control data JMPOOOO of 70, a jump is made to memory address O, and the sequence control program is executed again.

In addition, the time required to complete one cycle of the program is extremely short, and since the monitoring program always returns to the sequence control program after execution, monitoring is executed while the sequence control is being executed, and the interrupt function is This means that online monitoring can be performed even if the sequence controller is not equipped, and in this case there is no need to use a host computer, which is extremely practical.

The operator presses push button switch 1 for external command to start monitoring.
When it is confirmed that the light emitting diode 111 that was turned on by pressing 06 is turned off, the monitoring result is displayed externally.

First, the sequential counter clear push button switch 104 is pressed to set the content of the sequential counter 115 to O.

Next, the contents of the sequential counter 115 are incremented by 1 to become 1.

The input of the read/write instruction terminal R/W of the memory circuit 130 is “H”.
I+, when the contents of the sequential counter 115 become 1, the contents stored at memory address 1 of the storage circuit 130 are output to the data output terminal Dout, and the contents of the memory address 1. If the memory content of is H"', that is, if the on-off state of the internal input/output element tested first according to the monitoring program satisfies the conditions of the test command, O
The light emitting diode 135 for K display is lit, and if the stored content of memory address 1 is L'', that is, the on-off state of the internal input/output element tested first according to the monitoring program satisfies the conditions of the test command. If not, the NG display light emitting diode 137 is lit.

Further, the memory address display 119 displays the content 1 of the sequential counter 115.

When the push button switch 105 for sequential counter addition is pressed again, the content of the sequential counter 115 becomes 2, and the memory circuit 13
The light emitting diodes 135 and 137 display whether or not the contents stored in memory address 2 of 0, that is, the on-off state of the internal input/output element tested second according to the monitoring program, satisfies the conditions of the test command. 2 is also displayed on the memory address display 119.

In this way, each time the push button switch 105 for sequential counter addition is turned off, the contents of the sequential counter 115 are incremented by 1, and the stored contents of the memory circuit 130 are displayed on the light emitting diodes 135 and 137 in order from memory address 1. The contents are displayed on the memory address display 119.

Therefore, the operator must check the number displayed on the abnormal circuit number display 103, the number displayed on the memory address display 119, and the number displayed on the abnormal circuit number display 103.
By looking at the display of the light emitting diode 133 for K display and the light emitting diode 137 for NG display, it is possible to know whether an abnormality has occurred in the circuit of the internal input/output element system due to the collapse.

For example, if the display number on the abnormal circuit number display 103 is A1 and the display number on the memory address display 119 is 2, and the NG display light emitting diode 137 is turned on, the second This means that an abnormality has occurred in the circuit of the internal input/output element LS3 that was tested first.

FIG. 6 shows another embodiment of the monitoring circuit 100.

In FIG. 6, components having the same reference numerals as those in FIG. 2 have the same functions as the components in FIG.

In addition, in FIG. 6, the input/output selection circuit 12 shown in FIG.
, register 101. The AND gate 102 and abnormal circuit number display 103 are omitted.

In FIG. 6, 140 is the input/output test circuit 1
In this embodiment, when a pulse is input to the T terminal, the J
It is composed of a plurality of J- flip-flops 1401 to 140-n, which are set when the terminal input is "°H" and unconditionally reset when the R terminal input becomes "L'".

The output of the input/output test circuit 120 is input to the J terminal of each flip-flop 140-1 to 140-n, the output of the anti-game 114'f-1 to 141-n is input to the TE terminal, and the R terminal is input to the output of the input/output test circuit 120. The pulses generated by the push button switch 104 for successive counter clearing are inputted via the inverter 142.

A selector 143 decodes the contents of the sequential counter 115 and selects the AND gates 141-1 to 141-n.
Enable N411, and when it is 2, Antogame-1-14
1-2, when it is n, it is ant game t14
1-n are enabled.

The output of the AND gate 131 is input to a single input terminal of each AND gate 141-1 to 141-n.

144 is a display circuit for externally displaying the stored contents of the memory circuit 140; each flip-flop 140- of the memory circuit 140;
It is composed of a plurality of light emitting diodes 144-1 to 144-n connected to Q output terminals 1 to 140-n.

Therefore, according to this embodiment, while the flip-flop 107 serving as the monitoring start flag circuit is set, the results of the determination of the on-off state of the input/output elements determined by the input/output test circuit 120 are stored in the order of determination. circuit 140
The stored contents are simultaneously displayed externally by the light emitting diodes 144-1 to 144-n of the display circuit 144.

If the determination result is OK, the flip-flop is set and the light emitting diode is turned on.

Therefore, the operator only has to determine that the input/output element corresponding to the light emitting diode that does not light up is the cause of the failure.

In this embodiment, there is no need to operate the memory push button switch of the memory circuit 130 as in the embodiment shown in FIG.

In addition, in the actual case described above, the monitoring program uses test instructions 4>TNA and TFA, but the AND gate 121 of the input/output test circuit 120
Test life'eTNA, TNO.

TNE is input through the OR gate, and test command 4>TFA, TPO is input to the AND gate 122.

If TFE is input through the OR gate, all test commands + TNA, T
FA, TNO, TPO, TNE, TFE can be used.

In addition, a monitoring circuit 1 is provided in the test flag circuit 14.
If the same test circuit as the input/output test circuit 120 used in 00 is provided, the input/output test circuit 120 is not provided in the monitoring circuit 100 and the test circuit provided in the test flag circuit 14 is monitored. It may also be used as the circuit 100.

Furthermore, although the storage circuit 130 or 140 stores the determination result by the input/output test circuit 120, it is not necessarily necessary to store the determination result, and the on-off state of the input/output element sent on the line IT is stored. It may also be stored directly.

Alternatively, the operator can judge whether it is normal or abnormal when it is off.

As described above, according to the present invention, even if the sequence controller does not have an interrupt function, online monitoring can be performed without stopping sequence control, and since a host computer is not required, monitoring can be performed easily and at low cost. It has the following advantages.

In addition, during the monitoring execution process, the presence or absence of an abnormality is determined for each operating unit, and the circuit number corresponding to the operating unit with an abnormality is displayed, and only the input conditions are monitored and stored, so it is possible to investigate the cause of the failure based on the monitoring results. can be done easily and reliably.

Furthermore, the storage device for storing the monitoring results has the advantage of requiring a relatively small capacity as long as it can store the human power conditions corresponding to one operation unit.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, and FIG. 1 is a schematic block diagram of a sequence controller according to the present invention, and FIG.
The figure is a detailed diagram of the monitoring circuit 100 in FIG.
3 is a timing chart of control pulses, FIG. 4 is a sequence circuit diagram, FIG. 5 is a schematic diagram of a program sheet in which a sequence control program and a monitoring program are written, and FIG. 6 is another embodiment of the monitoring circuit 100. FIG. 7 is a functional block diagram of the monitoring circuit 100. 1...- Main memory circuit, 2... Program counter, 4... Instruction register, 6... Instruction decoder, 14...
...Test flag circuit, 10... External input/output element group, 11... Internal input/output element group, 12
...Input/output selection circuit, 12a...Input selector, 12b...Output selector, 100.
... Monitoring circuit, 101 ... Register, 103 ... Abnormal circuit number display, 104
・・・・・・Push button for sequential counter clearing, 1
05...Push button switch for sequential counter addition, 1
07...Monitoring start flag circuit (flip-flop on J-), 115...Sequential counter, 119...Memory address display, 120...
...Input/output test circuit, 130.140...
Memory circuit, 134...Display circuit, 143...
... Selector, 144 ... Display circuit, 200
. . . Monitoring storage device, 210 . . . Memory address switching circuit, 220 . . . First control means,
230... Second control means, 240...
- Abnormal circuit number display device, 250... Monitor result display circuit.

Claims (1)

[Claims] 1 Sequentially read out the sequence control data programmed in advance and stored in the storage device, import the on/off state of the input/output element specified by the read control data, and turn on/off the input/output element specified by the read control data. Determine whether the state satisfies the conditions of the input/output test command commanded by the control data, select the output element commanded by the control data, and execute the control using the result of the determination as a condition. In a sequence controller that sequentially controls a controlled object by turning on and off the selected output element according to an output command specified by data,
A monitor program is stored in a storage area different from a sequence control data storage area of the storage device, and this monitor program monitors a group of input conditions for controlling one of the output elements as a unit of operation. It is separated into multiple monitor programs and multiple discrimination programs that determine the presence or absence of an abnormality, and the on/off state of each input/output element, which is the input condition for each operation unit, or whether this on/off state satisfies the conditions of the test command. a monitor storage device 130 that stores the determination result of whether or not there is a child;
140, and a memory address switching circuit 115 for sequentially switching the memory addresses of the monitor memory devices 130 and 140 in synchronization with the execution of the monitor program. A first control means 106, 1 that reads and executes a determination program that determines the presence or absence of an abnormality for each operation unit.
09 is provided, and the monitor storage device 130,
A second control means 107, 13, 118, and 131 is provided to enable the memory address switching circuit 140 and the memory address switching circuit 115, and to output and display an abnormal circuit number assigned to an operation unit determined to have an abnormality. Display device 10L103
and a display circuit 134.144 for displaying the contents stored in the monitor storage device 130, 140.