JPS5851410B2 - Mask alignment accuracy measurement method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring mask alignment accuracy that can measure mask alignment deviation between two masks with high precision.

Conventionally, to measure mask alignment accuracy, it has been common to measure the deviation of the measurement pattern using a microscopic microscope, and vernier methods and moiré stripe methods have also been proposed; Even with these methods, measurements require the operator to look through a microscope and align the cursor or read the scale, and these methods require large amounts of measurement in terms of time and effort. The drawback was that it was difficult.

This invention has been made in view of the above points, and is a parallel MOS having a stacked gate of a first gate and a second gate.
The object of the present invention is to provide a method for measuring mask alignment accuracy that makes it possible to detect mask alignment deviations with high accuracy as electrical characteristics of parallel MOS transistors by fabricating transistors on semiconductor wafers.

The present invention will be explained below based on examples.

FIG. 1 is a plan view of an example of parallel MOS transistors for measurement fabricated on a semiconductor wafer in order to carry out the present invention, with the uppermost protective film and electrode lead-out conductor removed.

Although this figure is a plan view, necessary parts are shaded for easy understanding.

By creating the parallel MOS transistor shown in FIG. 1 and a parallel MOS transistor whose parallel direction is rotated by 90 degrees, it is possible to measure mask alignment accuracy in two directions perpendicular to each other.

In FIG. 1, 4 is a field oxide film, 5 is indicated by diagonal lines downward to the right, 6 is the first gate oxide film and the first gate electrode formed by the first mask, and 7 is indicated by needle lines downward to the left. , 8 is a second gate oxide film and a second gate electrode formed by the second mask, 9 is a source/drain region, and 11 is an aluminum (Al) wiring.

In order to make it easier to understand the structure of the parallel MO8I-transistor for measurement, its cross-sectional structure will be explained along the steps of its creation.

2A to 2D are cross-sectional views corresponding to the cross section taken along the line ■-■ in FIG. 1 at the main stages of fabricating a parallel MOS transistor.

As shown in FIG. 2A, a silicon oxide (Si02) film 2 and a silicon nitride (Si2N+) film 3 are sequentially formed on a silicon substrate 1, the S12N4 film 3 in the field region is removed by etching, and the remaining Si2N4 film 3 is removed by etching. Field oxide film 4 is formed using film 3 as a mask.

Next, as shown in FIG. 2B, the SiO2 film 2 and the Si
Remove the 2N4 film 3 and add a new SiO2 film to the removed area.
A polycrystalline silicon film is formed, and through a process of mask alignment using a first mask and etching, a first gate consisting of a first gate oxide film 5 and a first gate electrode 6 is formed.

Subsequently, as shown in FIG. 2C, after oxidizing the silicon substrate 1 and the first gate electrode 6 to form a 5I02 film, a polycrystalline silicon film is formed on this SiO2 film, and a second mask is formed. Through the process of mask alignment and etching, a second gate consisting of a second gate oxide film 7 and a second gate electrode 3 is formed, and then a field oxide film 4, a first gate electrode 6 and a second gate are formed. Source/drain regions 9 are formed using the gate electrode 8 as a mask.

Next, as shown in the second diagram, 10 SiO2 films are formed, etched except for the necessary parts, and Al is vapor-deposited.
Wiring 11 is formed.

Finally, the protective film 12 and the necessary electrode extraction conductor 13
, and complete the creation of the parallel MO8) transistor for measurement.

It goes without saying that the above-mentioned parallel MO8) transistor can be made using either an n-channel MOS transistor or a p-channel MOS transistor.

Furthermore, the gate electrode is not limited to polycrystalline silicon, but may also be made of molybdenum, tungsten, or the like.

FIG. 3 is a cross-sectional view of the parallel MOS transistor corresponding to the cross section taken along the line ■--■ in FIG. 1.

In the parallel MOS transistor shown in FIG. 1, if the second gate electrode 8 is shifted from the first gate electrode 6 by ΔL in the positive direction of the Y direction shown in the figure due to misalignment of the masks, then Ll and L2 are L+△L and L, respectively
−ΔL (L is the gate length of the gate formed by the first gate electrode 6 and the second gate electrode 8 when there is no mask misalignment), and the gate length of the gate formed by the first gate electrode 6 and the second gate electrode 8 is The electrical characteristics of the two parallel MOS transistors (with a common source) are differential, and mask alignment errors are electrically magnified and measured.

At this time, the short channel effect of the threshold voltage Vth can be used as the electrical characteristic to be measured of the MOS transistor, but the Vth
Since the change in th is not linear, it is easier to measure using mutual conductance gm, which has good linearity.

FIG. 4 is a graph showing an example of gm-1/Leff characteristics.

Leff indicates the effective channel length (the value obtained by subtracting the length of the source/drain region below the gate by lateral diffusion from the gate length), and as shown in Figure 4, it is the reciprocal of the effective channel length Leff. Since the relationship with gm shows good linearity, this characteristic is used to convert mask misalignment into an electrical quantity.

For example, if Leff-3 μm is used as the reference (when there is no mask alignment misalignment), if there is a deviation of 0.5 μm in the positive direction of the Y direction shown in FIG.
z Leff2 = 2.5 μm, and the difference in gm between the two transistors is differential, so in this example it is approximately 20 μm.
The difference is 0μ8-1.

Therefore, mask alignment deviation can be measured by measuring the gm of each MOS transistor and taking the difference.

Since gm can be measured stably, mask misalignment down to about 0.1 μm can be detected using this method.

Moreover, since the measurement is electrical, even a large amount of measurement can be easily and quickly performed.

The above describes the case of detecting mask misalignment in the Y direction shown in Figure 1, but as mentioned above, a parallel MO8) transistor whose parallel direction is rotated by 90' from the parallel MOS transistor shown in Figure 1 is created. For example, mask misalignment in the X direction shown in FIG. 1 can be measured in a similar manner.

As detailed above, in the method for measuring mask alignment accuracy according to the present invention, two stacked gates of a first gate and a second gate are arranged in parallel, and the overlapped portion of the first gate and the second gate is Since mask alignment deviation is measured from the differential electrical characteristics of parallel MOS transistors formed in opposite directions in the array direction, mask alignment accuracy can be performed with high precision, high speed, and high efficiency. .

[Brief explanation of drawings]

Fig. 1 is a plan view of an example of a parallel MOS transistor for measurement, Fig. 2 A-D is a cross-sectional view at the main stages of manufacturing the parallel MOS transistor for measurement, and Fig. 3 is an AI' for the gate electrode of the parallel MOS transistor for measurement. FIG. 4, which is a cross-sectional view of a portion where wiring exists, is a graph showing gm-1/Leff characteristics. In the figure, 1 is a silicon substrate, 5 is a first gate oxide film, 6 is a first gate electrode, 7 is a second gate oxide film,
8 is a second gate electrode, 9 is a source/drain region, 1
1 is an Al wiring. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. Two first masks on a semiconductor substrate using a first mask.
gates are formed in parallel, and using a second mask, each of the two second gates is overlapped with one of the first gates, and the overlapping portions are mutually aligned in the arrangement direction of the first gates. Mask alignment characterized by measuring mask alignment misalignment between the first mask and the second mask from differential characteristics of electrical characteristics of parallel MOS transistors created by forming parallel MOS transistors in opposite directions. Accuracy measurement method. 2. The method for measuring mask alignment accuracy according to claim 1, characterized in that two sets of parallel MO8) transistors are created so that their parallel directions are perpendicular to each other.