JPS5851433B2 - Method of manufacturing lateral field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a so-called lateral field effect transistor (hereinafter abbreviated as ``horizontal F'ETJ'') in which source, drain, and gate electrodes are formed on one main surface of a semiconductor chip. It is about improvement.

Figure 1 is a plan view showing a conventional horizontal FET chip;
The figure is a sectional view taken along the line ■-■ in FIG. 1.

In the figure, 1 is a semi-insulating substrate, 2 is an active layer with a mesa-shaped structure formed by epitaxial growth on a part of the main surface of the semi-insulating substrate 1, and 3 and 4 are each on the surface of the active layer 2. The active layers 2 face each other at a predetermined distance.
A source electrode and a drain electrode 5 are formed across a part of the upper part and a part of the main surface of the semi-insulating substrate 1, and a part of the source electrode and a drain electrode 5 crosses the middle part of the opposing part of the source electrode 3 and the drain electrode 4 to form the active layer 2. A gate electrode 100 is formed across a part on the upper part and a part on the main surface of the semi-insulating substrate 1, and 100 is the horizontal FET.
It's a tip.

Next, the state in which the chip 100 is mounted on the ceramic substrate of the package will be described with reference to the plan view shown in FIG.

In the figure, 6 is a ceramic substrate of a package on which the chip 100 is mounted, and 7 is a metallized film formed on a part of the surface of the ceramic substrate 6. When the chip 100 is mounted, the source lead of the package is pulled out. The chip attachment parts 8 and 9 are each made of a metallized film formed on a part of the surface of the ceramic substrate 6, and are connected to the drain lead of the package and connected to the drain electrode 4 of the chip 100. 10 is a source bonding wire connecting the source electrode 3 of the chip 100 and the chip mounting part 7; A drain bonding wire 12 connects the drain electrode 4 of the chip 100 and the drain bonding pad 8, and a gate bonding wire 12 connects the gate electrode 5 of the chip 100 and the gate bonding pad 9.

By the way, when the chip 100 is mounted on a package, there are
It is also necessary to bond and connect the gate electrode 5 and the gate bonding pad 9 with a source bonding wire 10, a drain bonding wire 11, and a gate bonding wire 12, respectively.

These bonding connections are extremely difficult tasks, so we aim to reduce these bonding connections.
In order to improve workability, an improved horizontal FET chip, as shown in cross-section in FIG. 4, has been used.

In the figure, 101 is an improved lateral FET chip.

13 is formed on the back surface of the chip 101 to be brazed on the chip mounting portion 7 of the ceramic substrate 6 shown in FIG.
This is a metal film connected to the source electrode 3.

As described above, since the metal film 13 is formed on the back surface of the chip 101, the source electrode 3 of the chip 101 and the chip mounting part 7 are electrically connected at the same time as the chip 101 is brazed onto the chip mounting part 7. Connected.

Therefore, as shown in FIG. 3, the bonding work using the source bonding wire 10 becomes unnecessary, and the work of mounting the chip 101 onto the ceramic substrate 6 can be simplified.

Further, since the source wiring resistance due to the source bonding wire 10 can be reduced, electrical characteristics can be improved.

Next, a conventional method for manufacturing the chip 101 will be described with reference to cross-sectional views shown in FIGS. 5a-f.

First, a growth layer 2a is formed on the first main surface of a semi-insulating semiconductor crystal wafer 1a on which a plurality of chips 101 are to be formed [FIG. 5a].

Next, mesa etching is performed on the wafer 1a, leaving a portion of the growth layer 2a which is to become the active layer 2 of each chip 101 (FIG. 5b).

Next, a part on each active layer 2 and the wafer 1a connected thereto are
The source electrode 3 of the chip 101 is formed so as to span the upper part, and the drain electrode 4 facing the source electrode 3 is formed (FIG. 5C).

Next, a source electrode 3 and a drain electrode 4 are formed on each active layer 2.
The gate electrode 5 of the chip 101 is formed in the middle part of the opposing part [FIG. 5d].

Next, a first layer of the wafer 1a including the tops of the active layer 2, the source electrode 3, the drain electrode 4, and the gate electrode 5 is formed.
After bonding, for example, a glass plate 14 on the main surface of the wafer 14 with wax 15, the second main surface of the wafer 1a is polished to form a wafer 1b having a predetermined thickness (FIG. 5e).

Thereafter, the glass plate 14 and wax 15 are removed.

Then, a photoresist film 16 is deposited on the entire surface of the wafer 1b, except for a part on each source electrode 3 and a part of the continuous exposed part of the wafer 1b (FIG. 5f).

Next, with the photoresist film 16 attached, the wafer 1b is cut and divided into chips to become the chips 101 using, for example, a scriber or a diamond saw.
These divided chips are subjected to electroless plating to form a metal film 13 connected to the source electrode 3, and if necessary, the thickness of the metal film 13 is increased by electroplating, and then photoresist is applied. The membrane 16 is removed from the chip to produce the chip 101 shown in FIG.

However, in such a conventional manufacturing method, since it is necessary to form the metal film 13 after cutting and dividing the wafer 1b into chips, the manufacturing process is complicated and the workability is poor.

The present invention was made in view of the above-mentioned drawbacks, and instead of dividing a semi-insulating semiconductor crystal wafer into chips, a metal film connected to a source electrode formed on the surface of the chip is connected to the chip. An object of the present invention is to provide a method for manufacturing a horizontal FET that can be formed on the back side of a lateral FET.

FIGS. 6a-f are cross-sectional views illustrating the production steps of an embodiment of the method according to the invention.

In the method of this embodiment, the production steps shown in FIGS. 5a and 5b are exactly the same as in the conventional example, so illustration and explanation of these production steps will be omitted here.

First, a groove 17 is formed in the periphery of the portion of the wafer 1a which has gone through the manufacturing steps shown in FIG. 5 and is to become a horizontal FET chip [FIG. 6a].

Next, a source electrode 3 and a drain electrode 4 facing each other are formed on each active layer 2 by a selective plating method or a selective vapor deposition method, and a metal film 18 connected to the source electrode 3 is formed on the inner wall surface of the valley groove 17. form [Fig. 6b].

Next, a gate electrode 5 is formed across each active layer 2 across the intermediate portion of the opposing portions of the source electrode 3 and drain electrode 4 [FIG. 6C].

Next, for example, a glass plate 14 is bonded with wax 15 on the first main surface of the wafer 1a, including the tops of the active layer 2, the source electrode 3, the drain electrode 4, the gate electrode 5, and the metal film 17. Then, the second main surface of the wafer 1a is polished to form a wafer 1b having a predetermined thickness (FIG. 6d).

At this time, the depth of the groove 17 is set so that a part of the metal film 18 formed on the inner wall surface of the groove 17 is exposed on the back surface of the wafer 1b.

Thereafter, a metal film 19 connected to the metal film 18 is formed on the back surface of the wafer 1b by electroless plating, and if necessary, the thickness of the metal film 19 is increased by electroplating.

Finally, after removing the glass plate 14 and the wax 15, the wafer 1b is automatically divided into horizontal FET chips having the same structure as the chip 101 shown in FIG. 4 [FIG. 6f].

In this method of manufacturing a horizontal FET chip, the metal film 18 can be formed at the stage of creating the metal film 19 without dividing into individual chips as in the conventional example shown in FIG. Therefore, it is possible to simplify the manufacturing process and improve workability.

In the above embodiment, the groove 17 is formed all around the periphery of the chip, but it is not necessary and the source electrode 3
A groove may be formed only in the periphery of the chip near the chip, and the chips may be divided into individual chips from this groove.

As explained above, according to the method according to the present invention, the entire peripheral area of the first main surface of the semiconductor wafer on which a plurality of horizontal FET chips are to be formed is formed. a step of forming a groove of a predetermined depth on the periphery or a part thereof; a step of forming a first metal film connected to the source electrode of the chip of the horizontal FET on the inner wall surface of the groove; polishing the main surface of the semiconductor wafer to expose a part of the first metal film formed on the inner wall surface of the groove, the first metal film exposed on the second main surface of the semiconductor wafer; The method includes a step of forming a second metal film connected to the second main surface on the second main surface, and a step of dividing the semiconductor wafer into individual chips of the horizontal FET from the valley groove. The second metal film connected to the source electrode formed on the front surface of the chip can be easily formed on the back surface of the chip without dividing it into individual chips as in the conventional example.

Therefore, the manufacturing process can be simplified, and
Workability can be improved.

[Brief explanation of the drawing]

Figure 1 is a plan view showing a conventional horizontal FET chip;
The figure is a cross-sectional view taken along the line ■-■ in Figure 1, Figure 3 is a plan view showing the chip mounted on the ceramic substrate of the package, and Figure 4 is a cross-sectional view showing the improved horizontal FET chip. Figures 5a to 5f are the above-mentioned improved horizontal F.
FIGS. 6a-6f are cross-sectional views showing each manufacturing step of a conventional method for manufacturing an ET chip, and FIGS. 6a-6f are cross-sectional views showing each manufacturing step of an embodiment of the method according to the present invention. In the figure, 1 is a semi-insulating substrate, 1a and 1b are wafers, 2 is an active layer, 2a is a growth layer, 3 is a source electrode,
4 is a drain electrode, 5 is a gate electrode, 6 is a ceramic substrate, 7 is a chip mounting part, 8°9 is a drain bonding pad and a gate bonding pad, respectively, 10, 1
1 and 12 are bonding wires, 13 is a metal film, 14 is a glass plate, 15 is wax, 16 is a photoresist film, 17 is a groove, 18 is a first metal film, 19 is a second metal film, 100, 101 are horizontal FET chips. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Grooves of a predetermined depth on the entire circumference or part of the periphery of the formation area of each chip on the first main surface of the semiconductor wafer on which a plurality of field effect transistor chips are to be formed. forming a first metal film that forms the source electrode of the field effect transistor of each chip and extends to the inner wall surface of the valley groove; polishing the second main surface of the semiconductor wafer; exposing a part of the first metal film formed on the inner wall surface of the valley groove, a second metal connected to the first metal film exposed on the second main surface of the semiconductor wafer; A method for manufacturing a lateral field effect transistor, comprising the steps of: forming a film on the second main surface; and dividing the semiconductor wafer into individual semiconductor chips from the grooves.