JPH063837B2 - Method for manufacturing three-dimensional semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a three-dimensional semiconductor integrated circuit in which a semiconductor single crystal layer on which a circuit element is formed has a multilayer structure.

[Conventional technology]

In recent years, as the densification of two-dimensional semiconductor integrated circuits is approaching its limit, development of three-dimensional semiconductor integrated circuits is in progress. Compared with a two-dimensional semiconductor integrated circuit, a three-dimensional semiconductor integrated circuit not only allows circuit elements to be integrated at a higher density, but also facilitates parallel processing of information, speeds up the processing speed, and further increases the processing speed. It has the advantage that it can be functionalized.

Conventionally, such a three-dimensional semiconductor integrated circuit has been manufactured through the following steps. For example, when using a silicon semiconductor, first, the upper surface of a silicon wafer on which predetermined circuit elements and electrodes are formed is covered with an insulating layer, and a polycrystalline silicon film is grown on the insulating layer by a low temperature vapor deposition method or the like. Next, the polycrystalline silicon film is partially melted and recrystallized by using a laser, an electron beam or the like, and an upper circuit element is formed in the crystallized portion. Then, after forming electrodes and the like on the circuit element, the upper surface is covered again with an insulating layer, and this step is repeated for the required number of layers.

The above-mentioned prior art is well known, and for example, “Electronic Materials” published by Industrial Research Society, No. 44, January 1987 issue.
Pages 51 to 51, JP-A-59-175139,
Alternatively, it is disclosed in JP-A-57-113267.

[Problems to be solved by the invention]

However, in the conventional three-dimensional semiconductor integrated circuit manufactured as described above, a polycrystalline silicon film is irradiated with a small spot such as a laser or an electron beam to perform melting and recrystallization to form a circuit element in an upper layer. Since the crystal region is obtained, the following problems occur.

Since melt recrystallization is rapidly performed, the crystallinity is poor and the crystal orientation and the like are not constant. For this reason, there are many variations in the characteristics of the element, making it difficult to design the circuit,
It also causes a decrease in yield.

Since it is not easy to single-crystallize a thick layer, MOS / FET elements are usually formed using the interface of the single-crystal region, and the bulk cannot be fully utilized, making it difficult to form bipolar transistors. Is.

It is not easy to make the entire surface a uniform single crystal region,
Since grain boundaries and the like occur, it is difficult to increase the density of the device.

Since laser or electron beam etc. are sequentially irradiated to a predetermined place to melt and recrystallize, it is impossible to process a large number of wafers at a time, it takes a long time to manufacture, the productivity is deteriorated, and the process is Development becomes complicated and difficult, which is an obstacle to cost reduction.

[Means for solving problems]

In order to solve the above problems, a method for manufacturing a three-dimensional semiconductor integrated circuit according to the present invention includes a lower semiconductor single crystal layer (for example, a silicon layer formed of a p-type (100) wafer) and an upper semiconductor single crystal layer ( For example, a silicon layer made of an n-type (100) wafer) and a lower layer circuit element (for example,
MOS • FET) and upper circuit elements (eg, MOS • F)
ET or bipolar transistor) and a concave portion having a predetermined depth is formed in the upper semiconductor single crystal layer corresponding to a predetermined portion of the wiring electrode forming the lower circuit element, and then the upper layer is formed. A second step of covering the upper surface of the semiconductor single crystal layer and the inner surface of the recess with an insulating film (for example, made of SiO ₂ , SiN, etc.), and smoothing the bottom surface of the upper semiconductor single crystal layer, A third step of opening the bottom of the recess, an upper surface of the lower semiconductor single crystal layer after the first step, and a bottom surface of the upper semiconductor single crystal layer after the third step are provided with an adhesive layer (for example, polyimide). A fourth step of adhering via a film layer), and a through hole reaching a predetermined portion of the wiring electrode is formed by removing an adhesive layer that partitions the opened concave portion and the predetermined portion of the wiring electrode. A step, a sixth electrically connecting the lower circuit element and the upper layer circuit element through the through hole
And a process.

[Action]

A method of manufacturing a three-dimensional semiconductor integrated circuit according to the present invention will be described.

As the semiconductor single crystal layer forming each layer, a silicon wafer having good crystallinity formed by the conventional CZ method or FZ method is used. The formation of the lower-layer circuit element on the lower-layer semiconductor single crystal layer and the formation of the upper-layer circuit element on the upper-layer semiconductor single crystal layer are individually performed for each layer by a method similar to the conventional method.

The concave portion in the second step is formed by using, for example, a photo etching technique, a selective etching technique, or the like so as to correspond to the position where the through hole is formed.

In addition, in the third step, the through hole has an appropriate length in order to electrically connect the lower layer circuit element and the upper layer circuit element at a short distance without damaging the signal or causing a disconnection. This is a process necessary for forming. In the third step, for example, polishing, rappinz, etc. or KO
The length of the through hole can be easily controlled by a method such as etching using H, NaOH, hydrofluoric nitric acid or the like.

Therefore, when forming the concave portion in the second step, it is only necessary to make the depth equal to or larger than the length of the through hole to be formed.

In the fourth to sixth steps, if the lower semiconductor single crystal layer and the upper semiconductor single crystal layer are adhered and the lower circuit element and the upper circuit element are electrically connected through the through hole, two-layer three-dimensional structure is obtained. A semiconductor integrated circuit is formed. Next, this upper semiconductor single crystal layer is used as a lower semiconductor single crystal layer, a new upper semiconductor single crystal layer is further adhered to the upper semiconductor single crystal layer by the same process, and this is repeated to repeat three or more three-dimensional semiconductors. An integrated circuit can be constructed.

As described above, according to the manufacturing method of the present invention, by incorporating the bonding step, it becomes possible to manufacture the semiconductor single crystal layer and the circuit element of each layer in a separate step for each layer.
As a result, the conventional manufacturing process of the two-dimensional semiconductor integrated circuit can be applied as it is, and the circuit elements can be formed at a high density in the uniform single crystal layer having no crystal grain boundary.
The reliability of the three-dimensional semiconductor integrated circuit can be improved. Further, as described above, the through holes can be easily formed, and a large number of bonding steps can be collectively processed. Therefore, the productivity of the three-dimensional semiconductor integrated circuit can be improved.

[Embodiment 1] The following will describe one embodiment of the present invention with reference to FIGS. 1 to 10.

In this embodiment, the first silicon layer 1 made of a p-type (100) wafer is used as the lower semiconductor single crystal layer which is the first layer, the upper layer is for the first layer and the lower layer is for the third layer. N-type (100) as the second semiconductor single crystal layer
A second silicon layer 2 made of a wafer is used, a third silicon layer 3 made of an n-type (100) wafer is used as an upper semiconductor single crystal layer of the third layer, and each semiconductor single crystal layer is bonded. The present invention relates to a three-dimensional semiconductor integrated circuit by MOS • FET using a polyimide film as an adhesive layer.

The manufacturing process of this three-dimensional semiconductor integrated circuit will be described. First, as shown in FIG. 2, n-channel MOS.FETs 4 and 4 are provided at predetermined locations on the upper surface of the first silicon layer 1.
The MOS • FET 4 is formed on the insulating film 5 that covers the upper surface of the first silicon layer 1 and has a window opened at a predetermined position, and on the both ends of the window in the surface layer of the first silicon layer 1 to serve as a source and a drain, respectively. Type diffusion layers 6 and 6 and insulating film 5
A gate oxide film 7 formed to cover the entire window, a gate polycrystalline silicon film 8 formed only on the central upper surface of the gate oxide film 7, and a protective insulating film 9 covering these upper surfaces. A wiring insulating electrode 11 having a predetermined pattern is formed, and a protective insulating film 11 is formed so as to cover the entire upper surface of the wiring electrode 10. The insulating film 5 is a film of SiO ₂ or SiN formed by a thermal oxidation method, a low temperature vapor phase growth method, or the like,
First, after forming the entire upper surface of the first silicon layer 1, a window of a portion where the gate oxide film 7 is formed is opened by a photo etching technique, a selective etching technique, or the like. Then, a thin gate oxide film 7 is formed by thermal oxidation or the like. The gate polycrystalline silicon film 8 is a polycrystalline silicon film formed by a low temperature vapor deposition method or the like, and is formed into a predetermined pattern by a photo etching technique or a selective etching technique. The diffusion layer 6 includes the gate polycrystalline silicon film 8 and the insulating film 5.
Is used as a mask to selectively diffuse n-type impurities into the first silicon layer 1 by using an ion implantation method, a thermal diffusion method, or the like. The protective insulating film 9 is a film of SiO ₂ , SiN or the like formed by a low temperature vapor deposition method or the like. The film for forming the wiring electrode 10 has contact holes formed by photo-etching technique and selective etching technique in the portion of the protective insulating film 9 and the gate oxide film 7 located above the center of each diffusion layer 6 formation position. Every time, a sputtering method, an electron beam evaporation method, or a low pressure CVD (Chemical Vapor) method is performed so as to cover the entire upper surface of the protective insulating film 9 and the contact hole.
Al, Mo, etc. formed by the pour deposition method, etc.
It is a conductive film made of a material such as W, WSi ₂ , MoSi ₂ or TiSi ₂ , and is formed into a predetermined pattern by a photo etching technique or a selective etching technique.
4 becomes a source electrode or a drain electrode or the like. The protective insulating film 11 is made of SiO ₂ formed by a low temperature vapor deposition method or the like.
And the like, and the surface thereof is smoothed by a flattening technique such as an etch-back method so that the subsequent second silicon layer 2 can be reliably bonded.

Next, as shown in FIG. 3, the contact hole 1 is formed at a predetermined position of the protective insulating film 11 corresponding to the position of the through hole later.
3 is formed, the polyimide film layer 12 is coated on the entire upper surfaces of the protective insulating film 11 and the hole 13. The polyimide film layer 12 is used as an adhesive layer, and usually finishes curing at a temperature of about 200 ° C. to 250 ° C., but here it is heated to about 80 ° C. and semi-cured for adhesion later. Leave the state.

Further, as shown in FIG. 4, MOS.FETs 4 and 4 are also provided on the second silicon layer 2 in the same process as the first silicon layer 1. However, since the second silicon layer 2 is an n-type semiconductor, p-type impurities are diffused in the diffusion layer 6 and this MOS.
FETs 4 and 4 are p-channel.

In the second silicon layer 2 on which the MOS • FETs 4 and 4 are formed in this manner, as shown in FIG. 5, a through hole is formed later from the surface protection insulating film 11 to the second silicon layer 2. And a protective insulating film 11 is covered with an insulating film 14. The holes 13 are formed by using a photoetching technique or a selective etching technique and using an etchant such as hydrofluoric nitric acid with the resist film as a mask. However, when the resist film cannot sufficiently withstand the etchant due to the deep holes 13, a metal film such as CrAu or TiAu formed by a vapor deposition method, a sputtering method or the like is formed, and then a photoetching technique or a selective etching technique is used. The metal film at a predetermined hole position is removed by, and the hole 13 is formed using the remaining metal film as a mask and using an alkaline etchant of hydrofluoric nitric acid or KOH or NaOH. The film of CrAu, TiAu, etc. remaining after forming the holes 13 is removed by etching with aqua regia, hot concentrated sulfuric acid or the like. The insulating film 14 is a film of SiO ₂ , SiN or the like formed by a sputtering method, a low temperature vapor phase growth method, an optical CVD method or the like.

Then, as shown in FIG. 6, a protective substrate 15 is attached to the upper surface of the second silicon layer 2 via a wax layer 16, and then smoothed to a thickness of about 0.5 to 200 μm from the lower surface side. Is processed, and a polyimide film layer 12 similar to the first silicon layer 1 is formed on the entire lower surface. The wax layer 16 is made of wax or the like, and is also filled in the holes 13 so that the protective substrate 15 is securely attached. The protective substrate 15 is a temporary support material made of glass, ceramics, or the like. The smoothing is performed by polishing, lapping or the like or etching using KOH, NaOH, hydrofluoric nitric acid or the like until the thickness reaches about 0.5 to 200 μm from the back surface side. In this case, the second silicon layer 2 is
Since (100) wafer is used, KOH, NaO
Preferential etching using H is effective. The polyimide film layer 12 has a thickness of 8 as in the case of the first silicon layer 1.
It is heated to about 0 ° C. and left in a semi-cured state.

As shown in FIG. 7, the first silicon layer 1 and the second silicon layer 2 formed as described above are overlapped at a predetermined position, the temperature is set to about 100 ° C., and an appropriate pressure is applied to bond them. To do. At the time of this adhesion, the wax layer 16 has a softening point of about 120 ° C., so that it will not be deformed even if pressure is applied between the second silicon layer 2 and the protective substrate 15. When the first silicon layer 1 and the second silicon layer 2 are adhered, as shown in FIG. 8, this time, they are heated to about 150 ° C. to melt the wax layer 16 and remove the protective substrate 15. At this time, the wax layer 16 remaining on the second silicon layer 2 is removed with a solvent such as Tricrane. When the wax layer 16 is completely removed, the polyimide film layers 12 and 12 exposed on the bottom surface of the hole 13 are removed to remove the second layer.
The hole 13 on the silicon layer 2 side is replaced with the hole 13 on the first silicon layer 1 side.
To complete the through hole. The removal of the polyimide film layers 12 and 12 is performed by plasma etching or K
It is performed by etching using an etchant such as OH.
Polyimide film layer 12.1 exposed on the bottom surface of the hole 13
When 2 is removed, a predetermined pressure is applied to the first silicon layer 1 and the second silicon layer 2 again in order to completely cure the polyimide film layers 12 remaining in the adhesive layer and ensure the adhesion. Is added under a condition of a predetermined temperature for a predetermined time.

When the first silicon layer 1 and the second silicon layer 2 are securely adhered in this way, as shown in FIG. 9, the insulating film 14 and the holes 13 on the upper surface of the second silicon layer 2 are covered with the first metal film 17.
And the second metal film 18 and covers the second portion other than the hole 13
The upper surface of the metal film 18 is covered with a resist film 19, and the buried metal layer 20 is formed in the hole 13 using the resist film 19 as a mask. The first metal film 17 is a metal film made of Cr, Ti, or the like, and the second metal film 18 is a metal film made of Cu, Ni, or the like, and is continuously formed by a sputtering method or an electron beam evaporation method. To be done. The resist film 19 is patterned by a photoetching technique so as to cover upper surface positions other than the through hole holes 13. Embedded metal layer 2
0 is a metal such as Au embedded in the hole 13 by electrolytic plating. The first metal film 17 is for firmly bonding the embedded metal layer 20 to the through hole 13, and the second metal film 18 is to serve as a plating underlayer for the embedded metal layer 20. Is.

When the embedded metal layer 20 is embedded, the unnecessary resist film 19 and the underlying first metal film 17 and second metal film 18 are removed by hot sulfuric acid or the like, and then, as shown in FIG. In order to connect the hole-buried metal layer 20 and the wiring electrode 10 on the second silicon layer 2, or to connect the wiring electrodes 10 to each other as necessary, a contact hole 21 is opened at a predetermined position of the insulating film 14. Then, the wiring electrode film 22 is formed in a predetermined pattern, and the upper surface thereof is covered with the polyimide film layer 12. The contact hole 21 is formed by removing the insulating film 14 and the protective insulating film 11 at predetermined places by a photo etching technique or a selective etching technique. The wiring electrode film 22 is a single metal layer such as Al, Mo, W or T
iAu, TiCu, CrAu, CrNi, or other multi-metal layer, which covers the entire upper surface of the insulating film 14 by a sputtering method, an electron beam evaporation method, or the like, and is then subjected to a photoetching technique,
A predetermined pattern is formed by a selective etching technique or the like. The polyimide film layer 12 is formed as an adhesive layer for adhering the third silicon layer 3, and is similar to the case where it is formed on the upper surface of the first silicon layer 1 and the lower surface of the second silicon layer 80. It is heated to about ℃ and left in a semi-cured state.

Then, the third silicon layer 3 on which the MOS • FETs 4 and 4 are formed is adhered to the upper layer of the second silicon layer 2 in a separate step, and the upper surface of the third silicon layer 3 is made of polyimide as shown in FIG. After covering with the film layer 12 and opening the contact hole 23, an electrode pad 24 for external attachment is formed. The formation of the MOS • FETs 4 and 4 in the third silicon layer 3 is performed in the same process as in the case of the first silicon layer 1 and the second silicon layer 2, and the holes 13 to be through holes are formed to form the buried metal. The layer 20 is embedded. This third silicon layer 3
Is an n-type semiconductor which is the same as the second silicon layer 2, p-type impurities are diffused in the diffusion layer 6, and
4 is a p channel. The adhesion of the third silicon layer 3 also
The same process as in the case of bonding the second silicon layer 2 is performed. Polyimide film layer 1 on top of third silicon layer 3
Since 2 is formed as a surface protective layer, not as an adhesive layer, it is heated to about 200 ° C. and cured from the beginning.
The contact hole 23 is formed by removing a predetermined portion of the polyimide film layer 12 by a photo etching technique or a selective etching technique. The electrode pad 24 is A
l, Mo, W, Cu single metal film or TiAu, Ti
It consists of multiple metal films such as Cu and CrCu.
After covering the upper surface of the polyimide film layer 12 by an electron beam evaporation method or the like, a predetermined pattern is formed by a photo etching technique or a selective etching technique.

The three-dimensional semiconductor integrated circuit of the present embodiment is manufactured by the above-mentioned process, and the MOS.FETs 4 ... Separately formed on the respective silicon layers 1, 2, and 3 have the holes 13 forming the through holes.
It is connected by a buried metal layer 20 inside.

In this embodiment, the metal layer 20 embedded in the through hole is used.
Although the metal film formed by electrolytic plating is used as the above, it is also possible to use an electroless plated film or a vapor deposition film. Further, although the MOS / IC has been described in this embodiment, C
The same can be applied to the -MOS IC, the bipolar transistor IC, and the like.

[Embodiment 2] The following will describe another embodiment of the present invention with reference to FIGS. 11 to 17.

In this embodiment, the semiconductor single crystal layer to be adhered is made particularly thin to facilitate the connection between the layers and enable parallel processing of signals, thereby increasing the processing speed.

In this embodiment, a first silicon layer 25 made of an n-type (100) wafer is used as a lower semiconductor single crystal layer which is a first layer, an upper layer for the first layer and a lower layer for the third layer. N-type (100) as the second semiconductor single crystal layer
A second silicon layer 26 made of a wafer is used, a third silicon layer 27 made of a p-type (100) wafer is used as an upper semiconductor single crystal layer of a third layer, and the semiconductor single crystal layer is bonded. A polyimide film is used as the adhesive layer, and M is used for the first silicon layer 25 and the second silicon layer 26.
The present invention relates to a three-dimensional semiconductor integrated circuit in which an OS.FET is incorporated and a bipolar transistor is incorporated in the third silicon layer 27.

The manufacturing process of this three-dimensional semiconductor integrated circuit will be described. First, as shown in FIG. 11, p-channel MOS FETs 28 are provided at predetermined locations on the upper surface of the first silicon layer 25. The MOS • FET 28 is formed on an insulating film 29 made of SiO ₂ , SiN or the like, which covers the upper surface of the first silicon layer 25 and has a window opened at a predetermined position, and both ends of the window in the surface layer of the first silicon layer 25. , P-type diffusion layers 30 and 30 serving as a source and a drain, respectively, and an insulating film 29.
Gate oxide film 31 formed so as to cover the entire window of
A gate polycrystalline silicon film 32 formed only on the central upper surface of the gate oxide film 31, a protective insulating film 33 covering these upper surfaces, and Al, M formed in a predetermined pattern.
a wiring electrode 34 made of o, W, MoSi ₂ , TiSi ₂ , WSi ₂ or the like, and a protective insulating film 35 made of SiO ₂ or the like is formed so as to cover the entire upper surface thereof. This MOS • FET 28 is the same as M in the first embodiment.
It is formed in the same process as the OS • FET4. The polyimide film layer 3 is formed on the upper surface of the protective insulating film 35.
6 is coated. This polyimide film layer 36 is also heated to about 80 ° C. and left in a semi-cured state for the subsequent bonding step, as in the case of the first embodiment.

Further, as shown in FIG. 12, MOS.FETs 28, 28 are also formed in the second silicon layer 26, holes 37 and ohmic contact layers 38 which will later become through holes are formed, and then covered with a protective insulating film 33. To do. MOS ・ FET2
8 is formed in the same process as the case of the first silicon layer 25, but here, at the stage where the insulating film 29, the diffusion layers 30 and 30, the gate oxide film 31, and the gate polycrystalline silicon film 32 are formed, Move to the process. Through hole 3
7 is formed by the photo etching technique and the selective etching technique, like the hole 13 of the first embodiment. At this time, the resist film may be used as a mask for etching with an etchant of hydrofluoric nitric acid, or the metal film of CrAu, TiAu or the like may be used as a mask for etching with an etchant of hydrofluoric nitric acid, KOH, NaOH or the like. The ohmic contact layer 38 is made of a metal layer such as Al, Pt, or Pd. First, the gate oxide film 31 on the diffusion layer 30 is removed by a photoetching technique, a selective etching technique, or the like, and then an Al film is thinly deposited on the entire surface. However, the photoetching technique and the selective etching technique leave only the diffusion layer 30 and other A
The film is removed, and finally, it is formed by sintering at a temperature of about 400 to 500 ° C. The protective insulating film 33 is made of SiO ₂ or SiN, and is formed in the same process as the case of the first silicon layer 25.

Next, as shown in FIG. 13, a protective substrate 40 made of glass, a quartz plate, or the like is attached to the upper surface of the second silicon layer 26 via the wax layer 39 in the same process as in the first embodiment. After smoothing the lower surface side of the second silicon layer 26, a polyimide film layer 36 is formed. Second silicon layer 26
The lower surface of the second silicon layer 26 is smoothed to a thickness of 0.5 to 10 μm, but as shown in FIG. 14, a predetermined depth is formed at a position corresponding to the scribe line on the upper surface side of the second silicon layer 26. Groove is formed by etching, and the upper surface is
_{If the} smoothing stop film 41 composed of ₂ etc. is coated in advance, the smoothing stop film 41 can be formed when smoothing from the lower surface.
By stopping the processing when the is exposed, the processing of the predetermined thickness can be performed with high accuracy. The polyimide film layer 36 has the same thickness of 80 as the first silicon layer 25.
It is kept in a semi-cured state by heating at about ℃.

First MOS-FET 28 is formed as described above
The silicon layer 25 and the second silicon layer 26 are adhered to each other at a predetermined position as shown in FIG.
And the removal of the protective substrate 40, the polyimide film layer 36 exposed on the bottom surface of the hole 37 is removed to form a through hole. These are performed in the same steps as in the first embodiment.

When the through hole is formed through the hole 37 in this manner, as shown in FIG. 16, a contact hole is opened on the ohmic contact layer 38, a wiring electrode 42 having a predetermined pattern is formed, and the entire upper surface is formed. The polyimide film layer 3
Coat with 6. The wiring electrode 42 is composed of a single metal film made of Al, Mo, W or the like or a multiple metal film made of TiAu, TiCu, CrCu, etc., and is coated with a metal film on the entire upper surface by a sputtering method, an electron beam evaporation method or the like. , A photoetching technique or a selective etching technique to form a predetermined pattern. This wiring electrode 42 is
The wiring electrode 4 is easily connected to the diffusion layer 30 through the ohmic contact layer 38 formed in advance.
At the time of forming 2, the high temperature treatment such as sintering is unnecessary, and the polyimide film layer 36 having low heat resistance is not adversely affected. The wiring electrode 42 has holes 37.
Although it enters into the through hole and is also connected to the electrode 34 on the first silicon layer 25, since the second silicon layer 26 is thin, there is no fear of disconnection. Like the upper surface of the first silicon layer 25 and the lower surface of the second silicon layer 26, the polyimide film layer 36 is heated to about 80 ° C. and left in a semi-cured state.

Finally, as shown in FIG. 17, the third silicon layer 27 having the separate bipolar transistor 52 is adhered to the upper layer of the second silicon layer 26, and the through hole of the hole 37 is penetrated to form the electrode 42. A three-dimensional semiconductor integrated circuit is completed by. The formation of the bipolar transistor 52 in the third silicon layer 27 is a conventional general method. First, the n ⁺ diffusion layer 43 is formed by selective diffusion of Sb from the upper surface of the third silicon layer 27, and then the upper surface. Then, an n-type single crystal layer 44 is formed by the epitaxial method, and a p-type diffusion layer 45 for separating each island is formed by selective diffusion.
Next, the p-type base layer 46 and the n-type emitter layer 47 are formed by selective diffusion, and the entire upper surface is covered with the insulating film 48. Then, a hole 37 to be a through hole is formed similarly to the case of the second silicon layer 26, and the entire upper surface is covered with an insulating film 49 such as SiO ₂ by a low temperature vapor deposition method, a sputtering method or the like. Finally, after forming contact holes at corresponding positions of the p-type base layer 46, the n-type emitter layer 47 and the collector layer 50 by the photo etching technique and the selective etching technique, the second
Al, Pt, P are formed in the same process as in the case of the silicon layer 26.
The ohmic contact layer 51 is formed by d or the like. When the bipolar transistor 52 is formed in this manner, the lower surface of the third silicon layer 27 is smoothed in the same process as in the case of the second silicon layer 26, and the second silicon layer 26 is formed through the polyimide film layer 36. The electrode 42 is adhered to the upper layer to form the electrode 42 in a predetermined pattern.

The three-dimensional semiconductor integrated circuit of the present embodiment is manufactured by the above process, and the MOS FET 28 and the bipolar transistor 52 which are separately formed in the respective silicon layers 25, 26 and 27 are provided in the hole 37 forming the through hole. It is connected by the electrode 42 formed over.

In this embodiment, the electrode 42 is directly connected to the lower electrode 42 or the electrode 34 through the through hole, but as in the case of the first embodiment, the embedded metal layer is formed by the electrolytic plating film or the electroless plating film. Can also be formed.

In addition, a first embodiment will explain a three-dimensional semiconductor integrated circuit using a MOS.FET, and a second embodiment will explain a MOS.FE.
Although the three-dimensional semiconductor integrated circuit using the T and bipolar transistors has been described, including the C-MOS IC,
The type and combination of elements to be formed can be freely selected.

Furthermore, in Examples 1 and 2, the n-type or p-type (1
00) A wafer was used, but the semiconductor mold and crystal plane are not limited to this.

Further, in the first and second embodiments, the polyimide film is used as the adhesive layer of each silicon layer, but the adhesive layer is not limited to this, and an epoxy resin, an acrylic resin, or another adhesive layer can be used.

Further, in the first and second embodiments, the holes 13 and 37 to be the through holes are formed before the bonding of the respective silicon layers, but they may be formed after the bonding.

Although the three-dimensional three-dimensional semiconductor integrated circuit is shown in the first and second embodiments, the three-dimensional semiconductor integrated circuit having only two layers or repeating the same steps may be a three-dimensional semiconductor integrated circuit having four or more layers. .

In addition, in each of the first and second embodiments, each layer is formed of only a silicon layer, but a three-dimensional semiconductor integrated circuit is formed by combining it with a mixed crystal semiconductor such as GaAs or InP, or only a mixed crystal semiconductor is used. It is also possible to configure a three-dimensional semiconductor integrated circuit.

〔The invention's effect〕

As described above, the method for manufacturing a three-dimensional semiconductor integrated circuit according to the present invention includes the first step of individually forming the lower circuit element and the upper circuit element in the lower semiconductor single crystal layer and the upper semiconductor single crystal layer, respectively. And after forming a recess of a predetermined depth in the upper semiconductor single crystal layer corresponding to a predetermined portion of the wiring electrode constituting the lower circuit element, along the upper surface of the upper semiconductor single crystal layer and the inner surface of the recess. A second step of covering with an insulating film, a third step of smoothing the bottom surface of the upper semiconductor single crystal layer to open the bottom of the recess, and a lower semiconductor single crystal layer after the first step A fourth step of adhering the upper surface and the bottom surface of the upper semiconductor single crystal layer that has been subjected to the third step with an adhesive layer, and an adhesive layer for partitioning between the opened concave portion and a predetermined portion of the wiring electrode are provided. By removing, A fifth step of forming a through-hole reaching the site, a configuration and a sixth step of electrically connecting the lower circuit element and the upper layer circuit element via the through hole.

Thereby, the present invention can crystallize the semiconductor single crystal layer of each layer and the formation of the circuit element in separate steps,
The following effects are produced.

Since a semiconductor single crystal layer of each layer having good crystallinity such as a silicon wafer can be used, variations in characteristics of the formed circuit elements are reduced, circuit design is facilitated, and yield is improved. Further, since a single crystal having a sufficient thickness can be obtained, it is easy to form a bipolar transistor using a bulk. Furthermore, since each layer can be formed of a uniform single crystal, there are no crystal grain boundaries and the like, and circuit elements can be formed with high density.

Moreover, since the circuit elements of each layer are formed separately for each layer, the process of the conventional two-dimensional semiconductor integrated circuit can be used as it is, and product development and manufacturing are facilitated. Furthermore, each layer can be processed in parallel by a separate process by a conventional method, instead of stacking while melting and recrystallizing each layer in sequence, and a large number of bonding processes can be performed at once. Therefore, the productivity is improved, and the product can be manufactured in a short period of time.

Further, in order to electrically connect the lower layer circuit element and the upper layer circuit element over a short distance without fear of signal attenuation or wire breakage, a recess having a length equal to or longer than a desired design is formed in the second step. Then, the through hole can be easily and surely controlled to have an appropriate length by the third step. Further, although the bottom of the opened recess is once closed by the adhesive layer in the fourth step, various effects that the through hole can be easily completed only by removing the unnecessary adhesive layer are also exhibited. .

[Brief description of drawings]

1 to 10 show an embodiment of the present invention. FIG. 1 is a partial cross-sectional front view of a three-dimensional semiconductor integrated circuit, and FIGS. 2 to 10 are three-dimensional semiconductor integrated circuits, respectively. 11 to 17 are vertical sectional partial front views showing a circuit manufacturing process, showing another embodiment of the present invention.
FIGS. 16 to 16 are vertical sectional partial front views showing the manufacturing process of the three-dimensional semiconductor integrated circuit, and FIG. 17 is a vertical sectional partial front view of the three-dimensional semiconductor integrated circuit. 1.25 is the first silicon layer (lower semiconductor single crystal layer), 2
26 is a second silicon layer (upper semiconductor single crystal layer and lower semiconductor single crystal layer), 3.27 is a third silicon layer (upper semiconductor single crystal layer), 4.28 is a MOS-FET (circuit element), 10 34 and 42 are wiring electrodes, 12 and 36 are polyimide film layers (adhesive layers), 13 and 37 are holes (through holes), 14 and 33 and 49 are insulating films, and 52 is a bipolar transistor (circuit element).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 25/07 25/18

Claims (1)

[Claims] 1. A first step of separately forming a lower layer circuit element and an upper layer circuit element in a lower semiconductor single crystal layer and an upper semiconductor single crystal layer, respectively, and a predetermined portion of a wiring electrode constituting the lower layer circuit element. Corresponding to, a second step of forming a recess of a predetermined depth in the upper semiconductor single crystal layer, and then covering with an insulating film along the upper surface of the upper semiconductor single crystal layer and the inner surface of the recess, and the upper semiconductor single crystal A third step of smoothing the bottom surface of the layer to open the bottom of the recess, an upper surface of the lower semiconductor single crystal layer after the first step, and an upper semiconductor single crystal layer after the third step. A fourth step of adhering the bottom surface of the wiring electrode via an adhesive layer, and removing the adhesive layer separating the opened concave portion and the predetermined portion of the wiring electrode to reach the predetermined portion of the wiring electrode. The fifth step of forming holes And a sixth step of electrically connecting the lower layer circuit element and the upper layer circuit element through the through hole, the method for manufacturing a three-dimensional semiconductor integrated circuit.