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JPS5854499B2 - Manufacturing method of semiconductor device - Google Patents
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JPS5854499B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5854499B2
JPS5854499B2 JP54033114A JP3311479A JPS5854499B2 JP S5854499 B2 JPS5854499 B2 JP S5854499B2 JP 54033114 A JP54033114 A JP 54033114A JP 3311479 A JP3311479 A JP 3311479A JP S5854499 B2 JPS5854499 B2 JP S5854499B2
Authority
JP
Japan
Prior art keywords
lead
insulating film
leads
manufacturing
supporting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54033114A
Other languages
Japanese (ja)
Other versions
JPS55125637A (en
Inventor
春夫 小嶋
隆 原口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54033114A priority Critical patent/JPS5854499B2/en
Publication of JPS55125637A publication Critical patent/JPS55125637A/en
Publication of JPS5854499B2 publication Critical patent/JPS5854499B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/701Tape-automated bond [TAB] connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/077Connecting of TAB connectors

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置の製造方法に関し、更に特定するな
らば、絶縁フィルム配線体を用いる半導体素子の実装方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of mounting a semiconductor element using an insulating film wiring body.

(b) 従来技術と問題点 より高密度実装が要求される半導体集積回路(IC)素
子の組立工程にあっては、その実装手段の一つとして優
れた耐熱性を持つポリイ□ド・フィルム表面にリード線
あるいは配線体が形成されたいわゆるフイルムキリアが
開発された結果、急速に自動化されたばかりマなく、高
密度の実装が可能となり、特殊な実装や高度の集積化が
可能となってきた。
(b) Due to conventional technology and problems, in the assembly process of semiconductor integrated circuit (IC) elements, which requires high-density mounting, polyide film surface with excellent heat resistance is used as one of the mounting means. As a result of the development of the so-called film carrier, in which lead wires or wiring bodies are formed, not only has it been rapidly automated, but it has also become possible to perform high-density packaging, special packaging, and a high degree of integration.

その一つの例として次に述べるTAB(TapeAut
omated Bonding )方式がある。
One example is the TAB (TapeOut) described below.
There is an omated bonding method.

つ1り第1図aに示すように、片面の中央帯の幅W程に
接着剤2を塗った3、5frrm程の幅を有するテープ
状ポリイミド・フィルム1を準備し、次いで同図すに示
すように両側帯に位置合せ孔3をプレス等であける。
As shown in Figure 1a, a tape-shaped polyimide film 1 having a width of about 3.5 frrm is prepared by applying adhesive 2 to the width W of the central band on one side, and then As shown, alignment holes 3 are made in both side bands using a press or the like.

この後の工程はすべてこの孔をガイドにしてリールに巻
き取りながら行われる。
All subsequent steps are performed while winding onto a reel using these holes as a guide.

次に同図Cのようにポリイミド・フィルム1の中央帯に
搭載すべき半導体素子を収容する長方形(正方形も含む
)の素子収容孔4をプレスで打ち抜く。
Next, as shown in Figure C, a rectangular (including square) element housing hole 4 for accommodating a semiconductor element to be mounted in the center band of the polyimide film 1 is punched out using a press.

次いで同図dに示すように該ポリイミド・フィルム10
表面に厚さ35μm程の銅(Cu)箔等の金属箔5を前
記接着剤2によって接着し、更に該金属箔5を所定の形
状にフォトエツチングする。
Then, as shown in FIG. d, the polyimide film 10
A metal foil 5 such as a copper (Cu) foil having a thickness of about 35 μm is adhered to the surface using the adhesive 2, and the metal foil 5 is further photo-etched into a predetermined shape.

そしてパターニングされた金属箔5上に錫(S n)の
無電界メッキを施して同図eに示すようにリード6を形
成する。
Then, electroless plating of tin (Sn) is applied to the patterned metal foil 5 to form leads 6 as shown in FIG.

半導体素子と該絶縁フィルム配線体のり−ド6との接続
は同図fに示すように、リード6の素子収容孔4に突出
した先端部自由端と、半導体素子7の電極部に形成され
た例えば金(Au)バンプ8との位置を合せておき、ボ
ンディング・ツールをリード6の先端におろして圧力を
かけ、加熱することにより、リード5のSnと半導体素
子の金パンプとが合金となり、接続一体化される。
As shown in FIG. For example, by aligning the position with a gold (Au) bump 8, lowering a bonding tool to the tip of the lead 6, applying pressure, and heating, the Sn of the lead 5 and the gold bump of the semiconductor element become an alloy. Connection is integrated.

このあと図示の一点鎖線で示される箇所即ち素子収容孔
4の内側にむいてリード6を切断してこれと同時にある
いは半導体素子7を該リード6と共に取り出して後同図
gに示すようにリード6を二段に折曲げ、セラミック基
板等の絶縁回路基板9等の、予め半田等の鑞材をつけた
配線パターン10に、前記リード6の外側端部の位置を
合せてボンディング・ツールにより抑圧加熱して、リー
ド6を配線パターン10に接続する。
Thereafter, the leads 6 are cut at the point indicated by the dashed line in the figure, that is, toward the inside of the element housing hole 4, and at the same time, or after the semiconductor element 7 is taken out together with the leads 6, the leads 6 are cut as shown in FIG. The outer end of the lead 6 is bent in two steps, and the outer end of the lead 6 is aligned with the wiring pattern 10 of an insulated circuit board 9 such as a ceramic board, on which a brazing material such as solder is applied in advance, and heated under pressure using a bonding tool. Then, the lead 6 is connected to the wiring pattern 10.

上述の工程中、リード6の内側先端部を半導体素子7の
バンプ8に接続する際や、リード6を切断し折り曲げる
際、あるいは切断後の取り扱い等によりリード6が変形
することがある。
During the above steps, the leads 6 may be deformed when connecting the inner tips of the leads 6 to the bumps 8 of the semiconductor element 7, when cutting and bending the leads 6, or due to handling after cutting.

リード6が変形すると、ソー160間隔は非常に狭いた
め隣接するリードが接触したり、前記セラミック基板9
上の配線パターン10に接続する際にリード6が隣接す
る配線パターン10に接触してし15などの問題がある
When the leads 6 are deformed, since the spacing between the saws 160 is very narrow, adjacent leads may come into contact with each other, or the ceramic substrate 9 may
When connecting to the upper wiring pattern 10, there are problems such as the lead 6 coming into contact with the adjacent wiring pattern 10 (15).

(C) 発明の目的 本発明の目的はかかる問題点を除去して、リードの変形
やピッチの狂い等を生じることなく、絶縁フィルム配線
体を容易に切断し得る半導体装置の製造方法を提供する
ことにある。
(C) Purpose of the Invention The purpose of the present invention is to provide a method for manufacturing a semiconductor device that eliminates such problems and allows easy cutting of an insulating film wiring body without causing lead deformation or pitch deviation. There is a particular thing.

(Φ 発明の構成 本発明の特徴は、絶縁フィルムと、該絶縁フィルムに開
口された素子収容孔と、該絶縁フィルム上に固着され前
記素子収容孔内に先端を突出させて配設された複数体の
リードとを有する絶縁フィルム配線体の、前記素子収容
孔内に半導体素子を載置し、該半導体素子表面に設けら
れた電極と前記素子収容孔内に突出せる前記リードの先
端とを接続し、次いで前記リードの他端を、該リードを
固定せる前記絶縁フィルムの支持部とともに切断し、次
いで前記リードを所定の支持基板上に形成された配線パ
ターンに接続する一連の工程に杭いて、前記素子収容孔
を、四隅に切り欠き部を有し前記リードを固定せる絶縁
フィルムの支持部が素子収容孔内に突出せる形状として
むき、該支持部を横断して切断することにある。
(Φ Structure of the Invention The present invention is characterized by an insulating film, an element accommodating hole opened in the insulating film, and a plurality of elements fixed on the insulating film with their tips protruding into the element accommodating hole. A semiconductor element is placed in the element accommodating hole of an insulating film wiring body having body leads, and an electrode provided on the surface of the semiconductor element is connected to a tip of the lead that can protrude into the element accommodating hole. Then, the other end of the lead is cut together with the supporting part of the insulating film to which the lead is fixed, and then the lead is connected to a wiring pattern formed on a predetermined support substrate. The device accommodating hole is peeled so that the supporting portion of the insulating film that has notches at the four corners so that the support portion of the insulating film for fixing the lead can protrude into the device accommodating hole, and the supporting portion is cut across the device accommodating hole.

(e) 発明の実施例 以下本発明の一実施例を図面により説明する。(e) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明の一実施例を示す図であって、同図a及
びbは第1図a及びbと全く同一で、ここ1では従来の
製造方法と変る点はない。
FIG. 2 is a diagram showing an embodiment of the present invention, and FIGS. 2A and 2B are completely the same as FIGS.

即ち第2図aに示すように、寸ず例えば3,5問程の幅
を有し、片面の中央帯にWなる幅に接着剤2を塗ったポ
リイミド・フィルム1を準備し、同図すに示すように該
ポリイミド・フィルム10両側帯の接着剤非塗布部に位
置合せ孔3をプレス等であける。
That is, as shown in Fig. 2a, prepare a polyimide film 1 having a width of, for example, 3 or 5 pieces and coated with adhesive 2 in a width W on the central band of one side. As shown in FIG. 2, alignment holes 3 are made using a press or the like in the adhesive-free areas of both side bands of the polyimide film 10.

この後の工程はすべてこの孔をガイドにしてリールに巻
き取りながら行われる。
All subsequent steps are performed while winding onto a reel using these holes as a guide.

次に同図Cのようにテープの中央帯に素子を収容するた
めの素子収容孔14をプレス等で打ち抜く。
Next, as shown in Figure C, an element housing hole 14 for accommodating an element is punched out in the central band of the tape using a press or the like.

但し該素子収容孔14の形状は、前記従来の製造方法で
は長方形であったのに対し本実施例では長方形のMに切
り欠き部11を設けた形状としてふ・く。
However, the shape of the element housing hole 14 is rectangular in the conventional manufacturing method, whereas in this embodiment, the shape is a rectangle M with a notch 11 provided therein.

次いで同図dに示すように該ポリイミド・フィルム1表
面に厚さ35μm程度の銅(Q])箔5を前記接着剤に
よって接着し、更に該銅箔5を所定の形状にフォトエツ
チングする。
Next, as shown in FIG. 4D, a copper (Q) foil 5 having a thickness of about 35 μm is adhered to the surface of the polyimide film 1 using the adhesive, and the copper foil 5 is photo-etched into a predetermined shape.

そしてパターニングされた銅箔5上に錫(Sn)の無電
界メッキを施して、同図eに示すようにリード6を形成
する。
Then, electroless plating of tin (Sn) is applied to the patterned copper foil 5 to form leads 6 as shown in FIG.

以上により本実施例においては、リード6の支持部15
が素子収容孔14内側に突出して形成される。
As described above, in this embodiment, the support portion 15 of the lead 6 is
is formed to protrude inside the element housing hole 14.

次いで同図fに示すように半導体素子7の電極部に形成
された例えば金(Au)からなりバンプと、前記リード
6の素子収容孔4に突出した先端部との位置を合せてむ
き、図示されないボンディングツールをリード6の先端
に釦ろして圧力をかけ加熱すれば、SnとAuとが合金
となり、接続一体化される。
Next, as shown in FIG. By pressing a bonding tool that is not attached to the tip of the lead 6 and applying pressure and heating, Sn and Au become an alloy and are connected and integrated.

次いで同図gに示す一点鎖線の部分、即ち素子収容孔の
各辺の外側で且つ四隅の切り欠き部11の最外端よりは
内側でリード6を絶縁フィルムと共に切断する。
Next, the lead 6 is cut together with the insulating film at the portion indicated by the dashed-dotted line shown in FIG.

なお同図gはgのx−x断面であり、8はバンプである
Note that g in the figure is a cross section taken along line xx of g, and 8 is a bump.

その結果、同図りに示すようにリード6の外側端部は絶
縁フィルムの棧12によりピッチを正確に保持した状態
に固定されて、絶縁フィルムのテープから分離される。
As a result, as shown in the figure, the outer ends of the leads 6 are fixed by the insulating film legs 12 in a state in which the pitch is maintained accurately, and are separated from the insulating film tape.

次にU図iに示すようにリード6を例えば二段に折り曲
げ、更にリード6の外側端部即ち前記絶縁フィルムの棧
12が付着している部分を必要に応じて上方に折り曲げ
る。
Next, as shown in Figure U, the lead 6 is bent, for example, into two stages, and the outer end of the lead 6, that is, the part to which the insulating film ridge 12 is attached, is further bent upward as required.

このリードを折り曲げる工程は、リード切断後にプレス
等を用いて行なってもよく、またリード切断時に行なっ
てもよい。
This step of bending the leads may be performed using a press or the like after cutting the leads, or may be performed at the time of cutting the leads.

しかる後同図jに示すようにリード6の絶縁フィルムの
棧12の付着している部分の内側をセラ□ツク基板9等
の予め半田をつけた配線パターン10に位置を合せ、図
示されないボンディングツールで押圧加熱することによ
り、リード6を配線パターン10に接続する。
Thereafter, as shown in FIG. J, the inside of the part of the insulating film of the lead 6 to which the beam 12 is attached is aligned with the pre-soldered wiring pattern 10 of the ceramic board 9, etc., and then soldered using a bonding tool (not shown). The leads 6 are connected to the wiring pattern 10 by pressing and heating.

この間前記リード6は絶縁フィルムの棧12に固着され
ているのでピッチが狂うことはなく、従って配線パター
ンとの位置合せは容易であり、位置ずれを生じることも
ない。
During this time, since the leads 6 are fixed to the insulating film sills 12, the pitch will not be distorted, and therefore alignment with the wiring pattern is easy and no misalignment will occur.

また、折り曲げ時や取り扱い等によりリードが変形する
こともない。
Further, the leads are not deformed during bending or handling.

前記絶縁フィルムの棧12は通常最後に取り除くが、搭
載空間に余裕がなるなら、これは絶縁物であり半導体装
置の電気的特性上無害であるので残しておいても差支え
ない。
The insulating film ledge 12 is usually removed last, but if there is sufficient mounting space, it may be left as it is an insulator and harmless in terms of the electrical characteristics of the semiconductor device.

以上説明したごとく本発明によれば、半導体装置の組立
工程全体にわたって半導体素子から導出されたり−ド6
変形させることがないので、該リード6をパッケージま
たは回路基板上の配線パターンや電極に接続する際に位
置すれかなく、位置合せが容易となり、従って作業能率
が向上するばかりでなく、製造歩留りも改善され、組立
ての自動化もより一層容易となる。
As explained above, according to the present invention, the semiconductor device is
Since the lead 6 is not deformed, it is easy to position the lead 6 when connecting it to the wiring pattern or electrode on the package or circuit board, and alignment is facilitated, which not only improves work efficiency but also reduces manufacturing yield. As a result, assembly automation becomes even easier.

第3図上記−実施例の効果の理解を容易にするために掲
げた図で、従来の製造方法による製造工程を示す。
FIG. 3 is a diagram provided to facilitate understanding of the effects of the above-described embodiment, and shows manufacturing steps by a conventional manufacturing method.

即ち従来の絶縁フィルム配線体は同図に示すように、素
子収容孔4の四隅に切り欠き部を設けていなかった。
That is, the conventional insulating film wiring body does not have cutouts at the four corners of the element housing hole 4, as shown in the figure.

そのため前記第2図りに示す構成を得るには、絶縁フィ
ルム1を図の破線で示すように切断せねばならず、その
ためカッタの形状が複雑となる。
Therefore, in order to obtain the configuration shown in the second diagram, the insulating film 1 must be cut as shown by the broken line in the diagram, which makes the shape of the cutter complicated.

かかる形状の複雑なカッタの作成及び調整は必ずしも容
易ではない。
It is not always easy to create and adjust a cutter with such a complicated shape.

これに対し前記本発明の一実施例においては、リード6
の支持部15を素子収容孔14内に突出させたことによ
り、この部分を横断するように切断すれば良く、従つ−
C直線状のカッタを用いることができ、カッタの製作及
びその調整は至って簡単である。
On the other hand, in the embodiment of the present invention, the lead 6
By making the support part 15 protrude into the element housing hole 14, it is only necessary to cut it across this part.
C A linear cutter can be used, and manufacturing and adjustment of the cutter are extremely simple.

なお前記一実施例ではり−ド6としてCuにSn メッ
キをしてものを用いて説明したが、リード6の材質はこ
れに限定されるものではなく、半導体素子の電極の材質
・形状や、パッケージあるいは回路基板の配線パターン
、電極の材質等との関連に釦いて適宜選択してよい。
In the above embodiment, the leads 6 are made of Cu plated with Sn, but the material of the leads 6 is not limited to this, and may vary depending on the material and shape of the electrodes of the semiconductor element, The selection may be made as appropriate depending on the wiring pattern of the package or circuit board, the material of the electrodes, etc.

オた前記一実施例ではり−ド6を折り曲げてボンディン
グしたが、フェース・ダウン・ボンディングのような場
合には リード6を折り曲げる必要のないことは言う1
でもない。
In the above embodiment, the lead 6 was bent for bonding, but it is not necessary to bend the lead 6 in cases such as face-down bonding.
not.

(f) 発明の詳細 な説明した如く本発明によれば、半導体装置の製造作業
が正確且つ容易となり、作業能率及び製造歩留りが向上
するばかりでなく、組立工程の自動化がより一層容易と
なる。
(f) Detailed Description of the Invention According to the present invention, the manufacturing operation of semiconductor devices becomes accurate and easy, and not only the work efficiency and manufacturing yield are improved, but also the automation of the assembly process becomes even easier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の製造方法を示す工程断面図
、第2図は本発明の製造方法の一実施例を示す工程断面
図、第3図は参考のために掲げた従来の製造方法を示す
平面図である。 図に釦いて、1は絶縁フィルム、2は接着剤、3は位置
合せ孔、4,14は素子収容孔、5は金属箔、6はリー
ド、Tは半導体素子、8は電極、9はパッケージまたは
回路基板、10は配線パターン、11は切り欠き部、1
2は絶縁フィルムの棧、15は支持部を示す。
FIG. 1 is a process sectional view showing a conventional method for manufacturing a semiconductor device, FIG. 2 is a process sectional view showing an embodiment of the manufacturing method of the present invention, and FIG. 3 is a conventional manufacturing method shown for reference. FIG. In the figure, 1 is an insulating film, 2 is an adhesive, 3 is an alignment hole, 4 and 14 are element housing holes, 5 is a metal foil, 6 is a lead, T is a semiconductor element, 8 is an electrode, and 9 is a package or a circuit board, 10 is a wiring pattern, 11 is a notch, 1
Reference numeral 2 indicates a leg of the insulating film, and reference numeral 15 indicates a support portion.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁フィルムと、該絶縁フィルムに開口された素子
収容孔と、該絶縁フィルム上に固着され前記素子収容孔
内に先端を突出させて配設された複数本のリードとを有
する絶縁フィルム配線体の、前記素子収容孔内に半導体
素子を載置し、該半導体素子表面に設けられた電極と前
記素子収容孔内に突出せる前記リードの先端とを接続し
、次いで前記リードの他端を、該リードを固定せる前記
絶縁フィルムの支持部とともに切断し、次いで前記リー
ドを所定の支持基板上に形成された配線パターンに接続
する一連の工程にかいて、前記素子収容孔を、四隅に切
り欠き部を有し前記リードを固定せる絶縁フィルムの支
持部が素子収容孔内に突出せる形状としておき、該支持
部を横断して切断することを特徴とする半導体装置の製
造方法。
1. An insulating film wiring body having an insulating film, an element accommodation hole opened in the insulating film, and a plurality of leads fixed on the insulating film and disposed with their tips protruding into the element accommodation hole. A semiconductor element is placed in the element housing hole, an electrode provided on the surface of the semiconductor element is connected to a tip of the lead that can protrude into the element housing hole, and then the other end of the lead is connected to Through a series of steps of cutting the insulating film together with the supporting portion to which the lead is fixed, and then connecting the lead to a wiring pattern formed on a predetermined support substrate, the element receiving hole is cut out at the four corners. 1. A method of manufacturing a semiconductor device, characterized in that a supporting portion of an insulating film having a portion and fixing the lead is shaped so as to protrude into an element housing hole, and the supporting portion is cut across the supporting portion.
JP54033114A 1979-03-20 1979-03-20 Manufacturing method of semiconductor device Expired JPS5854499B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54033114A JPS5854499B2 (en) 1979-03-20 1979-03-20 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54033114A JPS5854499B2 (en) 1979-03-20 1979-03-20 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS55125637A JPS55125637A (en) 1980-09-27
JPS5854499B2 true JPS5854499B2 (en) 1983-12-05

Family

ID=12377611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54033114A Expired JPS5854499B2 (en) 1979-03-20 1979-03-20 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5854499B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5874352U (en) * 1981-11-13 1983-05-19 リコーエレメックス株式会社 circuit board
JPS59175132A (en) * 1983-03-23 1984-10-03 Nec Corp Manufacture of semiconductor device according to tape carrier system
JPH0773154B2 (en) * 1986-04-10 1995-08-02 松下電器産業株式会社 Lead connection method
US4903113A (en) * 1988-01-15 1990-02-20 International Business Machines Corporation Enhanced tab package

Also Published As

Publication number Publication date
JPS55125637A (en) 1980-09-27

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