JPS585549B2 - Fault repeater search method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault repeater search method that facilitates troubleshooting of repeaters in a PCM transmission system.

In the PCM transmission system, repeaters are provided at predetermined distances along the transmission path, and each repeater performs regenerative amplification of the PCM signal.

If a failure occurs in one of these repeaters, reception will be interrupted, the reception level will drop abnormally, or errors will occur at the receiving end station. The search begins.

The search for a faulty repeater is generally performed by sequentially turning back the repeaters or placing them in a bypass state.

However, if a fault occurs in a repeater close to a terminal station, it is possible to search for the faulty repeater relatively quickly, but as the distance from the terminal station increases, the time required for the search increases, and the search control is complicated. There was a drawback.

In addition, a control line is provided between each repeater and the terminal station, and each repeater is provided with a fault detection means, so that when a fault is detected, a signal specific to the repeater is sent to the terminal station via the control line. Proposed.

However, a control line must be provided, resulting in an uneconomical configuration for long-distance transmission.

Fig. 1 is a block diagram of the main parts of the previously proposed faulty repeater search method, where IN is the input terminal of the repeater, EQ is the equalization amplifier, AGC is the automatic gain control circuit, and DET is the automatic gain. A detection circuit that detects an abnormality in the control voltage, TM is a timing extraction circuit, OFD is an input disconnection detection circuit that determines that the input is disconnected when the timing signal is not extracted normally, and PLO runs by itself when the input is disconnected, indicating that it is normal. time is a phase synchronized oscillator that is phase synchronized with the extracted timing signal, REG is a reproduction sending circuit, OUT is an output terminal of a repeater, SVS is a fault information sending circuit, DV1 is a frequency divider, G1 is an inhibit gate circuit, and G2 is a The OR gate circuit and G3 are an AND gate circuit.

During normal operation, the PCM signal applied to the input terminal IN is equalized and amplified by the equalization amplifier EQ, and then sent to the inhibit gate circuit G.
1 and the reproduction sending circuit REG via the OR gate circuit G2.
and a phase synchronized oscillator PLO which is phase synchronized with the timing signal extracted by the timing extraction circuit TM.
The output clock signal is applied to the reproduction sending circuit REG, and in synchronization with this clock signal, it is sent from the output terminal OUT to the next stage repeater or terminal station.

In this case, from the automatic gain control circuit AGC to the equalization amplifier EQ
Since the automatic gain control voltage applied to is within a predetermined range, the output signal of the detection circuit DET becomes "0", the inhibit gate circuit G1 is opened, and the AND gate circuit G
3 is in a closed state.

When a failure occurs, for example, if the level of the PCM signal applied to the input terminal IN becomes abnormally low or disconnected due to a failure in the previous stage repeater or transmission line, the automatic gain control voltage will show an abnormal value and the timing signal extraction will not occur normally. It will not be done.

The abnormal value of this automatic gain control voltage is detected by the detection circuit DET and the output signal is set to "1", and the inhibit gate circuit G
1 and open the AND gate circuit G3.

Further, due to the abnormal output of the timing extraction circuit TM, the input disconnection detection circuit OFD disconnects the timing signal applied to the phase synchronized oscillator PLO.

This causes the phase synchronized oscillator PLO to free-run oscillate.

This free-running oscillation frequency is set to correspond to the transmission speed of the PCM transmission line.

The clock signal output from the phase-locked oscillator PLO in a free-running oscillation state is frequency-divided by 1/N by a frequency divider DV1.

This N is selected as a value unique to the repeater, and the output of the AND gate circuit G3 becomes a clock signal when the frequency division signal is "1".

Therefore, as shown in FIG. 2, if the clock signal is a, the dividing signal is b, and the output signal of the detection circuit DET is C, the output signal of the AND gate circuit G3 has a period T as shown in d.
The all mark signal and all space signal are repeated in
and is sent from the output terminal OUT to the next stage repeater or terminal station in synchronization with the clock signal.

Since this fault information has a period T unique to the repeater, the terminal station can immediately identify the faulty repeater.

However, since a frequency divider with a different frequency division ratio must be installed for each repeater, it becomes difficult to implement this method when a large number of repeaters are installed.

An object of the present invention is to make it easy to identify a faulty repeater even when a large number of repeaters are installed.

Examples will be described in detail below.

FIG. 3 is a block diagram of the main parts of the embodiment of the present invention,
The same symbols as in FIG. 1 indicate the same parts, and DV2 is a frequency divider;
MEM is a memory such as read-only memory (ROM) that stores fault information including repeater address information, G4, G
5 is an AND gate circuit.

During normal operation, it is the same as in the previous embodiment, and when the automatic gain control voltage shows an abnormal value and the detection circuit DET detects the occurrence of a fault, the phase-locked oscillator PLO starts free-running oscillation in the same way as the operation explained with reference to FIG. The output clock signal is frequency-divided by 1/M by a frequency divider DV2, and the frequency-divided signal is applied to the memory MEM via an AND gate circuit G4, and fault information is read from the memory MEM and Gate circuit G
5. It is applied to the reproducing and transmitting circuit REG via the OR gate circuit G2, and is transmitted in synchronization with the clock signal.

The failure information read from the memory MEM consists of failure occurrence notification information A of the all mark signal and repeater address information B, as shown in FIG. 4A, for example, and is repeatedly read out at a period T.

This fault information will be sent out from the reproduction sending circuit REG in synchronization with the clock signal shown in FIG. 4b.

Note that the frequency divider DV2 has a frequency dividing ratio selected in accordance with the read speed of the memory MEM, and has the advantage that a memory having a lower speed than the transmission speed of the PCM transmission line can be used.

At the terminal station, the occurrence of a failure can be identified using the failure occurrence notification information A, and the failed repeater can be immediately identified using the repeater address information B.

As explained above, the present invention provides a phase-locked oscillator PLO
A frequency divider DV2 that divides the output from a clock oscillation source such as
, a fault detection circuit DET, and a memory MEM that stores fault occurrence notification information and repeater address information. When the fault detection circuit detects the occurrence of a fault, it accesses the memory MEM according to the frequency divider output and detects the fault occurrence. The notification information and the repeater address are repeatedly read out, and the read information is sent to the terminal station as fault information in synchronization with the output from the clock oscillation source.The frequency division ratio of the frequency divider DV2 is set for each repeater. They can be the same, and the terminal station can immediately identify the faulty repeater using fault information consisting of fault occurrence notification information and repeater address information.

Furthermore, even if a large number of repeaters are installed, they can be easily identified by the repeater address information, and the repeater address information assigned to each repeater can be changed or added at will by rewriting the memory MEM. Because of this, there is an advantage that it is possible to easily deal with expansions and changes in the PCM transmission system.

Furthermore, when a fault occurs, the information can be read out and sent repeatedly, which has the advantage of making it easier to identify the faulty repeater at the terminal station.

Furthermore, since the fault information is transmitted through the PCM transmission line, there is no need to provide a control line, and the search for a faulty repeater can be performed economically.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main part of the faulty repeater search method proposed earlier, FIGS. 2a to d are diagrams explaining the fault information sending operation of FIG. Block diagram, 4th
Figures a and b are explanatory diagrams of the failure information sending operation in Figure 3. EQ is equalization amplifier, AGC is automatic gain control circuit, DET
TM is a detection circuit, TM is a timing extraction circuit, OFD is an input disconnection detection circuit, PLO is a phase synchronized oscillator, REG is a reproduction sending circuit, SVS is a fault information sending circuit, DVI and DV2 are frequency dividers, and MEM is a memory.

Claims (1)

[Claims] 1 In a method for searching for a faulty repeater in a PCM transmission system, a frequency divider that divides the output from a clock oscillation source, a fault detection circuit, fault occurrence notification information, and repeater address information are stored. A fault detection signal from the fault detection circuit accesses the memory according to the frequency divider output, repeatedly reads the fault occurrence notification information and repeater address information, and reads out the fault occurrence notification information and repeater address information from the clock oscillation source. A faulty repeater search method characterized in that the faulty repeater is sent to a terminal station as faulty information in synchronization with the output of the faulty repeater, and the faulty repeater is identified at the terminal station based on the faulty information.