JPS585548B2 - Fault repeater search method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault repeater search method that facilitates troubleshooting of repeaters in a PCM transmission system.

In the PCM transmission system, repeaters are provided at predetermined distances along the transmission path, and regenerative amplification of the fflM signal is performed in each repeater.

If a fault occurs in one of these repeaters, reception will be interrupted or an abnormal error will occur at the receiving terminal station. It is common to control the return or bypass state of the repeater.

In this case, when a fault occurs in a repeater close to a terminal station, it is possible to search for the faulty repeater relatively quickly, but as the distance from the terminal station increases, the time required for the search increases, and the search control is complicated. There were drawbacks.

In addition, a control line is provided between each repeater and the terminal station, and a fault detection means is provided in each repeater, and by detecting the occurrence of a fault, a signal specific to the repeater is sent to the terminal station via the control line. It is also proposed that

However, a control line must be provided, resulting in an uneconomical configuration for long-distance transmission.

An object of the present invention is to economically facilitate the search for a faulty repeater by transmitting faulty repeater information using a PCM transmission path.

Examples will be described in detail below.

FIG. 1 is a block diagram of one embodiment of the present invention.
is the input terminal of the repeater, OUT is the output terminal, EQ is the equalizing amplifier, AGC is the automatic gain control circuit, DET is the detection circuit that detects abnormalities in the automatic gain control voltage, TM is the timing extraction circuit, and RBG is the reproduction sending circuit. , SVS is a fault information sending circuit, OSC is a clock oscillator, DV1 is a frequency divider, G1
-G4 are gate circuits, G1 is an inhibit gate circuit, G2 is an OR gate circuit, and G3 and G4 are AND gate circuits.

During normal operation, the PCM signal applied to the input terminal IN is equalized and amplified by the equalization amplifier EQ, and is applied to the regeneration and transmission circuit REG via the gate circuits G1 and G2, and the timing signal extracted by the timing extraction circuit TM. The signal is sent from the output terminal OUT to the next stage repeater or terminal station in synchronization with .

Since the automatic gain control voltage applied from the automatic gain control circuit AGC to the equalization amplifier EQ is within a predetermined range, the output of the detection circuit DBT is set to "0".

Therefore, the AND gate circuit G3 of the fault information sending circuit SVS
, G4 are in a closed state.

If the level of the signal applied to the input terminal IN becomes abnormally low or disconnected due to the occurrence of a failure in the previous-stage repeater or the occurrence of a failure in the transmission line, the automatic gain control voltage will exhibit an abnormal value.

This is detected by the detection circuit DBT and the output is set to "1", and the gate circuit G1 is closed and the AND gate circuits G3 and G
4, so that instead of the timing signal from the timing extraction circuit TM, the clock signal from the clock oscillator OSC is applied to the Nyuu sending circuit REG via the AND gate circuit G3, and the clock signal is also applied to the Nyuu sending circuit REG via the frequency divider DV.
The frequency is divided by 1 to 1/N, and the clock signal and the frequency-divided signal are applied to the AND gate circuit G4.

The frequency divider DV1 has a frequency division ratio unique to the repeater, and the output signal of the AND gate circuit G4 is transmitted to the OR gate circuit G.
2 to the reproducing and transmitting circuit REG, and is transmitted in synchronization with the clock signal.

The clock oscillator OSC generates a clock signal with the same frequency as the timing signal, and the AND gate circuit G4 is controlled by the divided signal of the output of the divider DV1, so as shown in FIG. , an all-mark signal M and an all-space signal S, which are repeated with a period T of the frequency-divided signal, are sent out from the reproduction sending circuit REG.

The terminal station receives the fault information made up of the all mark signal M and the all space signal S to identify the occurrence of a fault, and since the period T is unique to the repeater, it can easily detect the fault repeater. can be identified.

FIG. 3 is a block diagram of another embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same parts, DV2 is a frequency divider, M
BM is a memory that stores fault information including repeater address information such as read-only memory (ROM), G5, G6
is an AND gate circuit.

As in the previous embodiment, the detection circuit DET detects that the automatic gain control voltage has become an abnormal value, and its output signal is 1.
Then, the clock signal from the clock oscillator OSC is applied to the reproduction sending circuit RBG via the AND gate circuit G3, and the clock signal is divided into 1/M by the frequency divider DV2 and applied to the memory MEM. Fault information is read from the memory MEM by the frequency divided signal.

Fault information is provided by AND gate circuit G6 and OR gate circuit G2.
The signal is sent out from the reproduction sending circuit REG via the clock signal in synchronization with the clock signal.

For example, as shown in FIG. 4, the fault information consists of all mark fault occurrence notification information A and repeater address information B, and is repeatedly sent out at a period T.

Note that the frequency divider DV2 is used to obtain a branch signal corresponding to the reading speed of the memory MEM, and is designed to use a memory having a lower speed than the transmission speed in the PCM transmission line.

Furthermore, at the terminal station, the faulty repeater can be immediately identified based on the fault occurrence notification information A and the repeater address information B.

As explained above, the present invention provides a repeater with a fault information sending circuit that sends out fault information in a pattern unique to the repeater, and detects the occurrence of a fault by detecting an abnormality in the automatic gain control voltage. The failure information is sent to the next stage repeater or terminal station in synchronization with the clock signal from the OSC, and the terminal station receives the fault information, thereby making it possible to immediately identify the faulty repeater.

Furthermore, by making the frequency division ratios of the frequency dividers different in each repeater, each repeater only needs to be provided with an oscillator having the same oscillation frequency, which has the advantage of being economically configurable.

In the above-mentioned embodiment, the fault detection means detects abnormalities in the automatic gain control voltage, and detects faults in the previous stage repeater, transmission path, and equalization amplifier EQ. Since it has a built-in oscillator OSC,
Regarding failures inside the repeater other than the playback and transmission circuit,
Fault information can be sent by fault detection.

Furthermore, since the fault information is transmitted through the PCM transmission line, there is no need to provide a control line, and a faulty repeater can be searched for economically and quickly.

[Brief explanation of drawings]

1 and 3 are block diagrams of different embodiments of the present invention, FIG. 2 is an explanatory diagram of fault information in FIG. 1, and FIG. 4 is an explanation of fault information in FIG. 3. It is a diagram. IN is an input terminal, EQ is an equalization amplifier, AGC is an automatic gain control circuit, DET is a detection circuit, TM is a timing extraction circuit, REG is a reproduction sending circuit, SVS is a fault information sending circuit, OSC is a clock oscillator, DVI, DV2 is a frequency divider, and MEM is a memory.

Claims (1)

[Claims] 1. In a method for searching for a faulty repeater in a PCM transmission method, a clock oscillator, a divider that divides the output of the clock oscillator at a frequency division ratio specific to each repeater, and a A gate circuit for periodically masking the output of the clock oscillator and fault detection means are provided, and the gate circuit is opened by the output of the fault detection means, and the output of the frequency divider is sent to the terminal station in synchronization with the clock from the clock oscillator. A faulty repeater search method, characterized in that the faulty repeater is identified by the fault information transmitted as fault information and according to the frequency division ratio by the frequency divider at the terminal station.