JPS58688B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention switches the tuning voltage applied to an electronic tuner using an electronic variable capacitance diode as a tuning element using a combination of a counter and a decoder or an electronic switching circuit such as a ring counter. To provide a channel selection device which can always select a fixed channel after power is turned on and is suitable for integrated circuit device implementation.

First, a basic configuration of an apparatus for selecting stations using a binary counter and a decoder as an electronic switching circuit will be explained with reference to FIG.

Here, 1 is a tuning voltage setting circuit that presets the tuning voltage BT to be applied to the variable capacitance diode of the tuner, and is equipped with a plurality of variable resistors 2a to 21, each of which is used to set the tuning voltage BT to be applied to the variable capacitance diode of the tuner. It is set to obtain a channel selection voltage BT, and a selected one is taken out to the terminal 4 via diodes 3a to 31, and impedance-converted by a transistor or the like (not shown) to obtain the voltage V.
It is added to each variable capacitance diode of the HF tuner and UHF tuner.

Reference numeral 5 denotes a channel switching circuit for switching which of the variable resistors 2a to 21 is to be operated, and here a binary counter 6 and a decoder 7 are used as the electronic switching circuit.

That is, a pulse generating circuit 8, a binary counter 6 that counts the pulses, a binary-hexadecimal decoder 7 that selectively generates an output according to its binary output, and the counter 6.
and a control circuit 9 that controls the operation of the pulse generation circuit 8.

The decoder 7 is equipped with an output switching transistor for each of the 16 output terminals a to p, and only one of these transistors is selectively turned on and output according to the binary output output from the counter 6. A low level output is generated at one of the terminals a to p, and the conductive transistor of the variable resistors 2a to 21 connected to the 12 output terminals a to l of the output terminals a to p is configured to generate a low level output. Current is applied to only those connected to the output terminal of the device.

When switching channels, one of the normally open switches 11a to 111 provided on the switch board 10, for example, the switch 11e, is closed.

At that time, if the channel at the position of the switch 11c is not selected, the output of the output terminal c of the decoder 7 to which this switch 11c is connected is at a high level, so the output is sent to the control circuit via the switch 11c. 9 input terminal CH.

At this time, the output from the output terminal OC causes the pulse generation circuit 8 to start generating pulses, and the generated clock pulses are applied to the counter 6 via the terminal CL, the control circuit 9, and the terminal UCL.

This causes the counter 6 to start counting, and the conductive transistors in the decoder 7 change accordingly.

When the transistor at the output terminal c to which the switch 11c is connected becomes conductive, the input terminal CH of the control circuit 9
Since the input to the channel becomes low level, the operation of the pulse generating circuit 8 is stopped, and the channel selection state is maintained until the switch for another channel is operated, and that channel is selected.

If the frequency of the clock pulses generated by the pulse generating circuit 8 is set sufficiently high, for example, about 2 KHz or more, the above-mentioned channel switching can be completed within a very short time while the switch is closed.

12U and 12D are switches that are opened and closed by operation signals such as ultrasonic waves or light when sequentially selecting channels by remote control or manual operation. When switch 12U is operated, a count-up signal is sent from the control circuit 9 to the counter 6. When the switch 12D is operated, a countdown signal is applied from the control circuit 9 to the counter 6, and the channel immediately below is selected.

Furthermore, 13 is a defeat circuit which stops the display of the channel display circuit during this switching period by the defeat signal outputted from the output terminal DEF of the control circuit 9 during channel switching, and by the output from the output terminal 14. This is for stopping the operation of the tuner AFC circuit.

A detailed configuration of the channel switching circuit 5 of this device is shown in FIG.

In the counter 6, 15A to 15D are flip-flops, 16A to 16D, 17B to 17D, and 18B to 18
D is a NOR gate, which constitutes an up/down counter.

Further, in the decoder, 19a to 19p are output switching transistors connected to the output terminals a to p, respectively, and 20a to 20p are transistors 19a to 1, respectively.
NOR gates connected to the base of 9p, 21a to 21h
are the input terminals A to D from the counter 6 and the NOR gate 20
The NAND gates connected between a to 20p constitute a binary-hexadecimal decoder.

This decoder 7 can generate 16 kinds of outputs a to p, but here, one of them a to l is used.
Twelve channels are selected using only two terminals, and when outputs are generated at the four output terminals m to p, the channels are automatically skipped.

In the pulse generation circuit 8 which generates a clock pulse to be applied as a count input to the counter 6 during channel selection, three transistors 22, 23 and 24 are connected in sequence.
A resistor 25 and a capacitor 26 for determining the oscillation frequency are connected to the base of the transistor 22, and a transistor 27 for controlling the oscillation is connected.

The collector of transistor 22 and the base of transistor 23 are connected, and the connection point between the collector of transistor 22 and the base of transistor 23 is grounded via a transistor 29 for oscillation control.

The oscillated clock pulse is taken out from the collector of the transistor 24 to the output terminal CL, and this output is also added to the base of the transistor connected between the base circuit of the transistor 22 and ground, and also to the base of the transistor 27 connected to the emitter of the transistor 22. Add it to the base as well.

An oscillation control signal that becomes low level when causing the base of the transistor 29 to oscillate is applied from the input terminal OC.

Oscillation is stopped when the oscillation control signal applied to the input terminal OC is at a high level.

On the other hand, when the oscillation control signal applied to the input terminal OC becomes a low level, an oscillation effect is performed, and as long as the oscillation control credit is at a low level, a clock pulse is generated at the output terminal CL, and the oscillation control signal becomes a high level. When the oscillation stops.

When the circuit constants are set as shown in the figure, the repetition frequency of the clock pulse is approximately 2 KHz.

Next, in the control circuit 9 that drives the counter 6 using the clock pulses generated in this way and performs a channel selection operation, a flip-flop 31 consisting of NOR gates 30U and 30D, and NOR gates 32U, 32D, 33U,
33D, the low level input that is applied to the input terminal UP when the count-up switch 12U is operated is inverted and applied to the NOR gates 30U and 33U by an inverter 34U, and the NOR gates 30D and 33D are used for countdown. The low level input applied to the input terminal DN when the switch 12D is operated is inverted and applied by the inverter 34D.

The outputs of the flip-flops 31 are respectively NOR gates 3
In addition to 2U and 32D, input terminal C from pulse generation circuit 8
Gating the clock pulse applied to L and also NO
It is combined with the outputs of inverters 34U and 34D by R gates 33U and 33D, and is added to the counter 6 as a count input from output terminals UCL and DCL.

NOR gate 33U. 33D output to inverter 35U, 3
The inverted value at 5D is also added to the counter 6 as a count input from the output terminals UCL and DCL.

In addition, in order to operate the pulse generation circuit 8 during manual tuning and when skipping channels, switches 11a to 11 for tuning are also provided.
The input applied to the input terminal CH from 1 to the input terminal CH and the input applied to the input terminal SKP from the output terminals m to p of the decoder 7 are inverted by the inverter 36 and output from the output terminal OC via the NOR gate 37. It is added to the pulse generation circuit 8 as an oscillation control signal.

38 and 39 are amplifiers for buffer amplification.

Next, the channel selection operation in such a configuration will be explained.

First, suppose that the flip-flop 15 in the counter 6
It is assumed that the outputs of A to 15D are "0000", the transistor 19a in the decoder 7 is conductive, a low level output is generated from the terminal a, and the outputs of the other terminals b to p are high level.

At this time, a current is passed through the variable resistor 2a, and the channel selection voltage set by the variable resistor 2a is taken out, so that channel a is selected.

In this state, when the up channel selection switch 12U of the channel selection switches 12U and 12D is sequentially closed by remote or manual operation, the input to the terminal UP becomes a low level.

Therefore, the output of the inverter 34U becomes high level, setting the flip-flop 31 to the first state.

Here, the first state is a state in which the output of the NOR gate 30U becomes a low level and the output of the NOR gate 30D becomes a high level.

A state opposite to this is defined as a second state.

This first state output causes the output of the NOR gate 32U to go high, passing the input from the NOR gate 33U to the terminal UP to generate an output, and inverting it in the inverter 35U to output the output from the terminals UCL and UCL, respectively. Added to counter 6 as a count up signal.

Since the counter 6 is triggered at the trailing edge of the input for counting, in this case, it is triggered at the trailing edge of the input to the terminal UP, that is, when the operation of the switch 12U is completed and it is opened, and the count contents are Upload one and the output is “
1000'', the output of the decoder 7 is moved to the terminal A, and the channel is switched to select the b channel.

Thereafter, in the same manner, every time the up channel selection switch 12U is operated, the counter 6 is triggered one step at a time in the count-up direction at the trailing edge of the operation, and the counter 6 is triggered one step at a time in the count-up direction. Channels are selected one by one.

The flip-flop 7a then switches the down channel selection switch 12D.
When is operated, it enters the second state.

Next, when the up tuning switch 12U is operated in a state where an output is generated from the terminal l in the decoder 7 and the l channel is selected, an output is generated from the next terminal m as described above. It becomes like this,
In this device, the next terminals m to p are not used and must be skipped over, so at this time the low level outputs generated at terminals m to p are applied to terminal SKP of control circuit 9. .

Then, the output of the inverter 36 becomes high level, a low level oscillation control signal is generated from the NOR gate 37, and this is applied from the terminal OC to the pulse generation circuit 8 to start its oscillation operation.

Therefore, a clock pulse is generated from the terminal CL of the pulse generating circuit 8.

However, there is a slight time delay before oscillation starts.

This clock pulse is applied to the NOR gate 32 in the control circuit 9.
U.

33U and an inverter 35U, and is applied to the counter 6 from terminals UCL and UCL as a count-up signal.

Therefore, the counter 6 automatically counts up in the upward direction, and outputs are generated one after another at the terminals n, o, and p of the decoder 7, but the outputs from these terminals n, o, and p are also output from the terminal SK.
Since the oscillation control signal continues to be generated and the clock pulse is continuously generated while the output is being generated from these signals.

Then, when the count output of the counter 6 returns to "0000" again and an output is generated from the terminal a of the decoder 7, the input to the terminal SKP disappears and the oscillation control signal also disappears, so the pulse generation circuit 8 stops generating clock pulses. Stop.

As a result, the counter 6 stops counting, and channel a is selected.

In this way, when sequentially selecting channels in the up direction, 1
Automatic jumping from channel to channel a is performed.

The sequential tuning operation in the countdown direction is basically the same as the above-mentioned sequential tuning in the up direction, and when the tuning switch 12D is closed, the input to the terminal DN becomes low level, and the flip-flop 31 is turned on. set to the second state.

Therefore, in this case, the output of the NOR gate 30D becomes a low level, and the outputs of the NOR gates 32D and 33D and the output of the inverter 35D are then applied to the counter 6 as a countdown signal from the terminals DCL and DCL.

As a result, for example, if one channel has been selected, the next channel will be selected.

Thereafter, in the same manner, each time the down channel selection switch 12D is operated, the channels are selected in the down direction in the order of →j→i, . . . .

Even if the down channel selection switch 12D is operated while channel a is selected, the next terminals p to m are
An input is applied to terminal SKP while an output is generated at
An oscillation control signal is generated to generate clock pulses, which are connected to NOR gates 32D, 33D and inverter 35.
By being applied as a countdown signal to the counter 6 via D, the next l channel is automatically selected.

Next, the operation when a channel to be selected is directly designated by operating the switch board 10 will be described.

Again, it is assumed that channel a is initially selected.

In this state, if the switch 11i of the switch board 10 is operated to select the i channel next, the output of the terminal i for the i channel in the decoder 7 is at a high level, so the output is controlled. It is applied to terminal CH of circuit 9.

The input to this terminal CH is formed by two inverters 38 and 39 and then applied to the NOR gate 30U, so the flip-flop 31 is set to the first state and the output of the NOR gate 30U is set to a low level. do.

This state is similar to the case of sequential channel selection in the up direction described above.

Therefore, in the case of direct channel selection, the counter 6 is controlled only in the direction of counting up.

On the other hand, since the input to the terminal CH is also applied to the NOR gate 37, its output becomes low level and an oscillation control signal is applied to the pulse generation circuit 8 from the terminal OC.

As a result, the pulse generation circuit 8 operates and a clock pulse is generated at its terminal CL, and this clock pulse is
The signals pass through R gates 32U and 33U and inverter 35U, respectively, and are applied to counter 6 as a count-up signal from terminals UCL and UCL.

As a result, the counter 6 counts up and switches the channel to be selected in the order of a→b→c, . . . .

When this count is performed up to the position of the i channel, the output from the terminal i becomes low level, so the terminal CH
The input to the i-channel becomes low level, the oscillation control signal also becomes low level, the clock pulse generation operation from the pulse generation circuit 8 is stopped, and counting is no longer performed, and the selected state of the i channel is maintained. .

In this way, the i-channel is directly selected.

Of course, the same applies to other channels as well.

Incidentally, if the frequency of the clock pulse is set sufficiently high at this time, such a channel selection operation can be completed during the moment when the switch is operated and closed.

In addition, when directly selecting channel C while selecting channel K, it is necessary to jump between terminals m and p of the decoder 7, but this jumping operation also occurs at the time of the count up mentioned above. The operation is similar to that of k→
Needless to say, channels are automatically selected in the order of l→a→b→c.

In this way, in this device, both sequential tuning in the up and down directions as well as direct tuning can be performed satisfactorily.

In FIG. 2, a NOR gate 40 provided in the control circuit 9 is used to generate a defeat signal at the terminal DFF during channel selection.

In the above embodiment, flip-flops and gates are used as means for controlling the count-up and count-down of the counter, but any other circuit configuration may be used as long as it performs the same operation. Needless to say.

Further, in addition to the above-mentioned combination configuration of a counter and decoder as the electronic switching means, a ring counter configuration may also be used.

Using electronic switching circuits in this way allows for the use of many digital circuit technologies, so integrated circuits (hereinafter referred to as I
(referred to as C) can be easily made into a device.

Particularly, the channel switching circuit 5 is suitable for IC implementation, and the interior surrounded by the dashed line as shown in FIG. 1 can be made of one to several IC elements.

The figure shows the case where it is made with one IC element, and the double circles indicate the main terminals required for connection with an external circuit.

Of course, if two or more IC elements are used, terminals are required to connect them.

As described above, channel selection is performed using an electronic channel switching circuit implemented as an IC, but such a device has a problem in that the channel is not constant when the power is turned on.

In other words, the counter or ring counter in the channel switching circuit does not have a constant count state when the power is turned on. You never know what will happen, and various channels are randomly selected depending on the time.

Of course, you can then select the desired channel by specifying the channel using the method described above, but the fact that the channel that is selected first when the power is turned on is not constant means that the This gives the user a sense of instability during use, which is a major negative factor in terms of usability.

For this reason, in this type of channel selection device, as seen in Japanese Patent Publication No. 51-3441, the channel switching circuit is reset by a time constant circuit using a capacitor when the power is turned on, and a fixed selection is forced. It is being done to bring it into a local state.

When this means is applied to the above-mentioned device, as shown in FIG.
Transistors 41A to 41D are connected to each Q output terminal of
are connected, their bases are all connected to the collector of a transistor 42, and a time constant circuit consisting of a resistor 43 and a capacitor 44 is connected to the base of this transistor 42.

When the power is turned on, the transistor 42 is cut off until the terminal voltage of the capacitor 44 rises, and the transistor 41A is turned off.
~41E is made conductive, and flip-flops 15A~15D
These Q output terminals are forcibly reset to a low level.

However, in the case where the flip-flops 15A to 15D of the counter 6 are reset in this way,
Since the capacitor 44 cannot be formed inside the IC element and must be additionally connected to the outside, there is a drawback that a terminal 45 must be newly provided on one side of the IC element.

As is well known, IC devices must be designed to have as few terminals as possible, so conventional devices that require an increase in the number of terminals as described above are extremely inconvenient. .

SUMMARY OF THE INVENTION Therefore, the present invention provides a channel selection device that does not have any of these inconveniences and is capable of fixing the first channel selected when the power is turned on to a specific channel without increasing the number of terminals even when integrated into an IC. For this purpose, any one of the tuning switches connected to the outside of the electronic switching circuit for tuning is kept in the same operating state as the switch for a certain period of time after the power is turned on. an initial channel setting circuit that generates a signal, and the initial channel setting circuit operates the electronic switching circuit so that the channel to which the setting circuit is connected is operated immediately after the power is turned on; The feature is that a certain channel is always selected when the system is turned on.

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

Note that the one in FIG. 4 is the initial channel setting circuit 46.
Except for the part 1. Since it is the same as that in FIG. 2, the same parts are given the same reference numerals and the explanation will be omitted.

In this embodiment, the a channel is always selected first when the power is turned on, and the initial channel setting circuit 46 for this purpose has a channel selection switch 11a connected in parallel to the a channel selection switch 11a. transistor 47
A time constant circuit consisting of a capacitor 48 and a resistor 49 connected to the base of the transistor 47 is provided so as to conduct the transistor 47 for a certain period (for example, 10 m5) when the power is turned on.

Note that 50 and 5152 are resistors and transistors that constitute a filter circuit for preventing noise mixing provided between the switches 11a to 111 and the terminal CH.

According to such a configuration, when the power is turned on, the transistor 47 is conductive for a certain period of time, which is equivalent to closing the channel selection switch 11a, and the counter 6 selects channels other than channel A immediately after the power is turned on. Even if the channel becomes OFF, the transistor 47 is conductive, so that a channel selection operation similar to the above-mentioned direct channel selection operation is performed, and the a channel is forcibly selected.

Since this operation is performed immediately after the power is turned on, the viewer can assume that the a channel has been selected from the time the power is turned on.
This makes it possible to provide the viewer with a sense of stability that the channel will be selected, resulting in a device that is easy to use.

FIG. 5 shows a second embodiment, which further ensures the above-described operation immediately after power is turned on.

That is, in order to control the control circuit 9 after power is turned on, the transistor 47 is made conductive for a certain period determined by the time constant of the time constant circuit consisting of the capacitor 48 connected to the base of the transistor 47 and the resistor 49 as described above. A drive current is applied to the terminal CH, but in order to control the control circuit 9, it is safe to have a drive current of a certain level or more. It is necessary to maintain the above driving current at a constant current or higher for a certain length of time.

However, if you try to keep the drive current from the transistor 47 large for a long period of time by increasing the time constant of the time constant circuit on the base side of the transistor 47, the supply time of the drive current will decrease if the power switch is turned off and on at short intervals. There is a risk that the length may become short and the operation may become uncertain.

Therefore, in the device shown in FIG. 5, instead of increasing the time constant of the time constant circuit, the switches 11a to 111 and the terminal CH
A filter circuit for preventing noise mixing, which is connected between the two terminals, is connected to the terminal CH via the diode 53, thereby eliminating the possibility of malfunction.

That is, if this diode 53 is not present, the current from the transistor 47 will be shunted to the terminal CH side and the resistor 51 of the filter circuit, and there is a risk that the current will drop below the minimum drive current at an early stage. If provided, the resistor 5 will be connected from the emitter of the transistor 47 when the power is turned on.
1 can be eliminated, and the control circuit 9
This allows the drive current applied to the motor to be maintained at a constant level or higher for a long period of time.

Furthermore, FIG. 6 shows an embodiment in which noise mixing from the initial channel setting circuit 46 side is also prevented, in which a capacitor 54 for noise bypass is connected to the base of the transistor 47, and a coil 55 is further connected in series with the capacitor 48. This is to prevent noise from entering the power supply.

Since most of the noise coming in from the power supply has a high frequency, it can be sufficiently blocked by appropriately selecting the values of the capacitor 54 and the coil 55. Furthermore, by inserting this coil 55, the noise that comes in when the power is turned on can be sufficiently blocked. Adverse effects on the operation of the constant circuit can also be almost eliminated.

In some cases, only one of the capacitor 54 and the coil 55 is required.

In the above embodiments, transistors were used as switching elements for the initial channel setting circuit 46, but as in the embodiment shown in FIG. 7, diodes 56. 57, both ends thereof may be connected to the switches 11a to 111 and the terminal CH, respectively, and a time constant circuit may be connected to the middle point.

Furthermore, in the configuration described above, since the initial channel setting circuit 46 is connected to the channel selection switch 11a connected to the outside of the electronic switching circuit, there is no manual access inside the channel switching circuit 5. There is no need to worry about adding additional components, and there is no need to increase the number of terminals even when the part surrounded by the dashed-dotted line is created using an IC element, and the effect can be achieved by using only an external circuit.

Therefore, there are no obstacles when converting it into an IC element.
This can greatly contribute to the development of IC devices.

It goes without saying that this initial channel setting circuit 46 can be arbitrarily used even if it has a circuit configuration other than that shown in the above embodiment as long as it is switched only for a certain period of time after the power is turned on. Needless to say, if you want to set a channel other than that channel, you just need to connect it to the channel selection switch of the desired channel.

Furthermore, the present invention can be implemented in a channel selection device that uses an electronic switching circuit composed of a ring counter or the like in addition to an electronic switching circuit composed of a counter and a decoder, and in that case, the counter and decoder shown in the figure All you have to do is replace that part with a ring counter or the like.

Furthermore, since the above embodiment uses a normally open type switch that is closed when a channel is selected as a channel selection switch, the initial channel setting circuit is a circuit that becomes conductive for a certain period of time when the power is turned on. were used by connecting them in parallel,
If a normally closed switch is used as the channel selection switch, it is necessary to use an initial channel setting circuit that shuts off for a certain period of time when the power is turned on, connected in series with the switch. In either case, it is sufficient to use a circuit that produces the same effect as if a channel selection switch had been operated for a certain period of time after the power was turned on.

As detailed above, according to the present invention, instead of changing the electronic switching circuit itself, the initial channel setting circuit is connected to any one of the tuning switches connected externally. This makes it possible to create an easy-to-use device that always selects a certain channel when the power is turned on, giving the viewer a sense of stability when using it, and has a configuration suitable for making it into an integrated circuit device. It is something that can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an example of a channel selection device using an electronic switching circuit, FIG. 2 is a circuit diagram of a main part of a conventional channel selection device, and FIGS. 3 and 4 are an embodiment of the present invention. FIGS. 5, 6, and 7 are circuit diagrams of essential parts of the channel selection device in other embodiments of the present invention, respectively. 1... Voltage setting circuit for channel selection, 5... Channel switching circuit, 6... Counter, 7...
...Decoder, 8...Pulse generation circuit, 9.
...Control circuit, 10...Switch panel, 1
1a-111...Switch for channel selection, 46...
...Initial channel setting circuit, 47...Transistor, 48...Capacitor and resistor for time constant circuit, 50, 51, 52...Resistor for filter circuit and capacitor, 53... diode, 54... capacitor, 55...
・Coil, 56°57...Diode.

Claims (1)

[Scope of Claims] 1. A tuning voltage setting circuit that sets a tuning voltage to be applied to an electronic tuner for each channel; an electronic switching circuit that selects the tuning voltage electronically; a pulse generation circuit that supplies switching pulses to the electronic switching circuit; a tuning switch that is provided for each channel and controls the switching state of the electronic switching circuit for each channel; and a control circuit provided between the electronic switching circuit and a state in which a predetermined one of the channel selection switches is operated for a certain period of time after power is turned on. The channel selection device is characterized in that an initial channel setting circuit that produces the same state as the above is connected, and when the power is turned on, the initial channel setting circuit always selects the channel of the connected switch. 2. The electronic switching circuit and the pulse generation circuit are built into an integrated circuit element, and the channel selection switch is connected to the outside of the integrated circuit element. A channel selection device according to claim 1. 3. The channel selection device according to claim 1, wherein the initial channel setting circuit has a time constant circuit that determines its operating time and a filter element for preventing noise mixing. 4. Claim 1, characterized in that the initial channel setting circuit has a transistor connected in parallel with a predetermined switch, and a time constant circuit is connected to the base of the transistor. The channel selection device described. 5. The initial channel setting circuit has two diodes connected in series with opposite polarities, and the series circuit is connected in parallel with a predetermined switch. 2. The channel selection device according to claim 1, further comprising a constant circuit connected thereto.