JPS5913058B2 - array processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention &A relates to an array processing device that enables high-speed processing of array operations when array operands are disposed non-contiguously on main memory.

In an array operation that is generally implemented by a program loop, array operand elements used in one loop are arranged at certain address intervals on the main memory. If this address interval is equal to the array operand element length, the array operands are considered to be continuous, and if not, the array operands are considered to be non-contiguous. Conventionally, in array arithmetic processing in the case of discontinuous array operands, the array operand elements to be executed sequentially are arranged intermittently on the main memory address, so the corresponding operand is transferred to the main memory at the point when it is needed each time the arithmetic operation is performed. It was fetching from the device. Therefore, the processing in the arithmetic unit has to wait until the array operand element is taken out from the main memory and sent to the arithmetic unit, resulting in a significant drop in performance due to the access time of the main memory.
To improve this, it is possible to have a buffer storage device and use a block transfer function to store the vicinity of the required array operand element as an l block, but it is possible to keep a copy in the buffer storage, but in the case of discontinuous array operand elements Since there is no sequentiality in the addresses of elements to be processed, we cannot expect much performance improvement by referring to neighboring data as array operand elements, which are copies, and the use of buffer storage devices There was also the fear that this would lead to a decrease in efficiency. The object of the present invention is to prefetch a fixed block of array operand elements by means of a block transfer function when the array operand elements are contiguous, but also to prefetch the preceding array operand elements when the array operand elements are noncontiguous. Achieves advance generation of field operand element addresses,
The preceding array operand element is fetched from the main memory using the generated address and stored in the operand stacker, and when the arithmetic unit needs the array operand element, the element is quickly fetched from the stacker. The objective is to provide a substantial amount of data to improve the performance of array operations.

Therefore, in the present invention, when the array operand elements are consecutive, the block transfer function provided in the device is used to prefetch the array operand elements.
In order to perform prefetching even when the array operand elements are non-contiguous, a means for detecting contiguity/discontinuity of the array operand elements, a plurality of operand address registers equal to the number of operands required in the array operation, and sequential execution are provided. It has a plurality of increment registers that hold increment values representing the difference in addresses between array operand elements, and when it is detected that the array operand elements are stored non-contiguously in main memory, the operand address A plurality of preceding array operand element addresses are generated from the increment value, and pre-fetching and stacking of the preceding array elements is performed in parallel with the array operation of the arithmetic unit. It is characterized by having a function that can supply the corresponding elements to the arithmetic device at high speed. Hereinafter, the contents of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows that the length of one element is equal to the increment value when array operand elements are placed consecutively in the order of sequential execution on the main memory.

Here, the array operand element length indicates the length of one element of the array elements to be executed sequentially,
The array operand element increment value indicates the address increment from the location where the element is located to the location where the next element is located. As shown in Figure 1, if the element length and increment value are equal, each element is placed consecutively, for example between element 0 and element 1, between element 1 and element 2, etc. There are no regions. In this case, the pre-fetching of the operand element can be easily realized using the block transfer function since the addresses are consecutive. FIG. 2 shows a case where the array operand elements placed on the main memory are placed non-contiguously in the order of sequential execution, and the increment value is larger than the element length. As is clear from Figure 2, when the increment value is larger than the element Z length, each element becomes discontinuous on the main memory, for example between element 0 and element 1, between element 1 and element 2, etc. There is an unused area. The present invention is directed to high-speed processing of array operations when the array operand elements are disposed non-contiguously on the main memory.
FIG. 3 shows a block diagram of one embodiment of the present invention.

In the figure, operand address registers 1 and 2 are registers that hold the addresses of the first and second operand elements, respectively, and increment Z registers 3 and 4 hold the increment values of the first and second operands, respectively. This is a register for This is an example in which the number of operands handled in the array operation is two, but the number of operands can be set to any number, and in reality, a corresponding number of operand address registers and increment registers are prepared. At the beginning of instruction execution, the first operand address register 1, the second operand address register 2, and the first operand increment register 3
, and initializes the second operand increment register 4, which is used to generate advance fetch addresses for subsequent array operand elements. That is, prior to execution of the array operation, the contents of the first operand increment register 3 and the second operand increment register 4 are sent to the address continuity check device 5, and the consecutive or non-contiguous array elements are checked for each first and second operand. investigate. Detection of continuous or discontinuous array elements is
As shown in FIGS. 1 and 2, this is done by checking whether the increment value of each operand is equal to the length of each corresponding operand element. The address continuity check device 5 sends continuous and non-continuous results to the control device 14. In the case of continuous operation, the control device 14 passes advance fetch control to a block transfer function (not shown), but since this control is well known and is not part of the gist of the present invention, a description thereof will be omitted. In the case of discontinuity, if the first operand element is fetched by a command from the control device 14, the first operand element address of the first operand address register 1 and the first operand increment value of the first operand increment register 3 are fetched. and the contents of the first operand fetch pointer 6 are sent to the first operand address generator 7.

The initial value of the first operand fetch pointer 6 is set to n if the operation is started from the nth array element counting from the array element existing at the address indicated by the first operand address register 1. Ru. The first operand address generator 7 multiplies the sent first operand increment value and the first operand fetch pointer value, and generates the sum of the product and the first operand address as the first operand element address. do. If the first operand element address can be generated, a fetch request is issued to the main storage device 16 using that address. Upon receiving the fetch request, the main storage device 16 retrieves the target array element from the corresponding address and sends it to the first operand stacker 11.
The first operand stacker 11 holds the array operand until the arithmetic unit 15 uses it. This completes the operation of fetching one array element of the first operand, but the control device 14 continues to fetch the first array element.
The contents of the operand fetch pointer 6 are updated, and the first operand address generator 7 generates an address using the updated pointer and issues a fetch request to the main memory 16. By repeating this operation, the first operand element is automatically fetched before the arithmetic unit 15 issues a use request, and a plurality of first operand elements at non-consecutive addresses are stored in the first operand stacker 11. The preceding fetch of the second operand element is performed in the same manner as the fetch of the first operand element, and is performed in parallel with the fetch operation of the first operand element.

The preceding fetch of the second operand includes a second operand address register 2, which has the same functions as those used in the first operand fetch, a second operand increment register 4, a second operand fetch pointer 8, and a second operand address generation register. The fetched second operand array elements are sequentially stored in the second operand stacker 13. For calculation in the calculation device 15,
If an array element is required, the arithmetic unit 15 issues a request to the control unit 14. At this time, if the request is for the first operand element, the first operand pointer 1
The stored array elements are transferred to the arithmetic unit 15 from the corresponding position in the first operand stacker 11 indicated by 0.
send to. When the corresponding array element is sent out, the first
The value of operand pointer 10 is the first value to be used next.
It is updated to point to the corresponding position in the first operand stacker 11 where the operand element is stored. When the arithmetic unit 15 requires the second operand element, the operation is the same as the operation sent when the first operand array element is required. ,,, When the a-th operand door/ray element is required, the Z-second operand pointer 12 and the second operand stacker 13 are used, and the corresponding array operand element is sent from the second operand stacker 13 to the arithmetic unit 15. It will be done.

In FIG. 3, the control device 14 performs pre-fetching of the first and second operand elements and sending the operand elements to the arithmetic device 15 independently and in parallel, and also stores the arithmetic results in the main storage device 16.
These two operations are performed independently.

As explained above, according to the present invention, even when array operand elements are arranged non-contiguously in main memory, it is possible to minimize performance degradation caused by the non-contiguous nature. Therefore, it is possible to reduce the performance difference between array arithmetic processing of continuous and non-contiguous element arrangements.

Furthermore, play in the arithmetic device due to the time available for array elements can be minimized, making it possible to further improve the usage efficiency of the arithmetic device.

[Brief explanation of drawings]

FIG. 1 shows a case in which array operand elements are arranged consecutively on the main memory, and FIG. 2 shows a case in which they are similarly arranged non-contiguously. FIG. 3 shows a block diagram of an embodiment of the present invention, in which there are two sets of operands. 1
, 2... Operand address register, 3, 4...
Operand increment register, 5... Address continuity check device, 6, 8... Operand fetch pointer, 7, 9... Operand address generator, 10
, 12... Operand pointer, 11, 13... Operand stacker, 14... Control device, 15... Arithmetic device, 16... Main storage device.

Claims (1)

[Claims] 1 An address register that holds the array element operand address of each of a plurality of array operands stored on the main memory, and an increment value that indicates the difference in address between array elements to be executed sequentially. an increment register; and an address continuity check means that receives the increment value as an input and detects whether each array operand element is stored consecutively with respect to the main memory address, and if it is not consecutive. To do this, a preceding array operand element address is created from the increment value and the array operand address, and the desired operand stack is fetched one after another from the main memory before the arithmetic unit needs the corresponding operand. 1. An array processing device characterized in that the operands are stored in the operands, and when the arithmetic device requires the operands, the corresponding operands are supplied to the arithmetic device from the corresponding operand stacker.