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JPS59130B2 - Method for measuring electrical characteristics of defects at the interface between insulating films and semiconductors - Google Patents
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JPS59130B2 - Method for measuring electrical characteristics of defects at the interface between insulating films and semiconductors - Google Patents

Method for measuring electrical characteristics of defects at the interface between insulating films and semiconductors

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Publication number
JPS59130B2
JPS59130B2 JP14000978A JP14000978A JPS59130B2 JP S59130 B2 JPS59130 B2 JP S59130B2 JP 14000978 A JP14000978 A JP 14000978A JP 14000978 A JP14000978 A JP 14000978A JP S59130 B2 JPS59130 B2 JP S59130B2
Authority
JP
Japan
Prior art keywords
capacitance
interface
semiconductor
insulating film
measurement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14000978A
Other languages
Japanese (ja)
Other versions
JPS5567147A (en
Inventor
王義 山崎
卓雄 菅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shingijutsu Kaihatsu Jigyodan
Original Assignee
Shingijutsu Kaihatsu Jigyodan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shingijutsu Kaihatsu Jigyodan filed Critical Shingijutsu Kaihatsu Jigyodan
Priority to JP14000978A priority Critical patent/JPS59130B2/en
Publication of JPS5567147A publication Critical patent/JPS5567147A/en
Publication of JPS59130B2 publication Critical patent/JPS59130B2/en
Expired legal-status Critical Current

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  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 本発明は、絶縁膜と半導体界面の捕獲中心の密度、エネ
ルギー準位、捕獲断面積等の電気的特性を金属一絶縁膜
一半導体(MIS)ダイオードの方形波応答の温度依存
性より、高感度、高精度でしかも簡便に測定する方法に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention describes the electrical characteristics such as the density, energy level, and trapping cross section of trap centers at the interface between an insulating film and a semiconductor to determine the square wave response of a metal-insulating film-semiconductor (MIS) diode. The present invention relates to a method for easily measuring temperature dependence with high sensitivity and high accuracy.

絶縁膜一半導体界面の電気的特性は、バイポーラ・トラ
ンジスタや電界効果トランジスタ等の半導体素子及び集
積回路の動作に対して本質的な影響を与えるため、この
界面の電気的特性を、密度、エネルギー準位等の静的な
性質ばかりでなく、捕獲断面積等の動的な性質まで高感
度でしかも簡便に測定することは極めて重要なものであ
る。従来、絶縁膜一半導体界面の電気的特性の測定法と
しては、MISダイオードのアドミタンスのバイアス電
圧及び周波数依存性より求める方法が各種知られている
。しかし、この方法では本質的に半導体表面電位を高精
度で求める必要があるが、絶縁膜中の固定電荷あるいは
絶縁膜一半導体界面の凹凸による表面電位の二次元的分
散及び半導体中の浅い不純物密度の深さ方向の不均一等
による誤差を生じ、その測定精度、感度とも充分なもの
とは言えない。又、静的な界面の特性は比較的短時間で
測定可能であるが、動的な特性まで求めようとすると一
般に長時間を要する。ところで、半導体p−n接合ある
いはショットキー接合の接合容量の方形波過度応答を2
つのサンプリング時間を0、を2における容量の差ΔC
で評価し、この容量差の温度掃引より、接合部に存在す
る深い不純物準位の電気的性質、すなわち、エネルギー
準位、捕獲断面積、密度の空間分布を測定するDLTS
(Deep−LevelTransientSpect
roscopy)と呼ばれている方法があり、高感度、
高精度を有することが確認されており、MISダイオー
ドの絶縁膜一半導体界面の界面準位の測定にも応用され
ている。
The electrical properties of the insulating film-semiconductor interface have a fundamental influence on the operation of semiconductor devices such as bipolar transistors and field effect transistors, and integrated circuits. It is extremely important to easily and sensitively measure not only static properties, such as the concentration, but also dynamic properties, such as the capture cross section. Conventionally, as a method for measuring the electrical characteristics of an insulating film-semiconductor interface, various methods have been known in which the electrical characteristics are determined from the bias voltage and frequency dependence of the admittance of a MIS diode. However, in this method, it is essentially necessary to obtain the semiconductor surface potential with high precision; however, it is necessary to obtain the surface potential due to fixed charges in the insulating film or two-dimensional dispersion of the surface potential due to irregularities at the insulating film-semiconductor interface, and the shallow impurity density in the semiconductor. Errors occur due to non-uniformity in the depth direction, etc., and both measurement accuracy and sensitivity cannot be said to be sufficient. Further, although static interface characteristics can be measured in a relatively short time, it generally takes a long time to determine dynamic characteristics. By the way, the square wave transient response of the junction capacitance of a semiconductor p-n junction or Schottky junction can be expressed as 2
Difference in capacitance ΔC between two sampling times 0 and 2
DLTS measures the electrical properties of deep impurity levels existing in the junction, that is, the spatial distribution of energy levels, trapping cross sections, and density, from the temperature sweep of this capacitance difference.
(Deep-LevelTransientSpect
There is a method called ``roscopy'', which has high sensitivity and
It has been confirmed that it has high accuracy, and it is also applied to the measurement of the interface state at the insulating film-semiconductor interface of MIS diodes.

しかし、温度掃引中方形波印加電圧を一定に保つ従来の
方法では例えばサンプリング時間tlにおける容量c(
tl)がフェルミ準位の温度依存性のため温度により変
化し、そのため、MISダイオードの界面準位の測定に
応用した場合C(tl)の変化を逐一補正する必要が生
じ、DLTSのスペクトロスコピツクな特徴が充分生か
されていない欠点がある。これに対して本発明の方法は
従来の上記DLTSをMISダイオードの絶縁膜一半導
体界面の界面準位測定用に改良したものであつて、その
目的とする所は、温度掃引中にサンプリング時間tlま
たはを2における高周波容量を一定にするように印加方
形波電圧に帰還系をもうけ、複雑な計算器処理すること
なく直接界面準位密度のエネルギー分布をX−Yレコー
ダ上に記録させ、かつ、捕獲断面積もそのレコーダ上の
図面より極く簡単に求めることができる測定法を提供し
ようとするものである。
However, in the conventional method of keeping the square wave applied voltage constant during temperature sweep, for example, the capacitance c(
tl) changes with temperature due to the temperature dependence of the Fermi level. Therefore, when applied to the measurement of the interface state of a MIS diode, it is necessary to correct each change in C(tl), and the spectroscopic method of DLTS It has the disadvantage that its characteristics are not fully utilized. In contrast, the method of the present invention is an improved version of the conventional DLTS for measuring the interface state at the insulating film-semiconductor interface of a MIS diode, and its purpose is to measure the sampling time tl during temperature sweep. Or, a feedback system is provided for the applied square wave voltage so as to keep the high frequency capacitance at 2 constant, and the energy distribution of the interface state density is directly recorded on the X-Y recorder without complicated computer processing, and The objective is to provide a measurement method that allows the captured cross-sectional area to be determined very easily from the drawing on the recorder.

以下、本発明の手法を実施例を交えて詳細に説明する。Hereinafter, the method of the present invention will be explained in detail with reference to examples.

本発明による測定法を実施するための界面準位測定装置
の一例の構成の大要を第1図に示す。約30分〜1時間
に亘る温度掃引中約80Kから400K程度まで昇温可
能なクライオスタツト1内に測定すべきMISダイオー
ド2を配置し、その高周波容量C(t)と標準容量3の
容量値COとの差C(t)−COを高速応答の差動測定
型の容量計4で測定する。この高周波容量の測定周波数
は、例えば1MIIzとすることができる。また標準容
量COはバイアス電圧を与えたときの静止状態の容量値
またはその近傍の値を選定することができる。この時、
MISダイオード2には容量計4を介して方形波発生器
5と帰還型直流電源6により第2図aに示す如き方形波
状の繰返し電圧を印加する。ただし、第2図ではn型半
導体基板を有するMISダイオード2の場合を例示して
いる。この方形波電圧のパルス幅、周期は任意に設定で
き、またピーク値電圧Vbはフラツトバンド電圧より正
の電圧とし、半導体表面に電子の蓄積層を形成し、界面
準位に電子が捕獲されている状態とする。ここで、MI
Sダイオード2に印加するバイアス電圧を、半導体表面
に空乏層が形成される電圧Va、例えば−3に変化させ
た時、界面準位から伝導帯への電子が放出され、これに
伴なつてMISダイオード2の高周波容量C(t)は第
2図bに例示する如く変化する。この過度応答を2つの
サンプリング時間T,,t2、例えばt1=5ms..
t2=10msにおける容量の差ΔC(=−C(T2)
−C(T2))で評価する。この容量差を2入力型のボ
ツクスカ一・アベレジヤー7で測定する。さて、この容
量差ΔCをMISダイオード2の温度に対して図示する
のが従来のDLTSであるが、本発明の方法では温度掃
引中、一方のサンプリング時間t1における高周波容量
C(t1)が標準容量COに等しくなる様にバイアス電
圧Vaに対して帰還路をもうける。すなわち第1図に示
すように容量計4で測定した高周波容量C(T,)と標
準容量Gとの差C(T,)−COをボツクスカ一・アベ
レジヤー7を介して帰還型直流電源6に供給する。この
場合bも同時に変化するが、半導体表面に電子の蓄積層
さえ出来ていれば何ら支障ないので、方形波電圧のピー
ク値を充分大きく取つておけばよい。さて、MISダイ
オード2の温度を、例えば熱電対8により測定し、その
出力をさらにリニアライザー9により絶対温度T(k)
に比例する出力に変換する。そして容量差ΔCと絶対温
度Tとの比ΔC/Tを割算器10により出力し、このΔ
C/Tを絶対温度Tに対してX−Yレコーダ11上に記
録すると、ΔC/Tが界面準位密度に比例し、Tがほぼ
エネルギー準位に比例するため、直接X一Yレコーダ上
に界面準位密度のエネルギー分布が描かれる。又、捕獲
断面積はサンプリング時間Tl,t2を変えて今一度測
定し、2つの曲線の変化より簡単に決定される。次に上
記の事項を理論式を用いて以下に説明する。
FIG. 1 shows an outline of the configuration of an example of an interface level measuring device for carrying out the measuring method according to the present invention. The MIS diode 2 to be measured is placed inside the cryostat 1, which can be heated from about 80K to about 400K during a temperature sweep for about 30 minutes to 1 hour, and its high frequency capacitance C(t) and the capacitance value of the standard capacitance 3 are measured. The difference C(t)-CO with CO is measured with a high-speed response differential measurement type capacitance meter 4. The measurement frequency of this high frequency capacitance can be, for example, 1 MIIz. Further, as the standard capacitance CO, a capacitance value in a resting state when a bias voltage is applied or a value close to the capacitance value can be selected. At this time,
A square wave-like repetitive voltage as shown in FIG. 2a is applied to the MIS diode 2 by a square wave generator 5 and a feedback DC power source 6 via a capacitance meter 4. However, FIG. 2 illustrates the case of the MIS diode 2 having an n-type semiconductor substrate. The pulse width and period of this square wave voltage can be set arbitrarily, and the peak value voltage Vb is set to be a voltage more positive than the flat band voltage, so that an electron accumulation layer is formed on the semiconductor surface and electrons are captured in the interface state. state. Here, MI
When the bias voltage applied to the S diode 2 is changed to a voltage Va at which a depletion layer is formed on the semiconductor surface, for example -3, electrons are emitted from the interface state to the conduction band, and along with this, the MIS The high frequency capacitance C(t) of the diode 2 changes as illustrated in FIG. 2b. This transient response is divided into two sampling times T,, t2, for example t1=5ms. ..
Capacitance difference ΔC (=-C(T2) at t2=10ms
-C(T2)). This capacitance difference is measured using a two-input type box scan averager 7. Now, in the conventional DLTS, this capacitance difference ΔC is plotted against the temperature of the MIS diode 2, but in the method of the present invention, during temperature sweep, the high frequency capacitance C(t1) at one sampling time t1 is the standard capacitance. A feedback path is provided for the bias voltage Va so that it is equal to CO. That is, as shown in FIG. 1, the difference C(T,)-CO between the high frequency capacitance C(T,) measured by the capacitance meter 4 and the standard capacitance G is sent to the feedback type DC power supply 6 via the box filter and averager 7. supply In this case, b changes at the same time, but there is no problem as long as an electron storage layer is formed on the semiconductor surface, so the peak value of the square wave voltage should be set sufficiently large. Now, the temperature of the MIS diode 2 is measured by, for example, a thermocouple 8, and the output is further converted to an absolute temperature T(k) by a linearizer 9.
Convert to an output proportional to . Then, the divider 10 outputs the ratio ΔC/T between the capacitance difference ΔC and the absolute temperature T.
When C/T is recorded on the X-Y recorder 11 against the absolute temperature T, ΔC/T is proportional to the interface state density and T is approximately proportional to the energy level, so it is recorded directly on the X-Y recorder. The energy distribution of the interface state density is drawn. Furthermore, the capture cross section is measured once again by changing the sampling times Tl and t2, and is easily determined from the changes in the two curves. Next, the above matters will be explained below using theoretical formulas.

今、n型半導体基板のMISダイオード2を例に取ると
、エネルギー準位Eにおける界面準位密度Nss(E)
は、で表わされる。
Now, taking MIS diode 2 of an n-type semiconductor substrate as an example, the interface state density Nss(E) at energy level E
is expressed as.

ただしεsは半導体の誘電率、NDは浅いドナー密度、
kはボルツマン定数、COxは酸化膜容量、Aは金属電
極面積であり、その他の記号はすでに定義してある。又
、エネルギー準位Eはで表わされる。
However, εs is the dielectric constant of the semiconductor, ND is the shallow donor density,
k is Boltzmann's constant, COx is oxide film capacitance, A is metal electrode area, and other symbols have already been defined. Also, the energy level E is expressed as.

ただしEcは半導体伝導帯下端のエネルギー、Ncは伝
導帯の電子の実効準位密度、Vnは電子の熱速度、σn
(E)はそのエネルギー準位での電子に対する捕獲断面
積である。第(1)式よりC(t1)を一定にすること
によりΔC/TがNssに比例することが、第(2)式
より捕獲断面積がエネルギー準位に強く依存しない場合
は絶対温度TがEcから測つたエネルギー準位に比例す
ることが明らかで、界面準位密度のエネルギー分布が直
接X−Yレコーダ11上に記録されることがわかる。さ
て、捕獲断面積、及び温度とエネルギー準位との関係は
第(2)式を利用して求めることができる。
However, Ec is the energy at the bottom of the semiconductor conduction band, Nc is the effective level density of electrons in the conduction band, Vn is the thermal velocity of electrons, σn
(E) is the capture cross section for electrons at that energy level. Equation (1) shows that by keeping C(t1) constant, ΔC/T is proportional to Nss. Equation (2) shows that if the capture cross section does not strongly depend on the energy level, then the absolute temperature T It is clear that Ec is proportional to the energy level measured, and it can be seen that the energy distribution of the interface state density is directly recorded on the XY recorder 11. Now, the capture cross section and the relationship between temperature and energy level can be determined using equation (2).

具体的手法を第3図に示す。すなわち、サンプリング時
間Tl,t2の比T2/t1を一定に保つて変化させ、
Tl,t′2とする。この時ΔC/T対Tを表わす曲線
AおよびBは第3図に示す如く相互にシフトする。とこ
ろで同じエネルギー準位に対応する界面準位密度は当然
等しいため第(1)式より同じΔC/T値を有する。逆
に言うと、任意の等しいΔC/Tに対応する温度を第3
図の如くT,T′とすると、これは同じエネルギー準位
に対応し、第(2)式を用いて捕獲断面積σnは、で与
えられる。
The specific method is shown in Figure 3. That is, the ratio T2/t1 of the sampling times Tl and t2 is kept constant and changed,
Let Tl,t'2. At this time, curves A and B representing ΔC/T versus T shift relative to each other as shown in FIG. Incidentally, since the interface state densities corresponding to the same energy level are naturally equal, they have the same ΔC/T value according to equation (1). Conversely, the temperature corresponding to any equal ΔC/T is the third
As shown in the figure, T and T' correspond to the same energy level, and the capture cross section σn is given by using equation (2).

ただしVnNcのT2の温度依存性を考慮しておりVZ
,V〃は300Kにおける値をを意味する。で与えるれ
る。
However, considering the temperature dependence of T2 of VnNc, VZ
, V〃 means the value at 300K. given by.

このように簡単な計算により捕獲断面積、エネルギー準
位を求めることができる。さて、具体的実施例として、
乾燥酸素中での高熱酸化によりシリコン表面上に形成し
たSiO2と基板シリコン界面の界面準位について測定
した結果を第4図に示す。第4図の曲線aはt1=5m
s,t2−10msのサンプリング時間で測定したΔC
/T対Tを界面準位密度Nss対エネルギー準位Eの目
盛りに変換したものである。ほぼEc一0.4eVから
Ec−0.5eVの広範囲にわたる測定が可能であるこ
とがわかる。第4図bは捕獲断面積のエネルギー依存性
を示す。捕獲断面積の平均値は約10−16cILで一
定であつた。なお、当絶のことではあるが、必ずしも温
度掃引を2回以上する必要はなく、Tl,t2,t3の
3つの時間でサンプリング可能な装置を用い、)の2出
力を取り出せば1回の温度掃引で充分であり、測定時間
が半分に短縮される。
In this way, the capture cross section and energy level can be determined by simple calculations. Now, as a specific example,
FIG. 4 shows the results of measurement of the interface level at the interface between SiO2 formed on the silicon surface by high-temperature oxidation in dry oxygen and the substrate silicon. Curve a in Figure 4 is t1=5m
ΔC measured with a sampling time of s, t2 - 10ms
/T vs. T is converted into a scale of interface state density Nss vs. energy level E. It can be seen that measurement over a wide range from approximately Ec-0.4 eV to Ec-0.5 eV is possible. Figure 4b shows the energy dependence of the capture cross section. The average capture cross section remained constant at approximately 10-16 cIL. Although it is a matter of course, it is not necessarily necessary to perform the temperature sweep more than once; if you use a device that can sample at three times, Tl, t2, and t3, and take out the two outputs of A sweep is sufficient and the measurement time is cut in half.

この場合にはいずれか1つのサンプリング時間における
容量値が標準容量COに等しくするようにすればよいが
、中間のT2における容量値C(T2)をCOに等しく
した方が、測定処理が容易となるため有利である。かく
の如く、本発明の測定法は、接合容量の過度応答の一種
であるDLTSをMISダイオードの絶縁膜一半導体界
面の界面準位測定用に改良したものであり、サンプリン
グ時間t1の容量C(t1)を温度掃引中変化しないよ
うに印加電圧に帰還をかけることにより界面準位密度の
エネルギー分布を直接X−Yレコーダ上に記録させ、か
つ、同時に捕獲断面積まで求めることを可能にする簡便
にして高感度な測定法である。
In this case, the capacitance value at any one sampling time may be made equal to the standard capacitance CO, but it is easier to make the measurement process by making the capacitance value C (T2) at the intermediate T2 equal to CO. It is advantageous because As described above, the measurement method of the present invention is an improved version of DLTS, which is a type of junction capacitance transient response, for measuring the interface state at the insulating film-semiconductor interface of a MIS diode. By applying feedback to the applied voltage so that t1) does not change during the temperature sweep, the energy distribution of the interface state density can be directly recorded on the X-Y recorder, and the capture cross section can also be determined at the same time. It is a highly sensitive measurement method.

その上、一般に面内分布を持つ半導体表面電位を介する
測定法でないこと、浅い不純物密度の深さ方向分布の特
別な仮定をする必要がないことから、精度の良い測定法
でもある。
Furthermore, it is a highly accurate measurement method because it is not a measurement method that uses the semiconductor surface potential, which generally has an in-plane distribution, and there is no need to make special assumptions about the shallow depth distribution of impurity density.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の測定法を実施する装置の一例の構成の
概略図、第2図aおよびbは、それぞれ印加電圧及びM
ISダイオードの高周波容量の時間変化の概念図、第3
図はエネルギー準位及び捕獲断面積を求める手順の説明
図であり、第4図は、SiO2/Si系のMISダイオ
ードについての測定例である。 1・・・・・・クライオスタツト、2・・・・・・MI
Sダイオード、3・・・・・・標準容量、4・・・・・
・差動測定型容量計、5・・・・・・方形波発生器、6
・・・・・・帰還型直流電源、7・・・・・・ボツクス
カーアベレジヤ一、8・・・・・・熱電対、9・・・・
・・リニアライザー 10・・・・・・割算器、11・
・・・・・X−Yレコーダ。
FIG. 1 is a schematic diagram of the configuration of an example of an apparatus for carrying out the measurement method of the present invention, and FIGS. 2a and 2b illustrate the applied voltage and M
Conceptual diagram of time change of high frequency capacitance of IS diode, Part 3
The figure is an explanatory diagram of the procedure for determining the energy level and capture cross section, and FIG. 4 is an example of measurement for a SiO2/Si-based MIS diode. 1... Cryostat, 2... MI
S diode, 3...Standard capacity, 4...
・Differential measurement type capacitance meter, 5...Square wave generator, 6
... Feedback type DC power supply, 7 ... Boxcar averager, 8 ... Thermocouple, 9 ...
... Linearizer 10 ... Divider, 11.
...X-Y recorder.

Claims (1)

【特許請求の範囲】[Claims] 1 金属−絶縁膜−半導体(MIS)ダイオードの高周
波容量の方形波過度応答を少なくとも2つのサンプリン
グ時間t_1、t_2における容量の差で評価し、この
容量差の温度掃引より絶縁膜−半導体界面の界面準位を
測定するにあたり、サンプリング時間t_1もしくはt
_2ににおける高周波容量を温度掃引中一定にするよう
に容量測定中に金属電極に印加しているバイアス電圧に
帰還をかけることを特徴とする界面準位測定法。
1. Evaluate the square wave transient response of the high-frequency capacitance of a metal-insulating film-semiconductor (MIS) diode by the difference in capacitance at at least two sampling times t_1 and t_2, and use the temperature sweep of this capacitance difference to determine the interface of the insulating film-semiconductor interface. When measuring the level, sampling time t_1 or t
An interface state measurement method characterized by applying feedback to a bias voltage applied to a metal electrode during capacitance measurement so as to keep the high frequency capacitance at _2 constant during a temperature sweep.
JP14000978A 1978-11-14 1978-11-14 Method for measuring electrical characteristics of defects at the interface between insulating films and semiconductors Expired JPS59130B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14000978A JPS59130B2 (en) 1978-11-14 1978-11-14 Method for measuring electrical characteristics of defects at the interface between insulating films and semiconductors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14000978A JPS59130B2 (en) 1978-11-14 1978-11-14 Method for measuring electrical characteristics of defects at the interface between insulating films and semiconductors

Publications (2)

Publication Number Publication Date
JPS5567147A JPS5567147A (en) 1980-05-21
JPS59130B2 true JPS59130B2 (en) 1984-01-05

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Application Number Title Priority Date Filing Date
JP14000978A Expired JPS59130B2 (en) 1978-11-14 1978-11-14 Method for measuring electrical characteristics of defects at the interface between insulating films and semiconductors

Country Status (1)

Country Link
JP (1) JPS59130B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0622259B2 (en) * 1982-07-28 1994-03-23 富士通株式会社 Interfacial electrical conductivity evaluation method

Also Published As

Publication number Publication date
JPS5567147A (en) 1980-05-21

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