JPS5914825B2 - Memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a method for sending read/write activation signals of a memory device.

Conventionally, to start reading or writing, the logical product of the device designation signal and the address flag signal indicating the timing for establishing address information is used to start the signal, and in the case of writing, a certain timing is taken from this start signal, and the data information is It controlled the timing of intake.

This system requires a circuit to create the timing as described above during writing, and has the disadvantage that the timing circuit must be changed if the timing at which the data flag signal is sent is changed. An object of the present invention is to provide a memory control method that eliminates the drawbacks of the prior art and reduces the amount of hardware.

The present invention enables processing to be performed by simply providing a simple AND circuit and a logical sum circuit, and the activation timing for reading is activated when an address flag signal is received, and the activation timing for writing is activated when a data flag signal is received. This is what I did.

The present invention will be explained in detail below using the figures.

FIG. 1 is a block diagram of a specific embodiment of the present invention, FIG. 2 shows a time chart for reading, and FIG. 3 shows a time chart for writing.

Here, 16 with column (row) and mouth (column) designation signals.
, 384×1 bit IC memory element 17 is used. 1 is a device designation signal sent from a central control unit (hereinafter referred to as CC) when accessing a storage device; 2 is a flip-flop 63 that holds the information until the end of the reading or writing operation; 4 is an address flag signal; 1 is a read designation signal, 5 is a data flag signal, 6 is a write designation signal, 7 is a logical bond circuit that can take an AND condition when reading, 8 is an AND circuit that can take an AND condition when writing, 9 is an OR circuit, 10 is the address information soft BOO sent from the CC.
~MABl3), 20 is a flip-flop for holding the address information, 11 is a timing circuit for creating the timing necessary for the operation of the storage device, 12 is a column designation timing signal for the IC memory element 17, 13 is a low designation timing signal, and 14 is a Write enable signal, 15 is write data information sent from CC, 21 is a flip-flop for holding the data information, 16 is read data from the memory element, 18 is 14-bit address information (MABOO-2M
A multiplex circuit divides ABl3) into two times and sends it to the IC memory element 17, 22 is a timing for the nuclear multiplex circuit, and 19 is an answer flag signal.

Next, the operation of the circuit shown in FIG. 1 will be explained using FIGS. 2 and 3.

First, in the case of reading (see the time chart in FIG. 2), a read designation signal 4 and address information 10 are sent to the storage device at the same time as the device designation signal 1.

Furthermore, when the address flag signal 3 indicating the establishment timing of the address information 10 is sent out, the logic of the AND circuit 7 is cleared, and the signal passes through the OR circuit 9 to activate the timing circuit 11. The timing circuit 11 first generates a low designation timing signal 13 that designates the memory element 17 low;
Of the 14-bit address information 10 that has already been input, the contents of 7 bits selected by the multiplex circuit 18 are taken in as input information, and then this memory element 1 is
A column designation signal 12 for specifying a column is generated after a certain timing specified in 7. At this time, the content of the multiplex circuit output switched by the multiplex circuit timing 22 is taken in as column information. The memory element 17 then receives a timing T defined for that element.
The read data 16 is output to O, and the answer flag signal 19 indicating the establishment timing is sent out, and the read operation is completed. Next, in the case of writing (see the time chart in Figure 3), at the same time as device designation signal 1, write designation signal 6,
Address information 10 is sent to the storage device side.

At this time, the address flag signal 3 is sent out, but since the write is specified, the AND condition of the AND circuit 7 cannot be satisfied, and the timing circuit 11 is not activated. Furthermore, write data information 1
5, and a data flag signal 5 which informs the timing of establishment of the data, the logic of the logic bond circuit 8 is cleared and the signal passes through the OR circuit 9 to start the timing 11.
Thereafter, column information and column information are generated at appropriate timings and addresses are specified, as in the case of reading. Further, a write enable signal 14 is sent out at an appropriate timing defined by the memory element 17. At this timing, the memory element 17 stores the write data information, sends out the answer flag signal 19, and the write cycle ends. As described above, if the present invention is implemented, writing can be started using the data flag signal as timing, so there is no need for a timing circuit to create a time period in the storage device from sending out address data to sending out write data. Even if the time from data transmission to write data transmission changes, there is no need to change the timing circuit as in the past.
It has a highly versatile configuration that can reduce the amount of hardware and at the same time accommodate changes in timing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a memory cape circuit embodying the present invention, and FIGS. 2 and 3 are time charts showing the operation of the circuit shown in FIG. 1 during reading and writing. . 1... Device designation signal, 2, 20, 21...
...Flip-flop, 3...Address flag signal, 4...Read designation signal, 5...
Data flag signal, 6...Write designation signal, 7
, 8...AND circuit, 9...OR circuit, 10...address information, 11...
Timing circuit, 12... Column specification timing signal, 13... Row specification timing signal, 1
4...Write enable signal, 15...
・Write data information, 16...Read data, 1
8...Multiplex circuit, 19...
Unsuff flag signal, 22...timing for multiplex circuit.

Claims (1)

[Claims] 1. Read or read information by sending an address flag signal and a data flag signal, which are sampling signals that instruct the establishment timing of a device designation signal, address information, data information, and the address and data 2 information, from the central control unit to the storage device. In a data processing device that executes writing, the storage device includes a device designation signal holding circuit, an AND circuit to which an address flag signal and a read designation signal are connected, and a device designation signal holding circuit, a data flag signal, and a write designation signal connected to each other. Means consisting of an AND circuit connected and an OR circuit connected to the two AND circuits is provided, and the operation starts when an address flag signal is received for reading and when an address flag signal is received for writing. A memory control method characterized in that processing is performed using timing when a data flag signal is received.