JPS5914907B2 - Bidirectional negative resistance semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an internal structure of a bipolar negative resistance semiconductor device having good electrical characteristics.

The structure of a conventional bipolar negative resistance semiconductor element was a planar type in which the surface was covered with an oxide film or the like as shown in FIG. 1a.

The operation in this case can be described as an open base operation of an NPN (or PNP) transistor. That is, N.P.
If the external current carrying rate of the N transistor is α, and in particular α at small current is αo, then the voltage corresponding to the breakover voltages V1 and V2 shown in Fig. 2 is VB, and the lowest value after entering the negative resistance region. When the voltage at a point is Vc, it is generally known experimentally that there is a relationship of VC=VBnN/1-αo.

If a voltage exceeding VB is applied to the element,
As shown in Figure 1b, the current begins to flow rapidly, but as the current increases and 10α approaches 1, the terminal voltage becomes V
It becomes smaller than B, exhibiting negative resistance characteristics, and α reaches 1, resulting in VC of the above formula. In order to make the above-mentioned negative resistance characteristics easier to use, it has conventionally been done to increase the emitter emission efficiency γ and the base transport efficiency β of the transistor.

In other words, the emitter-base impurity concentration difference is increased to increase γ, the width of the base layer is narrowed to increase β, and the time time of minority carriers injected into the base layer is lengthened. has been commonly practiced.
In the conventional structure shown in FIG. 1, the width w of the base is actually about 10 to 30 microns, and this must be controlled with high precision. Also, for the purpose of cost reduction,
When the diameter of the wafer is increased, handling during the process25
In order to prevent cracks caused by carelessness, the thickness of the wafer must be at least about 150 microns, so the depth of the junction portion is 60 to 70 microns.
In such deep diffusion, the variation in the depth 30 of the junction becomes large, and the diffusion at high temperatures for a long period of time causes problems such as disturbance of the crystals of the substrate, resulting in a reduction in the lifetime of minority carriers, which causes many problems in manufacturing. accompanied by difficulties.

On the other hand, one way to lengthen the lifetime of minority carriers is to increase the resistivity of the substrate used, but this method also increases the breakdown voltage of the device, which causes various problems in practical applications. It's coming. Therefore, in order to lower the voltage, it is necessary to make the depth of the N layer shallower and make the impurity concentration gradient steeper. However, doing so would create a contradiction in that the width of the base would have to be made wider. In addition, in the element having the structure shown in FIG. 1, which has an N emitter layer 2 formed by diffusing N type impurities from both sides of a P type substrate 1, the portion where the junction is exposed on the surface of the substrate is covered with a silicon oxide film 4 or the like. However, the lateral force direction diffusion in this part is slower than in the vertical direction, and the impurity concentration gradient at the surface is steeper than in the center, and near the surface, due to crystal disturbance due to silicon oxide film, etc. Sporadic breakdown occurs, making it difficult to obtain an element with uniform characteristics and highly reliable negative resistance characteristics.

The present invention is intended to improve the various drawbacks mentioned above and to provide a bipolar negative resistance semiconductor element that is easy to manufacture and has highly reliable negative resistance characteristics.

Next, the basic principle of the present invention will be explained.

As mentioned above, in order to increase the transport efficiency β, it is desirable that fewer minority carriers recombine in the base layer. For this reason, as mentioned above, a high resistivity semiconductor substrate is used in order to extend the lifetime of the base layer. Therefore, if the resistivity of the semiconductor substrate is high, as a practical matter, recombination of minority carriers will be small even if the width of one layer of the base P is considerably wide. In the present invention, the difference from the conventional structure is that the high resistivity base P
A local p+ region having the same conductivity type as the P layer and a higher impurity concentration than the P layer is provided in the central part of the part in contact with the emitter N layer, especially excluding the peripheral area, and this p+ region and the emitter layer are The point is that the junction formed by the high resistivity semiconductor base P layer and the emitter diffusion layer is arranged outside the periphery of the junction between the layers.

When an N layer having a conductivity type opposite to that of the base P layer is further diffused on top of this thin p+ region, the breakdown voltage of the junction generated by the base P layer and the N layer is equal to that of the junction generated by the p+ layer and the N layer. Since the breakdown voltage is higher than the breakdown voltage of the element, the breakdown voltage of the element is determined not by the surface but by the juncture caused by the internal p+ layer and N+ layer. Therefore, the N layer,
By appropriately selecting the dimensions of the p+ layer, the breakdown characteristics of the device can be determined. Therefore, the region where minority carriers recombine is mostly in the p+ layer and the base p
In a single layer, minority carriers pass through without recombining, so the width of the base P layer can be made considerably wider. Next, embodiments of the present invention will be described using the drawings. Second
As shown in figure a, thickness 250 microns, specific resistance 5-10
An oxide film 4 is formed on both sides of a P-type silicon semiconductor substrate 1 of 0.0 nm by thermal oxidation. Next, by known optical means, p+
The oxide layer in this area is removed in order to diffuse layers 7 and 8. From here, diffusion is performed using boron as an impurity source to a depth of 30 microns. After that, an oxide film is applied to this substrate again, and the oxide film on the parts that should become N layers 2 and 3 is removed by optical means as before, and phosphorus is diffused from there as an impurity source to a depth of 15 microns. . Electrodes 5 and 6 are respectively provided on this to form one element. The width of the P layer 1 (high resistivity base layer) left on the semiconductor substrate 1 of the device thus obtained is about 230 microns, and the thickness of the N layers 2, 3 and the P+ layers 7, 8 is 15 microns each. micron and 30 micron.

Therefore, the width of the base layer is several times that of the element with the conventional structure, and the depth of the N layer is about 1/4, so the accuracy of the diffusion depth is improved and the structure is easy to manufacture. can do. Also, in this case, the breakdown voltage of the element is
.

The p-layer 1 is in a high resistivity region, and the transport efficiency of minority carriers is very good, and the transport efficiency β of the transistor has almost no relation to the thickness w of this base layer, and is mainly affected by the width of the p+ layer. . Therefore, there is no need to make the width of P layer 1 narrower in order to increase β, so the thickness of substrate 1 can be reduced to 25 mm.
It can be as large as about 0 microns. Figure 2 b is a
The characteristics of the element shown in the figure are improved compared to the characteristics shown in FIG.

FIG. 3 shows an example in which the present invention is applied to an element having a horizontal structure obtained by performing impurity diffusion from only one surface. It is convenient to assemble this element on the substrate surface because it is taken out only on the surface of the substrate.

The basic operating characteristics are naturally the same as those in FIG. 4 shows a vertical structure having a pair of upper and lower electrodes 5 and 6 as in FIG. 2, but the joint end is exposed on the side surface and protected by an insulating protective film 9. This is an example in which the present invention is applied to a so-called mesa structure, and as compared with the planar structure shown in FIG. 2, there are fewer defects at the surface bonding edge, so the yield of non-defective products is somewhat improved. In this way, by using the structure of the present invention, there is no need to accurately control the base width w, and since a thick semiconductor substrate is used, cracks during the process are reduced, and because shallow diffusion is performed, the diffusion time is shortened. It has many advantages such as improved reliability because breakdown does not occur on the element surface, making it easier to manufacture and making it possible to obtain elements with good and highly reliable negative resistance characteristics. .

In the above embodiment, an element having an NPN structure in which an N-conductivity type emitter layer is arranged on a P-conductivity type base layer has been described, but it goes without saying that the present invention can also be applied to an element having the opposite PNP structure.

[Brief explanation of the drawing]

FIG. 1A is a sectional view of a conventional Brehner type negative resistance element, and FIG. 1B is a characteristic curve diagram thereof. FIG. 2a is a sectional view of a bidirectional negative resistance semiconductor device according to the present invention, and FIG. 2b is a characteristic curve diagram thereof. FIG. 3 is a cross-sectional view of an embodiment of the present invention having a horizontal structure, and FIG. 4 is a cross-sectional view of an embodiment of the present invention having a mesa-shaped structure. 1... P-type high specific resistance substrate (base layer), 2, 3... Emitter layer, 4
......Silicon oxide film, 5,6...Electrode, 7,8...Local low resistivity base layer, 9.
...Insulating protective film.

Claims (1)

[Claims] 1 A high-resistivity base layer of P (or N) conductivity type, and a pair of N (or P) conductivity type emitter layers with this base layer in between, and a central portion of both emitter layers excluding the peripheral portions. The base layer portion in contact with the
) A junction between a conductivity type layer and a low resistivity P (or N) conductivity type layer, further a high resistivity base layer is interposed between the low resistivity layers, and the peripheral junction is A bidirectional negative resistance semiconductor device comprising a junction between an N (or P) conductivity type layer and a high specific resistance P (or N) conductivity type base layer.