JPS5915184B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5915184B2 JPS5915184B2 JP51041478A JP4147876A JPS5915184B2 JP S5915184 B2 JPS5915184 B2 JP S5915184B2 JP 51041478 A JP51041478 A JP 51041478A JP 4147876 A JP4147876 A JP 4147876A JP S5915184 B2 JPS5915184 B2 JP S5915184B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- emitter
- film
- substrate
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は、一低いベース抵抗が得られる半導体装置の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device that provides a lower base resistance.
現在、集積回路においてはベース外部抵抗rBが非常に
問題になつている。At present, the base external resistance rB has become a serious problem in integrated circuits.
ベース抵抗rBは、拡散型トランジスタを考えた場合第
1図に示すようにエミッタ7からベースコンタクト部分
2aに至るまでの拡散層の抵抗である。なおこの図で1
は半導体基板でコレクタとなわ、2はベース、3はSi
O2からなる絶縁膜、4はポリシリコン膜、5はエミッ
タ電極、6はベース電極である。ベース抵抗が大である
とトランジスタの高速動作が制限される等の不都合があ
るので、これを小にすることが望まれる。ベース抵抗r
Bを小にするにはベースの不純物濃度を高め、ベース断
面積を大に5 する等の手段が考えられるが、エミッタ
T直下の能動ベース領域まで不純物濃度を高くするとエ
ミッタ注入効率が低下するし、その厚さを大とするとベ
ース幅が大となつて高速動作が阻害される。ベース2を
複数の拡散領域で構成してもよいが、10工程が複雑化
し集積度も低下するばかヤか、マスク合せ誤差を生じる
とベース抵抗rB低下の効果も薄れる。そこで本発明は
セルフアラインで能動ベース領域以外のベース断面積を
大にする、つまりエミッタTとコレクタ1との間に挾ま
れてベー15スとして働らく部分とベースコンタクト部
分2aとの接続導体の役割を果すA部分を深くしてベー
ス抵抗rBを小にしようとするものである。本発明の半
導体装置の製造方法は、半導体基板にほう素をP型とし
てベース拡散を行ない、該基20板表面に絶縁膜を被着
したのちこれをパターニングしてエミッタ窓をあけ、次
いでポリシリコン膜を成長させ、その後該ポリシリコン
膜を酸化して該膜が基板と接するベース層部分の底部を
盛上らせ、然るのち前記エミッタ窓を通してエミッタ拡
25散を行なうことを特徴とするが、次に実施例を参照
しながらこれを詳細に説明する。第2図に示すように本
発明ではN型シリコン半導体基板1を用い、その表面に
形成した熱酸化SiO2膜3にベース窓をあけ、ほう素
BをP型30不純物としてベース拡散を行ない、ベース
層2を形成する。When considering a diffused transistor, the base resistance rB is the resistance of the diffusion layer from the emitter 7 to the base contact portion 2a, as shown in FIG. In this figure, 1
is a semiconductor substrate with a collector and rope, 2 is a base, and 3 is Si
An insulating film made of O2, 4 a polysilicon film, 5 an emitter electrode, and 6 a base electrode. If the base resistance is large, there are disadvantages such as limiting high-speed operation of the transistor, so it is desirable to reduce this resistance. base resistance r
In order to reduce B, it is possible to increase the impurity concentration in the base and increase the cross-sectional area of the base, but if the impurity concentration is increased to the active base region directly under the emitter T, the emitter injection efficiency will decrease. , if the thickness is increased, the base width becomes larger, which impedes high-speed operation. The base 2 may be composed of a plurality of diffusion regions, but this will complicate the 10 steps and reduce the degree of integration, and if mask alignment errors occur, the effect of lowering the base resistance rB will be diminished. Therefore, the present invention uses self-alignment to increase the cross-sectional area of the base other than the active base region, that is, the connecting conductor between the portion sandwiched between the emitter T and collector 1 and serving as the base 15 and the base contact portion 2a. The aim is to make the base resistance rB smaller by deepening the portion A that plays a role. The method for manufacturing a semiconductor device of the present invention is to perform base diffusion of P-type boron on a semiconductor substrate, deposit an insulating film on the surface of the substrate 20, pattern it to form an emitter window, and then use polysilicon to form an emitter window. The method is characterized in that a film is grown, and then the polysilicon film is oxidized to bulge the bottom of the base layer portion where the film contacts the substrate, and then emitter diffusion is performed through the emitter window. , which will now be explained in detail with reference to examples. As shown in FIG. 2, in the present invention, an N-type silicon semiconductor substrate 1 is used, a base window is opened in a thermally oxidized SiO2 film 3 formed on its surface, and a base is diffused using boron B as a P-type 30 impurity. Form layer 2.
次に全面CVD法によりSiO2膜11を成長させ、か
つこれをパターニングし、エミッタ窓Ilaおよびベー
スコンタクト窓11bをあける。更に全面にポリシリコ
ン膜12を成長35させるが、このポリシリコンには不
純物はドープしない。次に1000℃程度の酸化性雰囲
気においてポりシリコン膜12を酸化する。Next, a SiO2 film 11 is grown by CVD on the entire surface and patterned to form an emitter window Ila and a base contact window 11b. Furthermore, a polysilicon film 12 is grown 35 over the entire surface, but this polysilicon is not doped with impurities. Next, the polysilicon film 12 is oxidized in an oxidizing atmosphere at about 1000°C.
この結果、膜12は表面側から酸化してSiO2になシ
、この過程でポリシリコン膜12が接触する基板部分つ
まジベース層部分の不純物のほう素がポリシリコン膜側
に吸い寄せられてゆく。SiO2膜3、11へもほう素
は若干吸い取られるが、このほう素の吸い取り効果はシ
リコンが酸化されてSiO2になる過程で著しいのに対
し、酸化が進行しないときはSiO2膜へのほう素の吸
い取りは僅少なので両者には大きな差が生じる。As a result, the film 12 is oxidized to SiO2 from the surface side, and in this process, impurity boron in the substrate portion or the base layer portion with which the polysilicon film 12 comes into contact is attracted to the polysilicon film side. A small amount of boron is also absorbed into the SiO2 films 3 and 11, but this effect of absorbing boron is remarkable during the process in which silicon is oxidized to become SiO2, whereas when oxidation does not progress, boron is absorbed into the SiO2 film. There is a big difference between the two since the amount of absorption is small.
この酸化のための熱処理でベース層2のほう素は基板深
く拡散してゆき、ベース層は拡がるが、エミツタ窓11
a訃よびベースコンタクト窓11bの下部のベース層2
は、ポリシリコン膜へのほう素の吸い取v効果によりそ
の拡がり速度が極めて遅くなり、図示のようにベース層
下部は凹凸状になる。エミツタ窓訃よびベースコンタク
ト窓形成のための絶縁膜11をCVD法によ)被着させ
ると、この方法では低温処理が可能であるから、第2図
に示した工程でベース層2に拡散した不純物のほ素が基
板内へ広く拡散するのを阻市し、第3図に示す形状のベ
ース層2の不純物濃度を高くする点で有効である。Through this heat treatment for oxidation, the boron in the base layer 2 is diffused deep into the substrate, and the base layer expands, but the emitter window 11
Base layer 2 below the base contact window 11b
In this case, the spreading speed becomes extremely slow due to the v effect of absorption of boron into the polysilicon film, and the lower part of the base layer becomes uneven as shown in the figure. When the insulating film 11 for forming the emitter window and the base contact window is deposited by the CVD method, since this method allows low-temperature processing, the insulating film 11 is diffused into the base layer 2 in the process shown in FIG. This is effective in preventing the diffusion of impurities into the substrate and increasing the impurity concentration in the base layer 2 having the shape shown in FIG.
またポリシリコン膜12の酸化は全体が酸化するまで行
なうと差が付き過ぎるので途中で停止するとよく、あと
に残つたポリシリコン膜12はベース短絡の阻止用に利
用できる。Furthermore, if the polysilicon film 12 is oxidized until the entire surface is oxidized, there will be too much difference, so it is better to stop halfway, and the remaining polysilicon film 12 can be used to prevent base short circuits.
即ち既知のように電極のアルミニウムは基板のシリコン
と共晶合金を作)易く、これがベース短絡などを招くが
、ポリシリコンを介在させるとこれを阻止することがで
きる。次にSiO2膜13はエツチングして除去し、全
面にN型不純物を含んだPSG膜を成長させ、これをパ
ターニングしてエミツタ窓11a部分のそれを残し、少
なくともベースコンタクト窓11b部分のそれを除去し
、か\ろ状態で熱処理してN型不純物を該PSG膜から
エミツタ窓を通してべ+ース層2へ拡散させ、第4図に
示すようにN型エミツタ層14を形成する。That is, as is known, the aluminum of the electrode tends to form a eutectic alloy with the silicon of the substrate, which leads to base short circuits, but this can be prevented by interposing polysilicon. Next, the SiO2 film 13 is removed by etching, a PSG film containing N-type impurities is grown on the entire surface, and this is patterned to leave the part of the emitter window 11a and remove at least that of the base contact window 11b. Then, the N-type impurity is diffused from the PSG film into the base layer 2 through the emitter window by heat treatment in a still state, thereby forming the N-type emitter layer 14 as shown in FIG.
然るのちPSG膜はエツチングして除去し、全面に電極
材料、通常はアルミニウムを蒸着し、これをパターニン
グしてエミツタ電極5}よびベース電極6を作る。ポリ
シリコン膜12も、これらの電極と基板との間のそれを
残して他の部分をエツチングして除去する。なお、コレ
クタコンタクト拡散層が必要なら、エミツタ層14形成
と全く同様にして同時に形成できる。この第4図から明
らかなようにエミツタ層14と盛D上つた基板コレクタ
部分1aとの間の有効ベース層部分2aと、ベース電極
6(工程説明は省略したがベース層2形成の際にベース
コンタク+卜拡散を行なつてこのベース電極の下部には
P型ベースコンタクト部分を作る)との間のベース層は
断面積が大きく、従つてベース抵抗RBは低くなる。Thereafter, the PSG film is removed by etching, and an electrode material, usually aluminum, is deposited on the entire surface and patterned to form an emitter electrode 5 and a base electrode 6. The polysilicon film 12 is also removed by etching except for the portion between these electrodes and the substrate. Incidentally, if a collector contact diffusion layer is required, it can be formed simultaneously with the formation of the emitter layer 14 in exactly the same manner. As is clear from FIG. 4, the effective base layer portion 2a between the emitter layer 14 and the substrate collector portion 1a on which the embankment The base layer between the base layer (contact + diffusion is performed to form a P-type base contact portion below this base electrode) has a large cross-sectional area, and therefore the base resistance RB is low.
しかも有効ベース層部分2aの不純物濃度は前述の説明
から明らかなように低いので、エミツタのキヤリヤ注人
効率が下るようなことはない。また、ベース電極6下に
予め高濃度のベースコンタクト拡散領域を形成して訃け
ば、エミツタ拡散の熱処理時にベースコンタクト拡散領
域からその上のポリシリコン膜へ不純物が拡散し−C低
比抵抗化し良好なコンタクトが得られる。な卦、ほう素
を拡散した半導体基板表面の一部をCVDSiO2膜で
覆い、他の部分をポリシリコン膜で覆い、か\る状態で
熱処理してポリシリコン膜を酸化させた所、ポリシリコ
ン膜の下部半導体基板の不純物(ほう素)濃度はSiO
2膜の下部のそれに比べて約半分に下b1ほう素による
P型領域の深さには10〜30%の差が認められた。Moreover, since the impurity concentration in the effective base layer portion 2a is low as is clear from the above explanation, the carrier injection efficiency of the emitter does not decrease. Furthermore, if a highly concentrated base contact diffusion region is formed in advance under the base electrode 6, impurities will be diffused from the base contact diffusion region into the polysilicon film above it during heat treatment for emitter diffusion, resulting in a low -C resistivity. Good contact can be obtained. By the way, part of the surface of the semiconductor substrate with boron diffused was covered with a CVDSiO2 film, the other part was covered with a polysilicon film, and the polysilicon film was oxidized by heat treatment in a cold state. The impurity (boron) concentration of the lower semiconductor substrate is SiO
A difference of 10 to 30% was observed in the depth of the P-type region due to lower b1 boron, which is approximately half that of the lower part of the two films.
以上詳細に説明したように本発明によれば、ベース抵抗
RBをエミツタに依存しない独立の低い値にすることが
できる。As described above in detail, according to the present invention, the base resistance RB can be set to an independent low value that does not depend on the emitter.
というのは従来は所定のベース幅と注人効率を持つよう
にエミツタを形成するためにベース抵抗RBの低減に限
界があつたが、本発明ではベース領域を図示した如く変
形するので、その凹凸程度を変えることによねか\る制
約から免かれることができる。This is because in the past, there was a limit to the reduction of the base resistance RB because the emitter was formed to have a predetermined base width and pouring efficiency, but in the present invention, the base region is deformed as shown in the figure, so the unevenness can be reduced. By changing the degree, one can be freed from certain constraints.
第1図はベース抵抗の説明図、第2図〜第4図は本発明
の製造方法を説明する工程図である。FIG. 1 is an explanatory diagram of a base resistor, and FIGS. 2 to 4 are process diagrams illustrating the manufacturing method of the present invention.
Claims (1)
を行い、該基板表面に絶縁膜を被着したのちこれをパタ
ーニングしてエミッタ窓をあけ、次いでポリシリコン膜
を成長させ、その後該ポリシリコン膜を酸化して該膜が
基板と接するベース層部分の底部を盛上らせ、然るのち
前記エミッタ窓を通してエミッタ拡散を行なうことを特
徴とする半導体装置の製造方法。 2 絶縁膜としてCVD法により成長させたSiO_2
膜を用い、エミッタ拡散に不純物をドープしたPSC膜
を用いることを特徴とした特許請求範囲第1項記載の半
導体装置の製造方法。[Claims] 1 Base diffusion is performed on a semiconductor substrate using boron as a P-type impurity, an insulating film is deposited on the surface of the substrate, and an emitter window is formed by patterning this, and then a polysilicon film is grown. . A method of manufacturing a semiconductor device, comprising: oxidizing the polysilicon film to bulge the bottom of the base layer portion where the film contacts the substrate; and then performing emitter diffusion through the emitter window. 2 SiO_2 grown by CVD method as an insulating film
2. The method of manufacturing a semiconductor device according to claim 1, wherein a PSC film doped with impurities is used for emitter diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51041478A JPS5915184B2 (en) | 1976-04-13 | 1976-04-13 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51041478A JPS5915184B2 (en) | 1976-04-13 | 1976-04-13 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52124875A JPS52124875A (en) | 1977-10-20 |
| JPS5915184B2 true JPS5915184B2 (en) | 1984-04-07 |
Family
ID=12609449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51041478A Expired JPS5915184B2 (en) | 1976-04-13 | 1976-04-13 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5915184B2 (en) |
-
1976
- 1976-04-13 JP JP51041478A patent/JPS5915184B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52124875A (en) | 1977-10-20 |
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