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JPS5917542B2 - Hermetically sealed assembly method for semiconductor devices - Google Patents
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JPS5917542B2 - Hermetically sealed assembly method for semiconductor devices - Google Patents

Hermetically sealed assembly method for semiconductor devices

Info

Publication number
JPS5917542B2
JPS5917542B2 JP50035065A JP3506575A JPS5917542B2 JP S5917542 B2 JPS5917542 B2 JP S5917542B2 JP 50035065 A JP50035065 A JP 50035065A JP 3506575 A JP3506575 A JP 3506575A JP S5917542 B2 JPS5917542 B2 JP S5917542B2
Authority
JP
Japan
Prior art keywords
semiconductor element
metal
hermetically sealed
semiconductor
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50035065A
Other languages
Japanese (ja)
Other versions
JPS51110269A (en
Inventor
英二 萩本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP50035065A priority Critical patent/JPS5917542B2/en
Publication of JPS51110269A publication Critical patent/JPS51110269A/en
Publication of JPS5917542B2 publication Critical patent/JPS5917542B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K5/00Casings, cabinets or drawers for electric apparatus
    • H05K5/06Hermetically-sealed casings
    • H05K5/069Other details of the casing, e.g. wall structure, passage for a connector, a cable, a shaft

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の気密封止組立方法に関し、特に大
規模集積回路に適用して効果のあるものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hermetically sealed assembly method for semiconductor devices, and is particularly effective when applied to large-scale integrated circuits.

半導体素子の大きさは、とわ分け大規模集積回路用素子
に見られるごとく、その機能の上昇および製造技術の向
上により次第に大形化する傾向がある。
2. Description of the Related Art The size of semiconductor devices tends to gradually increase due to improvements in their functionality and manufacturing technology, as seen in devices for large-scale integrated circuits.

しかし一方これを収納するセラミック容器の大きさの方
は、互換性その他作業性を考え特殊な場合を除き形状寸
法が規格化されているので、気密性を確実ならしめるた
めにとられた規定巾のシール部分を除〈と、残る半導体
素子を載置すべきアイランド部分の大きさは当然その上
限寸法を制限され、寸法形状の大きな半導体素子をマウ
ントしようとする場合に問題が生ずる。通常金属板上に
半導体素子をマウントするには金属板上にヌ Auメッ
キを施し、Au−Si合金またはAu一Sn合金等をロ
ウ材として用い、半導体素子のSi材との間に合金化反
応を生ぜしめる方法が利用されている。このマウント方
法は半導体素子とアイランド部分の金属材、例えばコバ
ールに対しroて熱膨張率が近いこと、ぬれ性がよいこ
となどからマウント後の半導体素子の剥離、または破損
などの不良発生が少く、すぐれたマウント方法である。
しかしこの合金化反応は用いる金属ないし合金に5の融
点以上に温度を上げるだけでは容易には起らず、同時に
機械的振動を付加することが必要とされている。
However, the size of the ceramic container used to store it is standardized, except in special cases, for reasons of compatibility and workability. When the seal portion is removed, the size of the remaining island portion on which the semiconductor element is to be placed is naturally limited by its upper limit, which causes problems when attempting to mount a large-sized semiconductor element. Normally, in order to mount a semiconductor element on a metal plate, the metal plate is plated with Au, and an alloying reaction occurs between it and the Si material of the semiconductor element, using Au-Si alloy or Au-Sn alloy as a brazing material. A method is used to generate This mounting method is less likely to cause defects such as peeling or damage of the semiconductor element after mounting because the metal material of the semiconductor element and the island part, such as Kovar, has a coefficient of thermal expansion similar to that of RO and has good wettability. This is an excellent mounting method.
However, this alloying reaction cannot easily occur simply by raising the temperature of the metal or alloy used above the melting point of 5, and it is necessary to simultaneously apply mechanical vibrations.

従つてセラミック壁部材の内径を最大限にまで広げたメ
タライズ層で形成されるアイランド部分−杯に大きな半
導体素子をマウントする■0場合には、合金化反応を生
ぜしめることができない。この場合半導体素子をコバー
ルのような金属板上に予めマウントしておき、この金属
板ごとアイランド部分に接着する便法が用いられること
がある力ζ Auメッキを施したコバール板等を新た■
5 に必要とする土、半導体素子を二度までも高温にさ
らすことになク半導体素子の機能に悪影響を及ぼすこと
は明らかである。また半導体素子の裏面に予めAuを蒸
着させ、極力小さな機械的振動で合金化反応を促進させ
よ30うとする試みもあるが、ウェハーからの素子歩留
りが悪いとかなクのコスト高となるので、あまク広くは
用いられない。
Therefore, when a large semiconductor element is mounted on the island portion formed by the metallized layer in which the inner diameter of the ceramic wall member is maximized, no alloying reaction can occur. In this case, an expedient method may be used in which the semiconductor element is mounted in advance on a metal plate such as Kovar, and the entire metal plate is glued to the island part.
It is clear that exposing semiconductor devices to high temperatures more than once will adversely affect the functionality of the semiconductor devices. There is also an attempt to pre-deposit Au on the back side of the semiconductor element and accelerate the alloying reaction with as little mechanical vibration as possible30, but this results in a poor yield of elements from the wafer and high costs. Not widely used.

本発明は上記の情況に鑑み、大型半導体素子に好適な気
密封止組立方法を提供しようとするもの五 で、アイラ
ンド部からの魚離または破損したりするマウント不良を
生ずることなく、アイランド部分面積一杯の大きさの半
導体素子を気密封止することができる。
In view of the above circumstances, the present invention aims to provide a hermetically sealed assembly method suitable for large-sized semiconductor devices, and is capable of reducing the area of the island portion without causing mounting defects such as detachment from the island portion or damage. A full-sized semiconductor device can be hermetically sealed.

以下実施例に基づき詳細に説明する。A detailed explanation will be given below based on examples.

第1図は本発明の一実施例図である。FIG. 1 is a diagram showing an embodiment of the present invention.

Auメツキを施したコバールのような金属片1に予め半
導体素子2をマウントして卦く。このマウント方法は、
素子に機械的振動を十分に与えることができるのでAu
−Si,Au−Sn等の合金ロウ材を用いた合金反応法
を直接禾用することができる。このようにして金属片1
にマウントされた半導体素子2は、セラミツク壁部材3
卦よび4で積層に構成され外部リード線5を具えたセラ
ミツク容器に矢印方向から挿入され、上記壁部材4の端
面にメタライズ層を介してロウ付されたウエルドリング
6と金属片1とがシ一4接される。この際シーム溶接に
代えてレーザー溶接、電子ビーム溶接等の局部的加熱手
段の利用も可能である。またウエルドリング6の代りに
設けたwメタライズ層+Niメツキ層+Auメツキ層で
構成されるようなAuメツキ層と、金属片1上に半導体
素子2を予めマウントする際金属片1の表面の全面また
は少くとも気密封止部分まで流したAu−Sn合金、A
u−Si合金ロウ材とを接触させ、レーザー光線または
電子ビームの局部照射によつて生ずる合金化反応を利用
して金属片の封着を行なうこともできる。
A semiconductor element 2 is mounted in advance on a metal piece 1 such as Kovar plated with Au. This mounting method is
Since it is possible to apply sufficient mechanical vibration to the element, Au
An alloy reaction method using alloy brazing materials such as -Si, Au-Sn, etc. can be directly applied. In this way, metal piece 1
The semiconductor device 2 mounted on the ceramic wall member 3
A weld ring 6 and a metal piece 1 are inserted from the direction of the arrow into a ceramic container having a laminated structure of cubes and 4 and equipped with an external lead wire 5, and are brazed to the end face of the wall member 4 via a metallized layer. 14 times. At this time, instead of seam welding, it is also possible to use local heating means such as laser welding and electron beam welding. In addition, when the semiconductor element 2 is mounted on the metal piece 1 in advance, the entire surface of the metal piece 1 or Au-Sn alloy flowed to at least the hermetically sealed part, A
It is also possible to seal the metal pieces by bringing them into contact with a u-Si alloy brazing material and utilizing an alloying reaction caused by local irradiation with a laser beam or an electron beam.

第2図は上記本発明方法によつて得られた半導体装置の
一例を示す断面図である。
FIG. 2 is a cross-sectional view showing an example of a semiconductor device obtained by the method of the present invention.

本発明の以後の組立工程は従来の組立方法と同じく、金
属細線8を用いて結線しウエルドリング7に金属キヤツ
ブ9をシーム溶接して気密封止とすればよく、もちろん
その他いかなる手段によつて気密封止することも本発明
の実施をさまたげるものではない。金属片1の形状は上
記実施例のように平板でもまたは第3図に示すごとく台
形状に変形しても実施できる。台形状のものは金属片1
の位置合せを容易にするばかシでなく、壁部材4のボン
ディング面と半導体素子2との段差を縮めることができ
るので金属細線8による結線作業を容易にする利点をも
zまた金属片の材質はコバールに限ることなくCu,N
i,Feの如き材質でもよい。その場合には半導体素子
2との熱膨張率その他の特性の相違を緩和するために、
コバール等の金属板を半導体素子との間に挿入してマウ
ントすることが好ましい。更に金属板1の接合に局部加
熱手段を用いることにより、大規模集積回路等の大型素
子を最小限の加熱工程を経るのみで組立ることができる
。また小型素子に対しても本発明が実施できることはき
わめて当然なことである。更に本発明は第4図に示す如
き金属片1にヒートシンク10を取り付ける場合に対し
有効な構造を与える。このヒートシンクの材質にはコバ
ールのような金属以外にベリリア等の熱伝導のよい材料
を自由に選択することができる。更にまた第5図のよう
に足11を設けてこれを所望の外部リードに接着できる
構造としたものは、接地ピンを自由に選ぶ場合に有効で
ある。この外部リード線との接着は公知のメタライズ層
を設ける手段を禾用できることはもちろんである。
The subsequent assembly process of the present invention can be carried out in the same way as in the conventional assembly method, by connecting the wires using thin metal wires 8 and seam-welding the metal cap 9 to the weld ring 7 to achieve an airtight seal, or of course, by any other means. Hermetic sealing also does not hinder the implementation of the present invention. The shape of the metal piece 1 can be a flat plate as in the above embodiment, or it can be deformed into a trapezoidal shape as shown in FIG. The trapezoidal one is metal piece 1
The material of the metal piece also has the advantage of making it easier to connect with the thin metal wire 8 because it reduces the level difference between the bonding surface of the wall member 4 and the semiconductor element 2. is not limited to Kovar, but also Cu, N
It may be made of materials such as i, Fe. In that case, in order to alleviate the difference in thermal expansion coefficient and other characteristics with the semiconductor element 2,
It is preferable to mount a metal plate such as Kovar or the like by inserting it between the semiconductor element and the semiconductor element. Furthermore, by using local heating means for joining the metal plates 1, large-scale elements such as large-scale integrated circuits can be assembled with a minimum number of heating steps. Furthermore, it is quite natural that the present invention can be implemented for small devices as well. Further, the present invention provides an effective structure for attaching a heat sink 10 to a metal piece 1 as shown in FIG. As the material of this heat sink, in addition to metals such as Kovar, materials with good thermal conductivity such as beryllia can be freely selected. Furthermore, a structure in which a leg 11 is provided and can be bonded to a desired external lead as shown in FIG. 5 is effective when the ground pin is freely selected. Of course, the adhesion to the external lead wire can be achieved by using a known means for providing a metallized layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例図、第2図は本発明によつて
得られた半導鉢装置の一惰示す断面図、第3図は本発明
にかかる半導体封着金属板の変形図、第4図卦よび第5
図は本発明の応用例図である。 1・・・・・・金属片、2・・・・・・半導体素子、3
,4・・・・・・セラミック壁部材、5・・一・・外部
リード線、6,7・・・・・・ウエルドリング、8・・
・・・・金属細線、9・・一・・金属キヤツプ、10・
・・・・・ヒートシンク、11・・一・・足。
FIG. 1 is an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor pot device obtained by the present invention, and FIG. 3 is a modification of the semiconductor-sealed metal plate according to the present invention. Figure, Figure 4 and Figure 5
The figure is an example of an application of the present invention. 1...Metal piece, 2...Semiconductor element, 3
, 4... Ceramic wall member, 5... External lead wire, 6, 7... Weld ring, 8...
...Metal thin wire, 9...1...Metal cap, 10.
...Heat sink, 11...1...foot.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体封着金属板に半導体素子を予め接着し、前記
半導体素子をセラミック容器のアイランド部に明けた半
導体素子が一杯に入る大きさの貫通孔に挿入すると共に
該貫通孔周囲に設けられた金属化層に前記金属板をあて
がつて局部気密封着し、次いで金属細線でボンディング
し、その後キャップをかぶせて気密封止することを特徴
とする半導体装置の気密封止組立方法。
1. A semiconductor element is bonded in advance to a semiconductor-sealing metal plate, and the semiconductor element is inserted into a through-hole in an island portion of a ceramic container that is large enough to fully accommodate the semiconductor element, and a metal provided around the through-hole is inserted. 1. A method for assembling a semiconductor device in an hermetically sealed manner, characterized in that the metal plate is applied to the chemical layer for local hermetically sealing, then bonding is performed with a thin metal wire, and then a cap is placed on the layer for hermetically sealing.
JP50035065A 1975-03-24 1975-03-24 Hermetically sealed assembly method for semiconductor devices Expired JPS5917542B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50035065A JPS5917542B2 (en) 1975-03-24 1975-03-24 Hermetically sealed assembly method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50035065A JPS5917542B2 (en) 1975-03-24 1975-03-24 Hermetically sealed assembly method for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS51110269A JPS51110269A (en) 1976-09-29
JPS5917542B2 true JPS5917542B2 (en) 1984-04-21

Family

ID=12431607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50035065A Expired JPS5917542B2 (en) 1975-03-24 1975-03-24 Hermetically sealed assembly method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5917542B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259572A (en) * 1975-11-12 1977-05-17 Hitachi Ltd Electronic circuit device
US4598308A (en) * 1984-04-02 1986-07-01 Burroughs Corporation Easily repairable, low cost, high speed electromechanical assembly of integrated circuit die
JPH0738421B2 (en) * 1986-02-07 1995-04-26 株式会社日立製作所 Package for semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5113616B2 (en) * 1972-04-14 1976-05-01

Also Published As

Publication number Publication date
JPS51110269A (en) 1976-09-29

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