JPS5923656B2 - PLL circuit synchronization judgment signal forming circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a PLL (phase-locked loop) circuit, in which:
The present invention relates to a circuit that detects when a signal input to the PLL circuit loop is phase-locked with a reference signal and sends out a synchronization determination signal.

When inputting a signal output from a previous stage to a subsequent stage, it is often necessary to input the signal in phase synchronization with a certain reference signal due to signal processing in the latter stage.

In such a case, a PLL circuit or the like is inserted between the previous stage and the signal output from the previous stage is configured so that it is phase synchronized with the reference signal in the PLL circuit and then input to the latter stage. be done. In a circuit configured in this way, it is necessary to prevent the signal output from the previous stage from being input to the subsequent stage until the signal is synchronized with the reference signal, and to allow the signal to be input to the subsequent stage at the time the signal is synchronized. For this purpose, PL
It becomes necessary to create a synchronization determination signal for detecting that the signal input to the loop of the L circuit is synchronized with the reference signal.

An object of the present invention is to provide a novel circuit for creating and transmitting the synchronization determination signal.

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing the configuration of an embodiment in which the present invention is implemented in a carrier synchronization circuit for a PSK signal necessary for receiving and demodulating a PSK (phase shift key ink) signal.
The figure is a diagram showing signal waveforms at the locations indicated by A to B in FIG. 1.

In Figure 1, 1 is a first frequency mixing circuit, 2 is a first local oscillation circuit, 3 is a second frequency mixing circuit, 4 is an intermediate frequency amplification circuit, 5 is a frequency multiplier circuit, and 6 is a frequency A discrimination circuit, T is a first filter, 8 is a first phase detection circuit, 9 is a loop filter, 10 is an OR circuit, 11 is a second
12 is a reference signal oscillation circuit, 13 is a first phase shift circuit, 14 is a synchronization determination signal forming circuit, 15 is a second filter, 16 is a synchronization determination signal sending circuit, IT
18 is a gate circuit, 18 is a PSK signal demodulation circuit, and in the synchronization determination signal forming circuit 14, 141 is a second phase shift circuit, 142 is a second phase detection circuit, and 143 is a third phase detection circuit. , 144 is a subtraction circuit.

In explaining the embodiments of the present invention, first, the operation of the carrier synchronization circuit for PSK signals will be explained.

As is well known, in a PSK signal transmitting device that PSK modulates a carrier using a PCM code and transmits the signal, the carrier serving as the center frequency disappears, and the PSK signal receiving device receives the PSK signal.
The K signal is transmitted by sidebands only.

Therefore, the PSK signal receiving device cannot properly demodulate the PSK signal unless it reproduces a signal that should have a center frequency based on the sideband waves and synchronizes with the PSK signal transmitting device. The main parts of the synchronization circuit with this PSK signal transmitter are as shown in FIG. 1, and the operation of the circuit will be explained below. When the PSK signal wirelessly transmitted from the PSK signal transmitter is received by the PSK signal receiver, it is first input to the first frequency mixing circuit 1 .

In the first frequency mixing circuit 1, the first local oscillation circuit 2
The frequency of the difference between the signal from and the received signal (e.g. 10.7
A first intermediate frequency signal 11F having a center frequency of MHZ) is generated, and the frequency of the difference between the first intermediate frequency signal 11F and the signal from the second local oscillation circuit 11 is further generated in the second frequency mixing circuit 3. A second intermediate frequency signal 21F having a center frequency of (for example, 455 KHZ) is generated. The second local oscillation circuit 11, which is the basis for the creation of the second intermediate frequency signal 21F by the second frequency mixing circuit 3, is an AFC circuit (
It is composed of a voltage controlled oscillator (so-called CO) whose output signal frequency is controlled by the signal flowing through the automatic frequency control circuit loop and the PLL circuit loop, and the second intermediate frequency signal 21F is finally The signal is phase-synchronized with the reference signal of the PLL circuit (signal from the reference signal oscillation circuit 12, which will be described later).

That is, the second frequency mixer output from the second frequency mixing circuit 3
The intermediate frequency signal 21F is amplified by the intermediate frequency amplifier circuit 4 and then input to the frequency multiplier circuit 5, where the frequency is multiplied by eight, for example. Therefore, when the center frequency of the second intermediate frequency signal 21F is 455 KHz, the center frequency of the output signal of the frequency multiplier 5 is 3.64 MHZ. By the frequency multiplication operation, the sideband energy of the PSK signal is concentrated in the vicinity of the center frequency, and the signal thus concentrated in the vicinity of the center frequency is input to the frequency discrimination circuit 6.

The frequency discrimination circuit 6 generates a voltage signal corresponding to the deviation of the signal from the center frequency, and this voltage signal is inputted to the second local oscillation circuit 11 via the first filter 7 and the OR circuit 10. Since the second local oscillation circuit 11 is composed of a VCO as described above, it controls the second intermediate frequency signal 21F based on the voltage signal. 2nd above
The intermediate frequency amplifier circuit 4, the frequency multiplier circuit 5, the frequency discrimination circuit 6, and the first filter 7
, the loop returning to the second frequency mixing circuit 3 via the OR circuit 10 and the second local oscillation circuit 11 constitutes an AFC circuit loop, and this AFC circuit loop is a circuit that performs frequency multiplication in the middle of the loop. A special A with inserted
This is an FC circuit loop, and by this loop, the second intermediate frequency signal 21F of the PSK signal has a center frequency (for example, 455
This is a signal whose frequencies are concentrated within a certain range near KHZ).

The range in which the frequencies are concentrated is controlled to be a synchronizable range of a PLL circuit loop (hereinafter referred to as a pull-in range), which will be described later.

By the way, the second frequency is output from the second frequency mixing circuit 3, passes through the intermediate frequency amplifier circuit 5, the first phase detection circuit 8, the loop filter 9, the OR circuit 10, and the second local oscillation circuit 11. The loop returning to the mixing circuit 3 constitutes a PLL circuit which uses a signal sent from the reference signal oscillation circuit 12 via the first phase shift circuit 13 as a reference signal for synchronization.

That is, the second intermediate frequency signal 21F whose frequency is controlled within the pull-in range of the PLL circuit by the AFC circuit loop is input to the first phase detection circuit 8, where it is input to the first phase shift circuit 13. Then, the phase difference with the reference signal from the reference signal oscillation circuit 12 which is input manually is detected. The first phase detection circuit 8 outputs a voltage signal according to this phase difference,
This voltage signal is input to the second local oscillation circuit 11 via the loop filter 9 and the OR circuit 10, and the oscillation frequency of the second local oscillation circuit 11 is controlled. Through the above operations, the second intermediate frequency signal 21F is finally synchronized with the reference signal sent from the reference signal oscillation circuit 12.
The frequency of the reference signal is (center frequency of the second intermediate frequency signal x frequency multiplication number in the frequency multiplier circuit 5), and as mentioned above, the center frequency of the second intermediate frequency signal is 455 KH.
Z, when the multiplication number of the frequency multiplier circuit 5 is 8 times, the oscillation frequency of the reference signal oscillation circuit 12 is 3.64 MHZ.
The outline of the operation of the carrier synchronization circuit for PSK signals has been described above. When the second intermediate frequency signal 21F output from this carrier synchronization circuit is synchronized with the reference signal, the signal is sent to the synchronization judgment signal forming circuit 14 at the time of synchronization. A synchronization determination signal is formed, and the synchronization determination signal is inputted to the synchronization determination signal sending circuit 16 through the second filter 15. Sends a synchronization determination signal. The gate circuit 17 is turned on by the synchronization determination signal, and the second intermediate frequency signal 21F synchronized with the reference signal is input to the PSK signal demodulation circuit 18. In the above operation, the circuit configuration of the synchronization determination signal forming circuit 14 is the main part of the present invention, and the synchronization determination signal forming circuit 14 will be described below.

The phase of the reference signal input to the first phase detection circuit 8 when the second intermediate frequency signal 21F is synchronized with the reference signal and the second intermediate frequency signal 21F (second intermediate frequency signal passed through the multiplier circuit 5). The phase, that is, the phase of the signal output to the port in FIG. 1 and the phase of the signal output to A in FIG. In the case of , the phase differs from each other by π/2.

That is, if the phase of the second intermediate frequency signal 21F is O phase, the phase of the reference signal is π/2 phase. By the way, in the present invention, in order to determine whether the phase of the second intermediate frequency signal 21F is synchronized with the phase of the reference signal, it is necessary to determine whether the reference signal and the second intermediate frequency signal 21F are in the same phase or differ by π phase. The synchronization determination signal forming circuit 14 detects that the synchronization determination signal is generated.

Therefore, the phase of the reference signal supplied from the reference signal oscillation circuit 12 to the synchronizing signal forming circuit 14 must be different from the phase of the reference signal supplied to the PLL circuit loop by π/2 phase. For this purpose, the signal from the reference signal oscillation circuit 12 is input to the first transfer circuit 13, where it is used as a reference signal in two directions whose phases differ from each other by π/2 phases,
One is input into the PLL circuit loop, and the other is input into the synchronization determination signal forming circuit 14, respectively. The reference signal input from the first phase shift circuit 13 to the synchronization determination signal forming circuit 14 is further passed to the second phase shift circuit 141, where one side is in phase with the reference signal and the other side is different from the reference signal by π phase. The second phase detection circuit 14 receives the reference signal in two directions.
The signal is input to the second and third phase detection circuits 143.

Therefore, when the second intermediate frequency signal 21F is synchronized with the reference signal, the two signals input to the second phase detection circuit 142 are in phase, and the two signals input to the third phase detection circuit 143 are in phase. The phases of the signals differ from each other by π phase. The relationship between the signal waveforms at two points A to A in this state is shown in part A in FIG. By the way, until the PLL circuit enters the phase synchronization state, the phase of the second intermediate frequency signal 21F outputted to A and the phase of the reference signal outputted to C and 2 are not in phase or have a phase difference of π phase. First, the signals are placed in a bead state due to the difference in frequency, and the outputs of the second phase detection circuit 142 and the third phase detection circuit 143 are zero. When the PLL circuit enters the phase synchronization state, the 0 phase (0 phase) of the second intermediate frequency signal 21F (
In the second intermediate frequency signal 21F) which has not undergone phase shift, the second intermediate frequency signal 21 outputted to A
The reference signals outputted to F and C are in phase with each other, and the second intermediate frequency signal 21F outputted to A and the reference signal outputted to A are different in phase by π phase. The second phase detection circuit 142 and the third phase detection circuit 143 each independently output DC voltages having equal absolute values and opposite polarities. That is, if the DC voltage output from the second phase detection circuit 142 is e(7), the DC voltage output from the third phase detection circuit 143 is -e(V). When this DC voltage ECV) and -e (V) are input to the subtraction circuit 144, in this subtraction circuit 144, e-(-e)=2e
C1) is performed, and a synchronization determination signal is obtained with a high output of 2e (V).

The subtraction circuit 144 can be constructed from an analog circuit using an operational amplifier.

In other words, a circuit in which a feedback path is formed from the output of the operational amplifier to the input via a resistor, and the input is grounded via the resistor is widely known as a subtraction circuit. By connecting the outputs of the second phase detection circuit 142 and the third phase detection circuit 143 to the ... input and (to) input of the operational amplifier configured as above, the absolute value of 2e (V) can be obtained as described above. A high-output synchronization determination signal can be easily obtained. The 2e (V) synchronization determination signal formed by the synchronization determination signal forming circuit 14 is inputted to the synchronization determination signal transmission circuit 16 via the second filter 15, and the synchronization determination signal transmission circuit 16 receives the PSK signal. During this period, a synchronization determination signal is continuously sent to the gate circuit 17, and the gate circuit 17 remains on while the synchronization determination signal is being input.

When the input signal is phase-shifted by data,
Accordingly, the second intermediate frequency signal 21F also undergoes a phase shift.

For example, as shown in B and C in FIG. 2, the second intermediate frequency signal 21F outputted at A is outputted in one π/2 phase or π/2 phase. The second intermediate frequency signal 21F of the first π/2 phase or the π/2 phase and the reference signals sent to C and 2 are not in phase or do not have a phase difference of π phase. and the third phase detection circuit 143 have zero outputs, and the synchronization determination signal forming circuit 14 does not send out a synchronization determination signal. However, at the time when the O-phase second intermediate frequency signal 21F is output to point A, the second intermediate frequency signal 21F is already synchronized, and at this point, the synchronization determination signal is continuously output from the synchronization determination signal sending circuit 16. Since the second intermediate frequency signal 21F is output, it is correctly input to the PSK signal demodulation circuit regardless of whether it has been phase shifted or not. As described above in detail, according to the present invention, it is possible to obtain a high-level output of the synchronization determination signal that detects that the signal input to the PLL circuit is synchronized with the reference signal, thereby improving the ability of the synchronization determination operation. The present invention has extremely significant effects, as it is possible to significantly improve the PSK signal demodulation effect and to achieve stable PSK signal demodulation.

It is clear that the present invention can be implemented not only in PSK signal demodulation circuits but also in synchronization determination circuits of all PLL circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a diagram showing signal waveforms at points A to B in FIG. 1. (Main symbols), 14... Synchronization determination signal forming circuit, 8, 142, 143... Phase detection circuit, 12
...Reference signal oscillation circuit, 13,141...
...Phase shift circuit, 144...Subtraction circuit.

Claims (1)

[Claims] 1. An oscillation circuit that oscillates a synchronization reference signal of a PLL circuit;
a first phase shift circuit that makes synchronization reference signals different from each other by π/2 and outputs them in two directions, and inputs the output in one direction to a first phase detection circuit belonging to a PLL circuit; The output of the circuit in one direction different from the above is input, one is in phase with the input, and the other is in phase with the input, and the output is 2.
a second phase detection circuit whose inputs are one output of the second transfer circuit and the output of the PLL circuit; and the other output of the second transfer circuit. and P.L.
a third phase detection circuit that receives the output of the L circuit as an input, and a subtraction circuit that outputs a difference between the output of the second phase detection circuit and the output of the third phase detection circuit, the subtraction circuit 1. A synchronization determination signal forming circuit for a PLL circuit, characterized in that an output of is used as a synchronization determination signal for the PLL circuit.