JPS5929900B2 - Flip-flop integrated circuit system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit construction method for a flip-flop integrated circuit.

As is well known, registers in data processing devices and the like are often constructed using an integrated circuit (IC) having a flip-flop main body 1 and an output gate 2 as structural units as shown in FIG.

An example of a register configured using the IC shown in FIG.
As shown in the figure. That is, this register takes in input signals 51 to 5n according to the timing of the clock 4 when the input gate control signal 3 is ``1''. Also, when the output gate control signal 6 is ``1'', the contents of the flip-flop are are sent out via output gates T1 to Tn. Output gate 7
The output examples of 1 to Tn are wired OR connected to the operand buses 81 to 8n corresponding to bits. FIG. 3 shows a block diagram of an arithmetic unit whose basic configuration is the register of FIG. 2.

In the figure, 9, 10, and 11 are registers with the above configuration, and these registers are connected to the operand bus 13 or 1.
4, and is connected to the arithmetic circuit 12 through the result bus 15. Similarly, it is possible to put an external bus 16 from an external device onto the operand bus 14. Let us now assume an operation in which the contents of register 9 and the contents of register 10 are operated, the result is stored in register 9, and the contents of register 10 are further stored in register 11. In the case of Figure 3,
Two bus operations are required to perform this operation. In other words, the first time is register 9.
The contents of the register 10 are read to the operand bus 13 and the contents of the register 10 are read to the operand bus 14, respectively, and the arithmetic circuit 12
The result is stored in the register 9 via the result bus 15. The second time, the contents of the register 10 are read out to the operand bus 14, passed through the arithmetic circuit 12, and then transferred to the result bus 1.
5 and stored in register 11.

The desired calculation is executed as described above. Furthermore, consider the following operation. That is, this is a process in which the contents of the external bus 16 are stored in the register 11, the contents of the external bus 16 and the contents of the register 9 are calculated, and the results are stored in the register 10. In this case as well, two bus reload operations are required.

That is, the first time, the contents of the external bus 16 are transferred to the operand bus 14, passed through the arithmetic circuit 12, and stored in the register 11 by the result bus 15. The second time, the contents of the register 9 are sent to the operand bus 13, the contents of the register 11 are sent to the operand bus 14, and the calculation result of the calculation circuit 12 is stored in the register 10 from the result bus 15.

The desired calculation is executed as described above. Conventionally, the configuration shown in FIG. 4 has been used to perform the above calculation in one bus operation.

According to this configuration, the data on the operand bus 14 can be taken into the register 11 through the special bus 17 without passing through the arithmetic circuit 12, and each bus operation of the above-mentioned arithmetic operations can be executed once. become. However, this method requires the addition of hardware for the special bus, which also means the addition of random logic, which goes against the requirement of improving the degree of integration by making the logic of each register the same. . The purpose of the present invention is to
It is an object of the present invention to provide a flip-flop integrated circuit configuration method that facilitates the configuration of a register that can be written to from the operand bus side without hindering the improvement of the degree of integration.

In order to achieve the above object, the present invention provides a flip-flop in which an AND gate between the output of the flip-flop main body and an output control signal is configured with a gate capable of wired 0R, and a feedback circuit that takes the output of the AND gate as an input signal. An IC is constructed using a flip-flop having a loop as a constituent unit.

A flip-flop IC chip adopting the construction method of the present invention is shown in FIG.

This is a circuit consisting of a 4-bit flip-flop, and two types of input signals are possible: external input signals 181-184 outside the IC and flip-flop output signals 191-194 within the IC. 20 is a gate control signal for selecting external input signals 181-184 outside the IC, and 21 is a gate control signal for selecting internal flip-flop output signals 19, 194.

The flip-flop is established at the timing of clock 22. The contents of this flip-flop are output to the outside by an output gate control signal 23. Also, the output gate is
As in the case shown in the figure, this gate is capable of wired 0R. FIG. 6 shows an example of a block diagram of an arithmetic unit using the IC shown in FIG. In other words, each register 24, 25
, 26 are adapted to receive the flip-flop output signal within the 1C in addition to the external input signal from the result bus. Now, the contents of register 24 and register 25
Assume an operation in which the contents of the register 25 are calculated, the results are stored in the register 24, and the contents of the register 25 are stored in the register 26. In this case, when the operation of registers 24 and 25 is executed, the contents of register 25 are output to operand bus 27. Therefore, in the register 24, if the control signal to take in the external input signal from outside the IC is set to ``1'''', and in the register 26, the control signal to take in the internal flip-flop output signal to ``1'''', the register 24 will be set to ``1''''. The contents of the result bus, that is, the operation results of the contents of register 24 and the contents of register 25, are stored in register 26, and the contents of operand bus 27, that is, the contents of register 25 are stored in register 26. Next, the contents of external bus 28 are stored in register 26. Assume that the contents of the external bus 28 and the contents of the register 24 are stored, the contents of the external bus 28 and the contents of the register 24 are calculated, and the contents of the register 24 are stored. shows the contents of the external bus 28. Therefore, in the register 25, set the control signal to take in the external signal outside the IC to "1", and in the register 26, set the control signal to take in the internal flip-flop output signal to "1". , the register 25 contains the contents of the result bus, that is, the result of the calculation of the contents of the external bus 28 and the contents of the register 24, and the register 26 contains the operand bus 27.
In other words, the contents of the external bus 28 are stored. In other words, both of the above operations can be executed in one bus operation. As is clear from the above explanation,
When a data processing device is configured using the IC circuit according to the present invention, since the IC includes a feedback path that allows input from the operand bus, there is no need to use special gates or special wiring patterns for bypass. Both enable register writing from the operand bus, leading to higher performance and higher integration of data processing devices.

[Brief Description of the Drawings] Fig. 1 is a diagram showing the structural unit of a conventional flip-flop IC, Fig. 2 is a diagram showing a register configuration when the IC of Fig. 1 is used, and Fig. 3 is a diagram showing the configuration of a register when the IC of Fig. A block diagram of a data processing device based on registers, FIG. 4 is a diagram showing a case where a special path is provided in the configuration of FIG. 3, and FIG. 5 is a block diagram of an IC according to the present invention.
FIG. 6, which is a diagram showing a circuit configuration method, is a block diagram of a data processing device based on a register using the IC of FIG. 181-184...External input signal outside the IC, 19
1 to 194... Flip-flop output signal within own 1C, 20, 21... Input control signal, 22...
...Clock, 23...Output gate control signal.

Claims (1)

[Claims] 1. A plurality of flip-flops into which external signals are input in parallel, a plurality of AND gates into which the output signals of the corresponding flip-flops are respectively input, and a feedback signal which connects the output side of each AND gate and the input side of the corresponding flip-flop, respectively. line, an input control signal line that commonly controls each flip-flop so as to select either the external signal or a signal on the output side of the AND gate as an input signal, and an input control signal line that commonly controls each flip-flop so that the output of each flip-flop is connected to the corresponding AN.
and an output control signal line that commonly controls each AND gate so as to appear on the output side of the D gate,
The output side of the gate is wired OR with the data bus respectively.
1. A flip-flop integrated circuit system, characterized in that the flip-flop integrated circuit is connectable, and the signal on the data bus line can be input to the flip-flop via the feedback signal line.