JPS5931988B2 - Method for manufacturing complementary MOS gate circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a method for manufacturing a complementary MOS gate circuit having a large current drive capability.

Complementary gate circuit is a P-channel M on a single semiconductor substrate.
It is constructed by connecting an OS transistor and an N-channel MOS transistor in series, and is characterized by extremely low power consumption and extremely large noise margin.

However, since this type of circuit is inferior in large current drive capability, a bipolar transistor is added to the output section of the gate circuit as shown in FIG. 1 to increase the drive capability. Regarding the structure of configuring a bipolar transistor in the drain region of a MOS transistor, the structure is disclosed in Japanese Patent Publication No. 44-111824 "Display Device" published on May 29, 1969.
Unexamined Japanese Patent Publication No. 52-26181 published on February 26, 1977
It is described in detail in "Semiconductor integrated circuit device".

FIG. 2 shows a conventional manufacturing process for the complementary MOS gate circuit shown in FIG. Below, for comparison with the manufacturing process according to the present invention,
FIG. 2 will be briefly explained. An N-channel type M is formed on an N-type semiconductor substrate 1 made of silicon having a high resistivity of 5 to 10 Ω and having an impurity concentration of about 1×10”/cni.
In order to form an OS transistor, a low concentration P-type impurity is diffused to form a P-type semiconductor region 2 having an impurity concentration of about 5.times.10@15 /.about.(FIG. 2a).

Next, a channel blocking region 4 and a P
A P channel MOS is located at a position isolated from the semiconductor region 2.
In order to form the source and drain regions 5 and 6 of the transistor, after removing the oxide film 3 directly above the regions 4, 5 and 6 by etching, a high concentration of P-type impurity of about 1×1018/~ is diffused (second Figure b).

In order to form the source and drain regions 7 and 8 of the N-channel MOS transistor, the channel blocking region 9 of the P-channel MOS transistor, and the emitter region 10 of the bipolar transistor, a high concentration of N-type impurity of about 1×10 21 /~ is applied. Diffusion (Figure 2c).

After removing the oxide film 3 between the source and drain regions of the P-channel type and N-channel type MOS transistors, a gate oxide film 11 is formed (FIG. 2d). A contact hole 12 for metal wiring is formed (FIG. 2e).

After aluminum is deposited on the surface of the semiconductor substrate, it is etched and the drain region 7 and emitter region 10 are formed using the first layer wiring material 13.
(Fig. 2 f).

After growing the intermediate insulating film 14, a contact hole is formed, and after aluminum vapor deposition, an aluminum wiring 15 is formed as a predetermined second layer wiring material by etching (FIG. 2G, h).

As mentioned above, in the conventional manufacturing process, when gate oxidation is performed at about 1100° C. after n+ diffusion as shown in FIG. Current amplification rate β of bipolar transistor because it spreads to P+ region 5
It is extremely difficult to control.

Furthermore, if N+ diffusion is performed after gate oxidation as shown in FIG. 2d to eliminate the above drawback, the gate oxide film 11 will be contaminated with N type impurities
It has a drawback that makes the function of MOS transistor defective.
Furthermore, in conventional processes, when aluminum is used as a single-layer wiring material, the melting point of aluminum (about 660°C) is low, so the temperature is about 660°C.
This method has the disadvantage that it is difficult to grow the intermediate insulation at higher temperatures, making it impossible to obtain a high-quality intermediate insulation film.

In addition, when wiring with a width of 10 μm or less is made with aluminum, breakage easily occurs, making it unsuitable as a wiring material for high-density semiconductor circuit devices. In order to eliminate the drawbacks of the conventional method of manufacturing a complementary gate circuit device as described above, the present invention has been developed by using polycrystalline silicon for each gate electrode of a MOS transistor, the wiring between the electrodes of P and N channel transistors, and the emitter region of a bipolar transistor. It is intended to be simultaneously formed and solved through use.

An embodiment of the manufacturing process of the present invention shown in FIG. 3 will be described in detail below. 5~10Ω? In order to form an N-channel type MOS transistor region in the N-semiconductor substrate 21 having a high resistivity, a low concentration P-type impurity is diffused to form a P-semiconductor region 22 with an impurity concentration of about 5×10 15 /Cril. (Figure 3a).

Next, after selectively making holes in the oxide film 23 by etching,
Source and drain regions 24 of P channel transistor
, 25 and the channel blocking region 26 of the N-channel transistor, a high concentration of P-type impurities of about 1.times.10@18 /.about. is diffused (FIG. 3b). Further, source/drain regions 27, 28 of N-channel transistors and channel blocking regions 29 of P-channel transistors.
In order to form an oxide film 23 on the semiconductor surface, an oxide film 23 is again formed on the semiconductor surface by diffusing N-type impurities at a high concentration of about 1×10 21 /d (FIG. 3c).

Next, the oxide film 23 in the part that will become the gate electrode of the MOS transistor is removed, and a thin gate oxide film 31 with a film thickness of about 1000λ is grown. A contact hole 32 is formed in order to make contact with (FIG. 3d).

Furthermore, a polycrystalline silicon film 36 is grown in a vapor phase over the polycrystalline silicon film, and an N+ type impurity is doped at a high concentration of about 1×10 21 /~.

The N+ impurity is transferred to the P+ impurity via the polycrystalline silicon film 36.
At the same time as the polycrystalline silicon film is diffused into the region 25 and an N+ region which is the emitter region of the NPN type bipolar transistor is formed, the polycrystalline silicon film is changed into a conductor by the N+ impurity.
Here, the current amplification rate β of the transistor is controlled by the doping amount and doping time of the N+ type impurity (Fig. 3e).
. Since the polycrystalline silicon film 36 doped with N+ type impurities exhibits good conductivity, the necessary pattern is used as an electrode wiring after etching (FIG. 3f).

Next, an insulating film 34 is grown in a vapor phase, and after contact holes for leading out electrodes are formed, a second layer of wiring conductor 35 is deposited, and desired electrode wiring is formed by etching, completing the manufacturing process of the present invention. In the embodiment of the present invention, the steps shown in FIG. 3b and FIG. 3c may be interchanged, and there will be no difference in the electrical performance or yield of the product.

As explained above, in the manufacturing process according to the present invention, a polycrystalline silicon film is grown on the entire surface of the semiconductor substrate after gate oxidation, and a high concentration of N-type impurity is doped through the polycrystalline silicon film.
It is easy to control the diffusion state of the + region.

Moreover, the polycrystalline silicon film has the advantage of preventing contamination of the gate oxide film during the manufacturing process. Furthermore, since a polycrystalline silicon film is used as the first-layer wiring material, it can be processed at high temperatures, making it possible to grow a high-quality intermediate insulating film.

Using polycrystalline silicon as a wiring material, it is possible to obtain a wiring width of usually 6μ, which is thinner than aluminum material. In addition, the self-aligned silicon gate that has been implemented in the past has not been able to intersect the polycrystalline silicon film and the diffusion layer, making it impossible to create a multilayer wiring structure. However, according to this embodiment, cross wiring can be freely performed and the manufacturing process can be shortened. As described above, the manufacturing method according to the present invention exhibits extremely large effects in manufacturing semiconductor integrated circuit devices.

[Brief explanation of drawings]

Fig. 1 shows a complementary MOS gate circuit that increases the current 1 drive capability, Fig. 2 shows a manufacturing process diagram of a conventional complementary MOS gate circuit, and Fig. 3 shows a manufacturing process of a complementary MOS gate circuit according to an embodiment of the present invention. Show the diagram. 1, 21... Semiconductor substrate, 2, 22...
・P-semiconductor region, 3, 14, 23, 34...
Insulating film, 4, 9, 26, 29... Channel blocking region, 5, 7, 25, 27... Drain region, 6, 8, 24, 28... Source area, 10,
30...Emitsuta area, 11,31...
・Gate oxide film, 12, 32... Contact hole, 13, 15, 35... Metal wiring, 36...
...Polycrystalline silicon film.

Claims (1)

[Claims] 1. A second region is formed by diffusing a low concentration impurity having a second conductivity type from the surface of a first region of a high resistivity semiconductor substrate having a first conductivity type; A first source region and a first drain region are formed by diffusing highly concentrated impurities of a second conductivity type into two regions provided at a distance from the second region on the surface of the region, and forming a first source region and a first drain region. A highly concentrated impurity of the first conductivity type is diffused into two separated regions within the two regions.
forming a source region and a second drain region, forming an oxide film on the entire surface of the semiconductor substrate, and forming a region between the first source region and the first drain region and between the second source region and the second drain region; forming a gate oxide film by removing the oxide film between the regions, forming contact holes in the first drain and second drain regions, and forming a polycrystalline silicon film on the entire surface of the semiconductor substrate; A highly concentrated first impurity is diffused into the entire surface of the polycrystalline silicon film to convert the polycrystalline silicon film into a first layer wiring material, and at the same time, an emitter region of a bipolar transistor is formed in the first drain region. and selectively etching the polycrystalline silicon film to form a gate electrode and a wiring connecting the first and second drain regions on each of the gate oxide films, thereby covering the entire surface of the semiconductor substrate. Forming an intermediate insulating film and selectively etching the intermediate insulating film to form contact holes on wirings connecting each gate electrode to the first and second drain regions and on the first and second source regions. A second layer of wiring material is formed by vapor deposition on the entire surface of the semiconductor substrate, and the second wiring layer is selectively etched to separate each gate electrode and the first and second drain regions. A method for manufacturing a complementary MOS gate circuit device, including the step of forming connecting wiring and respective extraction electrodes of the first and second source regions. 2. The method of manufacturing a complementary MOS gate circuit device according to claim 1, wherein the first conductivity type is an N type, the second conductivity type is a P type, and the semiconductor substrate is a silicon substrate.