JPS5933980B2 - Method for manufacturing semiconductor substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a single crystal semiconductor layer on an insulating material, and in particular to a method for forming a single crystal semiconductor layer on an insulating material, and in particular to a method for forming a single crystal semiconductor layer on an insulating material.
Regarding CMOS-engineering C).

A semiconductor substrate having a single-crystal semiconductor layer on an insulating material is advantageous for realizing a low-power, high-speed integrated circuit because the parasitic capacitance of a semiconductor element formed in the semiconductor layer is small. In particular, substrates in which the semiconductor layer has a thickness of 1 μm or less are made of high-performance C.
Advantageous for MOS-IC. Conventionally, applicable techniques are a 505 substrate obtained by epitaxially growing silicon on a sapphire substrate, or a dielectric isolation technique for bipolar semiconductor devices called EPIC.

However, with such conventional semiconductor substrates and LSOS substrates, a thin semiconductor layer can be obtained, but since the semiconductor layer is grown on a foreign material, stress and defects are included in the semiconductor, resulting in poor quality and low productivity. economic efficiency cannot be improved.

In addition, even if the quality of the semiconductor layer is good in the pick method, it is not possible to realize a semiconductor layer with a thickness of 5 μm or less because of poor polishing and etching accuracy. All of these drawbacks make it unsuitable for use as a semiconductor substrate for integrated circuits having good electrical properties. An object of the present invention is to provide a method for manufacturing a semiconductor substrate that has a thin single-crystal semiconductor layer of excellent quality and can realize a high-performance integrated circuit.

The method for manufacturing a semiconductor substrate of the present invention includes the steps of forming an insulating film on the main surface of a single crystal semiconductor, forming grooves dividing the main surface, and forming a substrate member on the upper surface of the insulating film on one side of the main surface. A step of supplying a current through the vicinity of the groove from one of the divided main surfaces to etch the other, and a step of forming a predetermined semiconductor element on the other.

The formation of the formation can be done before or after the formation of the substrate member.

The grooves are precisely formed by electrolytic etching or oxidation etching using a chemical conversion method, and the depth of the grooves becomes the final thickness of the semiconductor layer. For the substrate member, a high melting point metal such as polycrystalline silicon or molybdenum is used that can withstand the heat treatment required in the manufacturing process of a predetermined semiconductor element. In the manufacturing method of the present invention, since the depth of the groove controls the final film thickness of the single crystal semiconductor layer, it is possible to realize a thin film thickness with extremely high precision.

The semiconductor layer is of high quality because it is obtained by etching the semiconductor matrix. Therefore, the semiconductor substrate obtained by the present invention realizes a low-power, high-speed semiconductor integrated circuit. Next, in order to better understand the characteristics of this invention, embodiments of this invention will be described using drawings.

FIGS. 1a to 1h are sectional views showing main steps of an embodiment of the present invention. In this embodiment, a silicon oxide film (SiO2 film) 102 of about 2 μm is grown by thermal oxidation on the surface of an N-type single crystal matrix 101 with a thickness of 200 μm and a resistivity of 1Ω (FIG. 1a).

Polycrystalline silicon 103 with a thickness of 200 μm is further grown on the upper surface of the SiO2 film 102 as a substrate member (Fig. 1b).
).

Next, the back surface of the matrix 101 is mechanically polished and further treated with a chemical etchant to form a single crystal layer 101' having a thickness of about 10 μm (FIG. 1c).

Grooves 104 dividing the surface are selectively formed on the polished surface of the single crystal layer 101' by photolithography (FIG. 1d).

This groove 104 divides the polishing surface into at least a peripheral portion A and a central portion B.

The photo-etching of the grooves 104 is carried out by etching with a mixture of nitric acid and monofluoric acid using a photoresist as a mask, or by providing a SiO2 film (not shown) of about 1000A on the polished surface in advance and photoetching, using this SiO2 film as a mask. ~8 『C2
This can be done by immersion in a specified potash solution. The anode of the power source is attached to the divided peripheral portion A, and the cathode is immersed in a solution to anodize the sample. The chemical conversion of silicon is performed using a dilute solution of oxalic acid, chromic acid, or sulfuric acid, or a saturated solution of ammonium borate in ethylene glycol, using a constant voltage chemical conversion method. The chemical formation current is supplied from the peripheral portion A to the central portion B through the lower part of the groove 104, and a chemical formation film is grown in the vicinity of the groove 104 and on the surface of the central portion B. Since this chemical film is obtained by oxidative etching of silicon, by removing the chemical film with a hydrofluoric acid solution, the polished surfaces of the central portion B and the grooves 104 settle. After performing constant voltage chemical formation at 100 V in a 2% sulfuric acid solution, the sedimentation was about 0.1 μm when the chemical film was removed.

By repeating this chemical formation and removal process, the polished surfaces of the grooves 104 and the central portion B repeatedly settle, and the sedimentation stops when the bottom of the grooves 104 reaches the SiO2 film 102. That is,
A silicon layer 101' having a thickness of approximately 1 μm, which is approximately equal to the depth of the groove 104, is formed in the central portion B. The oxidative etching described above can be replaced by electrolytic etching for faster processing.

That is, when the sample shown in FIG. 1d is electrolytically treated in 49% hydrofluoric acid with a constant current, the surface of the groove 104 and the center part B in the solution changes to porous silicon, and the bottom of the groove 104 becomes porous. S
Immediately before reaching the iO2 film 102, the electrolysis is switched to constant voltage electrolysis to control the end point. Since porous silicon is chemically etched extremely rapidly in the above-mentioned potassium solution, a single crystal silicon layer 101' having a thickness of about 1 μm can be formed in the central portion B (FIG. 1e). Next, the peripheral portion A used for current supply is polished and removed to complete the semiconductor substrate of this example (first
Figure f). That is, this base is a thick polycrystalline silicon base 103.
A thin single-crystal silicon layer 101' on which a predetermined semiconductor element is to be formed is formed on the upper surface of the substrate with an SiO2 film 102 interposed therebetween. The semiconductor body shown in FIG. 1f is, for example,
A silicon nitride film 10 is selectively formed on silicon as shown in FIG.
5, 106 and 107 are deposited, and thermal oxidation is performed using this as a selective oxidation mask to form the silicon layer in the gap with SlO2.
The film changes into a film 108 to insulate and isolate each element.

The bottom of this SiO2 film 108 reaches the SiO2 film 102, and the silicon layers 109 and 1 are separated from each other by this.
10 and 111 are active regions completely dielectrically isolated. Respective silicon layers 109, 110 and 11
1, by making full use of well-known photolithographic techniques such as selective diffusion hole formation and electrode formation, N-type regions 112 and 113 are formed, respectively.
N-type field effect transistor QN consisting of P-type region 114, P-type regions 115 and 116 and N-type region 1
P-channel field effect transistor Q consisting of 17
A CMOS-1C including a PN junction diode D including a p, N type region 118 and a P type region 119 can be formed. (FIG. 1h) According to the embodiment described above, a semiconductor substrate having a thin high-quality single crystal silicon layer of 1 μm or less on an insulating material is obtained.

This semiconductor substrate can realize a high-speed, low-power CMOS-1C in which each semiconductor element is separated by an insulating material and parasitic capacitance is reduced, as shown in FIG. 1h. FIGS. 2a to 2f are cross-sectional views of the main manufacturing steps of another embodiment of the present invention.

In this embodiment, approximately 2 μMf is applied to one flat main surface of an N-type silicon single crystal matrix 201 with a thickness of 200 μm and a resistivity of 1Ω.
) A SiO2 film 2.02 is grown by thermal oxidation, and this SiO2 film 202 is selectively etched to form two SOOs and a film 20 in grooves 203.
2,202' (Fig. 2a).

Approximately 2 μm of SiO is added to the groove 203 by thermal oxidation treatment again.
By growing the second film 204, a groove 203' having a depth of approximately 1 μm is etched in this portion of the base body 201 by oxidation etching.

A part of the SiO2 film 202' at the peripheral edge of the matrix is selectively etched, and this portion is exposed on the matrix surface 205 (FIG. 2b).

After these pretreatments, one major surface of the matrix was coated with a thickness of 300 It.
A conductive polycrystalline silicon 206 of m is grown as a substrate member (FIG. 2c).

In this embodiment, as shown in FIG. 2d, a positive electrode is bonded to the polycrystalline silicon 206, and the above-mentioned anodic etching is performed using hydrofluoric acid. Supply current in the direction of the arrow.

This current flows inside the base body 201 above the contact portion 207 and the groove 203', and uniformly etches the exposed surfaces of the peripheral portion A and central portion B of the base body 201. This electrolytic etching is groove 2.
The base material in the central part B is etched until the SiO2 film 204 grown at 03' becomes a barrier, and a single crystal silicon layer 20V of about 1 μm remains in the central part B at the SiO2 film 204 portion, thereby completing the semiconductor substrate ( Figure 2 e). Thereafter, in the same manner as described using FIGS. 1g to 1h of the previous example,
N type regions 207, 208 and P in the single crystal silicon layer 20V
N-channel field effect transistor QN consisting of type region 209, P-type region 210, 211 and N-type region 2
P-channel field effect transistor Q consisting of 12
A CMOS-1C including p is realized. In this example, compared to the previous example, the grooves were formed by oxidation etching, and SiO2
0.5 to 1.0 to ensure that the film 204 stops etching.
An insulating material-separated semiconductor body having an extremely thin monocrystalline silicon layer on the order of micrometers is obtained.

[Brief explanation of the drawing]

Figures 1a to 1h are sectional views of main steps in one embodiment of the present invention, and Figures 2a to 2f are sectional views of main steps of another embodiment of the invention. It is. 101...N-type silicon single crystal matrix, 102.
...SlO2 film, 103 ... Polycrystalline silicon, 104 ... Groove, 105, 106, 107
...Silicon nitride film, 108...Sl
O2 film, 109, 110...Active region, 111
, 112, 117, 118...N-type region, 11
3,115,116.119...P type region, 2
01... N-type silicon single crystal matrix, 202...
...SlO2 film, 203... Groove, 204.
...SlO2 film, 205...Material surface,
206...Polycrystalline silicon, 207,208,
212...N-type region, 209, 210, 211
...P-type pirate.

Claims (1)

[Claims] 1. A step of forming an insulating film on one main surface of a single crystal semiconductor, a step of forming a substrate member on the insulating film, and a step of forming the single crystal on the side where the insulating film is not provided. dividing the single crystal semiconductor into a central part and a peripheral part by forming a groove on the surface of the other main surface of the semiconductor; and a step of dividing the single crystal semiconductor into a central part and a peripheral part by forming a groove in the surface of the other main surface of the semiconductor; A step of supplying a current through the portion of the single crystal semiconductor between the provided one principal surface and removing the other principal surface side of the central portion of the single crystal semiconductor by anodizing and etching the surface thereof. and forming a semiconductor element in the central portion whose surface has been removed to a predetermined thickness by the chemical conversion etching. 2. Prepare a semiconductor substrate in which a groove is formed in one main surface of a single crystal semiconductor, thereby dividing the single crystal semiconductor into a central part and a peripheral part, and an insulating film is formed on one main surface including the groove. a step of forming a substrate member on the insulating film; and a step of forming a substrate member on the insulating film, and a step of forming a substrate member on the insulating film from the peripheral portion to the central portion between the bottom of the groove and the other main surface of the single crystal semiconductor on which the insulating film is not provided. a step of supplying a current through the portion of the single crystal semiconductor to remove the other main surface side of the central portion of the single crystal semiconductor from the surface by chemically forming and etching the surface; forming a semiconductor element in the central portion which has a predetermined thickness by removing the central portion.