JPS5935065B2 - How to read pattern information - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scanning pattern information reading method.

A conventional method for reading pattern information using a scanning photoelectric converter will be explained with reference to FIG.

In FIG. 1, 1 is a light source, 2 is pattern information, 3 is a lens, 4 is a photoelectric converter, 5 is a comparison circuit, and 6 is a reference level determination circuit.

That is, the light source 1 emits light, this light hits the pattern information 2 and is reflected, passes through the lens 3 and forms an image on the photoelectric converter 4 according to the pattern information 2.

At this time, the photoelectric converter 4 outputs an analog voltage or analog current according to the input light amount. This analog output is then input to a comparison circuit 5 and a reference level determination circuit 6, where it is compared with the output reference level of the reference level determination circuit 6 and converted into a binary value of "1" or "O". output as the value. Note that in this conventional method, the reference level is fixed.

Furthermore, as a result of storing and calculating the maximum and minimum values of the analog output of the photoelectric converter 4 according to the pattern information 2, for example, the average value of the maximum and minimum values is used as a reference level for comparison. There is. FIG. 2 is a diagram for explaining the relationship between pattern information and analog output level in the pattern information reading method as described above.
01 represents a "black" portion of the pattern information, and 202 represents a "white" portion of the pattern information, and this pattern information is imaged onto the photoelectric converter 204 through the lens 203.

At this time, the photoelectric converters 204 are n4, n2, n3...
The photoelectric converter 204 is configured to sample the amount of light as shown in nl, n2, n3...
The relative output characteristics with respect to the amount of light sampled by ... are shown in FIG. 2B. However, in the conventional method explained with reference to FIG. 1, the sampled relative output having the above-mentioned characteristics is compared with the output of the reference level determination circuit 6 and binarized. In practice, due to the noise level caused by pattern information etc.
The problem was that pattern information such as that shown in Figure 1 cannot be binarized accurately, the width of "white" or "black" becomes wide, and the resolution decreases.

Another drawback was that it was easily affected by the noise level during binarization. The present invention has been made in view of the above points, and it involves sequentially selecting an optimal reference level or determining an optimal analog output level according to already binarized pattern information that is correlated with the position of the pattern to be currently binarized. It is an object of the present invention to provide a pattern information reading method that can increase the resolution of pattern information, increase the signal-to-noise ratio, and obtain clear binarized pattern information by selection.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram for explaining the first embodiment of the present invention.

In this figure, 301 is a light source, 302 is pattern information, 303 is a lens, 304 is a photoelectric converter, 305 is a comparison circuit, 306 is a reference level determination circuit, and 307 is a storage circuit. That is, the light source 301 emits light, and this light is
It is reflected by the pattern information 302 and forms an image on the photoelectric converter 304 through the lens 303 according to the pattern information 302 . At this time, the photoelectric converter 304 outputs an analog voltage or analog current according to the input light amount. Then, this analog output is input to a comparison circuit 305 and a reference level determination circuit 306, and the comparison circuit 305 compares it with the output of the reference level determination circuit 306, and the result is "1".
It is output as a binary value of "0" or "O". Also,
This binarized output is stored in the storage circuit 307, and is input to the reference level determining circuit 306 at the next timing, and the output (reference level) of this reference level determining circuit 306 is selected. Therefore, in this first embodiment,
The results of adjacent bits on the main scan that have already been binarized are stored, and the reference level for the next analog output to be binarized is selected based on the results. FIG. 4 is a diagram showing a specific example of the configuration of the reference level determining circuit 306, which is suitable when the output of the photoelectric converter 304 is an analog voltage.

In this figure, 308 is a maximum value detection holding circuit, 309
is an addition calculation circuit, 310 is a minimum value detection holding circuit, 311
is an analog switch circuit. The operation of the reference level determining circuit 306 configured as described above will be explained.

The output of the photoelectric converter 304 in FIG. 3 is supplied to input 1, and maximum value detection and holding circuit 308 and minimum value detection and holding circuit 31
0, and the maximum value detection holding circuit 308 is
The maximum value of the output voltage of the photoelectric converter 304 is detected, the voltage is held, and the value is sent to the input terminal 1 of the addition calculation circuit 309. On the other hand, the minimum value detection and holding circuit 310 detects the minimum value of the output voltage of the photoelectric converter 304, holds that voltage, and adds the value to the input terminal 2 of the calculation circuit 309.
send to. Further, the output of the storage circuit 307 in FIG. 3 is supplied to the input 2 of the analog switch circuit 311. In this case, the analog switch circuit 311 controls, depending on the output of the memory circuit 307, whether the input terminal 3 of the addition operation circuit 309 is connected to the analog voltage (H-,) or grounded. Specifically speaking, the analog switch circuit 311 is
When input 2 is “0”, input terminal 3 of addition calculation circuit 309
Input the analog voltage (VH-L) to
1, the input terminal 3 of the addition calculation circuit 309 is grounded. Therefore, the addition calculation circuit 309 adds the three input voltages with appropriate weights, so that when the input terminal 3 is an analog voltage (VH-L), that is, the input 2 is "O
”, the voltage VH is output as the reference level, and when the input terminal 3 is grounded, that is, when the input 2 is “1”, the voltage VL is output.
is output as the reference level. As explained above, in the first embodiment, the result of the adjacent bit that has already been binarized is stored, and the reference level for the next analog output to be binarized is determined from the voltage VH (2 of 5VL). Therefore, in the first embodiment, the binarized results are as follows compared with the conventional method.

That is, FIG. 5 is a diagram for explaining the difference between the method according to the first embodiment of the present invention and the conventional method, and 401 in FIG.
402 is a photoelectric converter, and FIG. 5B shows each bit Ml, m2, m3 of the photoelectric converter 402.
The relative output of ... is shown in a graph.
When the graph shown in FIG. 5B is binarized using the conventional method (obtaining a binarized pattern using voltage S as a reference level), bits M3, m6, m7, and m8 become "1". On the other hand, when the voltage VH (5VL is set as the reference level) and is sequentially binarized from bit m1 by the method according to the first embodiment of the present invention, voltage VH is selected as the reference level for bits m1 to M2. “0”, bit M3
Then, in order to exceed the voltage VH as the reference level, set it to "1".
Therefore, bit M4 selects voltage VL as the reference level, so it becomes "1".Bit M5 becomes "O" because it is less than voltage VL as the reference level, and bit M6 selects voltage VH as the reference level. Since it is selected, it becomes "O". Subsequently, the results are sequentially binarized in the same manner, and the results of this binarization are shown in FIG. 6 together with the results of the conventional method. In FIG. 6, A indicates a sample point of the photoelectric converter 402, B indicates a binarization pattern according to the conventional method, and C indicates a sample point according to the first method of the present invention.
3 shows a binarization pattern according to the method of the embodiment. Therefore, as is clear from the above description, according to the first embodiment of the present invention, the resolution of pattern information can be increased and clear binarized pattern information can be obtained.

Furthermore, the margin for the noise level, that is, the signal-to-noise ratio is also increased, and as a result, clearer binary pattern information can be obtained. FIG. 7 is a diagram for explaining a second embodiment of the present invention, and this second embodiment is effective when the pattern information is a two-dimensional plane pattern.

Regarding the second embodiment, in FIG.
Reference numerals 1 to 305 are a light source, pattern information, lens, photoelectric converter, and comparison circuit, which have the same functions as the first embodiment, but the comparison circuit 305 converts the two-dimensional plane pattern into the X-axis direction and the Y-axis direction. The image is scanned sequentially while being binarized in the direction. Further, 306 is a reference level determining circuit, and 307 is a storage circuit, which stores binarized pattern information for one column or more, and is configured by, for example, a shift register. . Then, from the storage circuit 307, the binarization result of one bit before and the binarization result of one column before are sent to the reference level determination circuit 306. In other words, in the second embodiment, The reference level is selected based on the binarization result of one bit adjacent and the binarization result of one bit adjacent in the Y-axis direction (sub-scanning direction). In this case, it is easy to consider selecting voltages VH and VL as reference levels by logical OR of adjacent bits in the X-axis direction and Y-axis direction, but the nature of the pattern information to be binarized, photoelectric conversion The reference level is increased to a maximum of four types based on the resolution of the X-axis direction and the Y-axis direction of the converter 304, and the reference level that provides the most clear binarized pattern according to the 2-bit prior history pattern is selected. You may also do so. In the case of this second embodiment, the reference level can also be selected based only on the binarization result of one bit adjacent in the Y-axis direction.
As described in detail above, the present invention sequentially selects the optimal reference level or the optimal analog output level according to the already binarized pattern information that is correlated with the position of the pattern to be currently binarized. By doing so, it is possible to obtain clear binarized pattern information by increasing the resolution of pattern information and increasing the signal-to-noise ratio.
It is effective when applied to 1 fax and various code readers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a conventional pattern information reading method, FIG. 2 is a diagram for explaining the relationship between pattern information and analog output level in the pattern information reading method, and FIG. 3 is a diagram according to the present invention. A block diagram for explaining the first embodiment of the pattern information reading method, FIG. 4 is a block diagram showing a specific example of the reference level determining circuit in the first embodiment, and FIG. 5 is according to the first embodiment. A diagram for explaining the difference between the method and the conventional method, FIG. 6 is a diagram showing the result of binarization by the method according to the first embodiment and the conventional method, and FIG. 7 is a diagram showing the result of binarization by the method according to the first embodiment and the conventional method. FIG. 2 is a configuration diagram for explaining an example. 301... Light source, 302... Pattern information, 303... Luns, 304... Photoelectric converter, 305... Comparison circuit, 306...・・・
. . . Reference level determination circuit, 307 . . . Memory circuit.

Claims (1)

[Claims] 1. Binarization using a scanning photoelectric converter, a reference level determination circuit that outputs a reference level for comparison with the analog output of the scanning photoelectric converter, and a comparison circuit that compares the analog output with the reference level. In a pattern information reading method for obtaining pattern information, the results of binarization during scanning are sequentially stored in a storage circuit, and the results of binarization are sequentially stored in a storage circuit. The digitized result is input from the storage circuit to a reference level determination circuit, and this reference level determination circuit inputs the maximum and minimum values of the analog output of the scanning photoelectric converter and the already binarized pattern from the storage circuit. A pattern information reading method characterized by sequentially selecting an optimal reference level according to the information.