JPS5935178B2 - Method of forming solder bumps on electrodes on semiconductor substrates - Google Patents
Method of forming solder bumps on electrodes on semiconductor substratesInfo
- Publication number
- JPS5935178B2 JPS5935178B2 JP50143965A JP14396575A JPS5935178B2 JP S5935178 B2 JPS5935178 B2 JP S5935178B2 JP 50143965 A JP50143965 A JP 50143965A JP 14396575 A JP14396575 A JP 14396575A JP S5935178 B2 JPS5935178 B2 JP S5935178B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- metal mask
- electrodes
- semiconductor substrates
- solder bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は、半導体基板上の電極部に半田バンブを形成す
る方法に関する発明である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming solder bumps on an electrode portion on a semiconductor substrate.
半導体基板と外部リードとの接続には、極細Al線もし
くはAu線等を用いるワイヤボンディング法が採用され
ている。A wire bonding method using ultrafine Al wires, Au wires, or the like is used to connect the semiconductor substrate and external leads.
一方、接続部の信頼性向上、高密度化、コスト低減等の
目的のためワイヤーを用いないワイヤレスボンディング
法が各種提案されて一部実用化されている。本発明は、
このワイヤレスボンディング法において半田を用いる接
続法に関するものである。半田を用いる接続法には周知
のように、IBM社のCCB法がある。On the other hand, various wireless bonding methods that do not use wires have been proposed and some have been put into practical use for the purpose of improving the reliability of connection parts, increasing density, reducing costs, etc. The present invention
The present invention relates to a connection method using solder in this wireless bonding method. As is well known, the connection method using solder is the CCB method of IBM Corporation.
この方法は第1図に示すように、半導体基板1上の絶縁
膜3から露出するAl電極部2にCr−Cu−Auの金
属をメタルマスクを使用して順次蒸着し、その後前記と
は異なるメタルマスクを使用して半田を蒸着する。この
半田をメタルマスクを使用して真空蒸着する方法におい
て、蒸着半田量をコントロールすることは接続部の信頼
性の面から非常に重要であるとともに、半田量が多いほ
ど接続が容易になることは明白である。一方、半田の供
給法として真空蒸着法を用いる場合には、その蒸着厚さ
は、最大約100μと限定される。As shown in FIG. 1, this method uses a metal mask to sequentially deposit Cr-Cu-Au on the Al electrode portion 2 exposed from the insulating film 3 on the semiconductor substrate 1, and then Deposit solder using a metal mask. In this method of vacuum evaporating solder using a metal mask, controlling the amount of evaporated solder is very important from the viewpoint of reliability of the connection, and it is also true that the larger the amount of solder, the easier the connection. It's obvious. On the other hand, when a vacuum evaporation method is used as a solder supply method, the maximum evaporation thickness is limited to about 100 μm.
このため、IBM社では必要な半田量を得るため第2図
に示すように、電極部のCr−Cu−Au蒸着膜の径よ
り大きな穴径をもつメタルマスクにより半田を蒸着し、
その後溶融させ、表面張力によりCr−Cu−Au蒸着
膜上に半田が引きよせられる性質を利用して必要な半田
量を得ている。しかし、その時使用されるメタルマスク
の穴形状は円形であり、穴形状が電極部(Cr−Cu−
Au蒸着膜)より大きいため、隣接する電極間の間隔は
すくなくともメタルマスク穴径より大きくなければなら
なかつた。For this reason, in order to obtain the necessary amount of solder, IBM uses a metal mask with a hole diameter larger than the diameter of the Cr-Cu-Au deposited film on the electrode part to deposit the solder, as shown in Figure 2.
After that, it is melted and the required amount of solder is obtained by utilizing the property that solder is drawn onto the Cr--Cu--Au vapor deposited film due to surface tension. However, the hole shape of the metal mask used at that time is circular, and the hole shape is the electrode part (Cr-Cu-
The distance between adjacent electrodes had to be at least larger than the metal mask hole diameter.
もし、隣接電極間の間隔よりメタルマスク穴径が大きく
なると、第3図に示すように、半田が隣接電極間にわた
つて蒸着されることになり、溶融後に上記隣接電極上に
分離される半田量にバラツキが生じることは明白である
。一方、半導体は工C、LS工と高密度となり、歩留り
向上の点からも電極部相互間の間隔は、小さくなる傾向
にあり従来の円形の穴形状をもつメタルマスクでは必要
な半田量が得られなくなつてきた。そこで、本発明はメ
タルマスクの穴形状を円形でなく隣接電極にじやまにな
らない方向に伸長し長円形もしくは楕円等の穴形状とす
ることにある。If the metal mask hole diameter is larger than the distance between adjacent electrodes, as shown in Figure 3, the solder will be deposited between the adjacent electrodes, and the solder will be separated on the adjacent electrodes after melting. It is clear that variations in quantity occur. On the other hand, semiconductors have become denser with process C and LS processes, and in order to improve yields, the spacing between electrode parts tends to become smaller, and the required amount of solder cannot be achieved with conventional metal masks with circular hole shapes. I've become unable to do it. Therefore, the present invention aims at making the hole shape of the metal mask not circular but elongated in a direction that does not interfere with the adjacent electrodes, such as an oval or an ellipse.
このような方法を用いると、すくなくとも電極部のCr
−Cu−Au蒸着膜径以上の間隔が隣接電極間にあれば
必要な半田量を得ることができる。次に具体例について
第4図を用いて説明する。半導体基板1土に電極5が第
4図aのごとく配置されている時、隣接電極間の間隔が
せまく、従来の円形の穴形状をもつメタルマスクでは必
要な半田量が得られないとすると、第4図bのごとく電
極を再配置し、電極間隔を広げる必要が生じる。また、
その方法によつても十分な電極間隔が得られない時には
、半導体基板そのものの大きさを大きくする必要にせま
られる。これは、半導体基板の歩留り低下、コストの上
昇を招くことになる。第4図cは本発明によるメタルマ
スクを用いる場合の図であり、隣接する電極に接近しな
い方向に伸長した長円形の穴形状としたものである。こ
の方法によると従来の半導体基板がそのまま使用できる
大きな利点がある。以上説明したごとく、本発明のメタ
ルマスクを用いると従来のワイヤーボンデイングされて
いた半導体基板をそのまま使用できる利点が発生するた
め、特別なマスク変更、歩留りの低下等を防ぎその結果
半導体基板のコスト上昇を最小限におさえられるととも
に、接続法を従来のワイヤーボンデイングからワイヤレ
スボンデイングに容易に変更できる。When such a method is used, at least the Cr of the electrode part can be removed.
-If the distance between adjacent electrodes is equal to or larger than the diameter of the deposited Cu-Au film, the required amount of solder can be obtained. Next, a specific example will be explained using FIG. 4. When the electrodes 5 are arranged on the semiconductor substrate 1 as shown in FIG. 4a, the distance between adjacent electrodes is so small that the required amount of solder cannot be obtained with a conventional metal mask having a circular hole shape. It becomes necessary to rearrange the electrodes and widen the electrode spacing as shown in FIG. 4b. Also,
Even with this method, if sufficient electrode spacing cannot be obtained, it becomes necessary to increase the size of the semiconductor substrate itself. This results in a decrease in the yield of semiconductor substrates and an increase in cost. FIG. 4c shows a case where the metal mask according to the present invention is used, and has an oval hole shape extending in a direction that does not approach adjacent electrodes. This method has the great advantage that conventional semiconductor substrates can be used as they are. As explained above, the use of the metal mask of the present invention has the advantage of allowing the use of conventional wire-bonded semiconductor substrates as is, thereby preventing special mask changes and yield reductions, resulting in an increase in the cost of semiconductor substrates. In addition to minimizing the amount of noise, the connection method can be easily changed from traditional wire bonding to wireless bonding.
なお本発明の穴形状は、上記具体例の長円に限定される
ものではなく、他の形状を用いても同様な効果が得られ
ることは言うまでもない。Note that the hole shape of the present invention is not limited to the ellipse of the above specific example, and it goes without saying that similar effects can be obtained even if other shapes are used.
第1図は半田蒸着のプロセスを示す断面図、第2図は半
田溶融状態を示す断面図、第3図は電極間隔による差を
示す平面図および断面図、第4図a−cは従来製品と本
考案による方法によつて製造された製品とを比較するた
めの平面図である。
1・・・・・・半導体基板、2・・・・・・Al電極部
、3・・・・・・絶縁膜、4・・・・・・Cr−Cu−
Au蒸着用メタルマスク、5・・・・・・Cr−Cu−
Au蒸着膜、6・・・・・・半田蒸着用メタルマスク、
7・・・・・・半田蒸着膜。Figure 1 is a cross-sectional view showing the solder deposition process, Figure 2 is a cross-sectional view showing the solder melting state, Figure 3 is a plan view and cross-sectional view showing the difference due to electrode spacing, and Figures 4 a-c are conventional products. FIG. 3 is a plan view for comparison between the product manufactured by the method according to the present invention and the product manufactured by the method according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Al electrode part, 3... Insulating film, 4... Cr-Cu-
Metal mask for Au deposition, 5...Cr-Cu-
Au evaporation film, 6...metal mask for solder evaporation,
7...Solder vapor deposition film.
Claims (1)
導体基板上の電極部に半田バンブを形成する方法におい
て、前記メタルマスクの穴形状を前記電極部に最も近く
隣接する電極部には接近しない方向に伸長させた形状と
することを特徴とする半導体基板上の電極部に半田バン
ブを形成する方法。1. In a method of forming a solder bump on an electrode part on a semiconductor substrate by using a metal mask and melting solder after vacuum evaporation, the hole shape of the metal mask does not approach the electrode part closest to the electrode part. A method of forming a solder bump on an electrode portion on a semiconductor substrate, the method comprising forming a solder bump into a shape extending in a direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50143965A JPS5935178B2 (en) | 1975-12-05 | 1975-12-05 | Method of forming solder bumps on electrodes on semiconductor substrates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50143965A JPS5935178B2 (en) | 1975-12-05 | 1975-12-05 | Method of forming solder bumps on electrodes on semiconductor substrates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5268366A JPS5268366A (en) | 1977-06-07 |
| JPS5935178B2 true JPS5935178B2 (en) | 1984-08-27 |
Family
ID=15351161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50143965A Expired JPS5935178B2 (en) | 1975-12-05 | 1975-12-05 | Method of forming solder bumps on electrodes on semiconductor substrates |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5935178B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3631230B2 (en) * | 2002-11-21 | 2005-03-23 | 富士通株式会社 | Method for forming spare solder |
| JP4210171B2 (en) | 2003-02-25 | 2009-01-14 | 京セラ株式会社 | Flip chip type IC manufacturing method |
-
1975
- 1975-12-05 JP JP50143965A patent/JPS5935178B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5268366A (en) | 1977-06-07 |
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