Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS5935181B2 - Hybrid integrated circuit device - Google Patents
[go: Go Back, main page]

JPS5935181B2 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS5935181B2
JPS5935181B2 JP52014375A JP1437577A JPS5935181B2 JP S5935181 B2 JPS5935181 B2 JP S5935181B2 JP 52014375 A JP52014375 A JP 52014375A JP 1437577 A JP1437577 A JP 1437577A JP S5935181 B2 JPS5935181 B2 JP S5935181B2
Authority
JP
Japan
Prior art keywords
integrated circuit
terminal
hybrid integrated
circuit device
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52014375A
Other languages
Japanese (ja)
Other versions
JPS5399465A (en
Inventor
和夫 小笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP52014375A priority Critical patent/JPS5935181B2/en
Publication of JPS5399465A publication Critical patent/JPS5399465A/en
Publication of JPS5935181B2 publication Critical patent/JPS5935181B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は混成集積回路装置に関し特にビームリード又は
バンプ構造の半導体集積回路を基板実装してなる混成集
積回路装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which a semiconductor integrated circuit having a beam lead or bump structure is mounted on a substrate.

従来、混成集積回路装置における所要の回路の集積化は
以下の手順でおこなわれる。まず当該回路に使用する半
導体部品、コンデンサおよび抵抗等の回路接続を確認し
、この段階で前記当該回路の平面配置をおこなう。この
平面配置において重畳配線として利用できるのは搭載部
品の下部に限定される。このため、従来当該回路の混成
集積回路装置を構成するには以下の3通りの構成法が考
えられた。1 重畳配線が必要な個所を切断し、両切断
個所を外部端子として出し外部にて接続する。
Conventionally, integration of required circuits in a hybrid integrated circuit device is performed in the following steps. First, the circuit connections of semiconductor components, capacitors, resistors, etc. used in the circuit are confirmed, and at this stage the planar arrangement of the circuit is performed. In this planar arrangement, the area that can be used as superimposed wiring is limited to the lower part of the mounted component. For this reason, conventionally, the following three configuration methods have been considered for configuring a hybrid integrated circuit device of this circuit. 1 Cut the part where overlapping wiring is required, take out both cut parts as external terminals, and connect them externally.

2 重畳配線が必要な個所を切断し、両切断個所に内部
端子用電極を形成し、ジャンパー線等を用いて前記内部
端子用電極間の相互接続をおこなう。
2. Cut the parts where overlapping wiring is required, form internal terminal electrodes at both cut parts, and interconnect the internal terminal electrodes using jumper wires or the like.

3 混成集積回路に用いる薄膜あるいは厚膜導体を有す
る膜基板の導体構成を2層またはそれ以上とし、各導体
膜間に一部穴の開いた絶縁層をもうけ、この一部穴の開
いた部分により各導体層層間の接続をおこない重畳配線
をおこなう。
3 The conductor structure of a film substrate having a thin film or thick film conductor used in a hybrid integrated circuit is two or more layers, and an insulating layer with a hole partially formed between each conductor film is provided, and the portion where the hole is partially formed is Connections are made between each conductor layer and superimposed wiring is performed.

前記第1の構成法は、混成集積回路の外部端子数を増加
させる。このため当該回路を構成する混成集積回路装置
の外形寸法が増加し、実装上の問題が生じ、かつ価格の
上昇が伴う等の欠点がある。前記第2の構成法は当該回
路を構成する混成集積回路装置の外部端子数は回路構成
上必要な数で十分である。しかしながら前記第2の構成
法では数ケ所以上の相互接続に必要なジャンパー線が挿
入されるため、混成集積回路装置の組立が複雑となる欠
点がある。前記第3の構成法では当該回路の混成集積回
路用膜基板に、幾層もの導体層および絶縁層が必要とな
るため、膜基板の製造が複雑となる欠点がある。
The first configuration method increases the number of external terminals of the hybrid integrated circuit. For this reason, there are drawbacks such as an increase in the external dimensions of the hybrid integrated circuit device constituting the circuit, problems in mounting, and an increase in price. In the second configuration method, the number of external terminals of the hybrid integrated circuit device constituting the circuit is sufficient for the circuit configuration. However, in the second configuration method, jumper wires necessary for interconnection at several locations or more are inserted, which has the disadvantage that assembly of the hybrid integrated circuit device becomes complicated. The third construction method requires multiple layers of conductor layers and insulating layers for the hybrid integrated circuit membrane substrate of the circuit, which has the disadvantage that manufacturing of the membrane substrate is complicated.

従来の混成集積回路装置の構成法には前記の如き欠点を
有していよため、当該回路の実装状態および集積度等を
考慮して、前記第1、第2および第3の構成法によりい
ずれかの構成法を用いてきた。
Conventional methods for configuring hybrid integrated circuit devices have the above-mentioned drawbacks. I have been using this construction method.

本発明の目的は上述した従来の混成集積回路装置の欠点
を改善し、当該集積回路用膜基板寸法を減小し、組立が
容易である混成集積回路装置を提供するものである。
SUMMARY OF THE INVENTION An object of the present invention is to improve the drawbacks of the conventional hybrid integrated circuit device described above, to reduce the size of the membrane substrate for the integrated circuit, and to provide a hybrid integrated circuit device that is easy to assemble.

本発明による混成集積回路装置は、少なくとも1つの電
気的に素子において無関係な空端子を含む端子がほぼ同
−平面上に形成された半導体素子が基板上に実装されて
なる混成集積回路装置において、前記空端子の少なくと
も1つが基板上に設けられ、かつ半導体素子の下部を走
る配線導体に接続されていることを特徴とするものであ
る。
A hybrid integrated circuit device according to the present invention is a hybrid integrated circuit device in which a semiconductor element in which terminals including at least one electrically unrelated empty terminal are formed substantially on the same plane is mounted on a substrate. At least one of the vacant terminals is provided on the substrate and connected to a wiring conductor running under the semiconductor element.

あるいは本発明による混成集積回路装置は少なくとも1
本以−Lの空端子を有するビームリード又はバンプ構造
の半導体集積回路素子を、前記空端子のうち少なくとも
1本以上が混成集積回路を構成する膜基板における相互
配線導体に接続され、前記空端子の下部を通り6前記半
導体集積回路の下部を配線領域として使用することを特
徴とするものである。本発明によれば6半導体素子にお
ける空端子を用いることにより,何らの端子の配置の変
更を要せずに,すなわち標準化された端子配置形状のま
までこの素子の下面にかかる空端子と接続させた相互配
線のための配線導体を設けることができるため混成集積
回路の小型化が可能であると共に6該空端子の存在のた
めに半導体素子の実装強度の向上6半導体素子の放熱性
も向上せしめることができるものである。
Alternatively, the hybrid integrated circuit device according to the invention comprises at least one
In this article, a semiconductor integrated circuit element having a beam lead or bump structure having empty terminals of L is connected to a mutual wiring conductor in a film substrate constituting a hybrid integrated circuit, and at least one of the empty terminals is 6, and the lower part of the semiconductor integrated circuit is used as a wiring area. According to the present invention, by using the empty terminals in the six semiconductor elements, it is possible to connect the empty terminals on the bottom surface of this element without changing the arrangement of the terminals, that is, with the standardized terminal arrangement shape unchanged. Since it is possible to provide wiring conductors for mutual wiring, it is possible to miniaturize the hybrid integrated circuit, and due to the presence of the empty terminals, the mounting strength of the semiconductor element is improved.6 The heat dissipation of the semiconductor element is also improved. It is something that can be done.

以下図面を用いて本発明の詳細を説明する。The details of the present invention will be explained below using the drawings.

第1図は一般的な入出力平衡型増幅回路例を示す。増幅
回路1は理想入出力平衡増幅回路であり帰還路2により
帰還増幅回路構成となつている。端子11および端子1
2はそれぞれ第1および第2の入力端子を表わし6端子
13および端子14はそれぞれ第1および第2の出力端
子を表わしている。端子15および端子16はそれぞれ
電源電圧印加端子を表わしている。電源電圧が1種類の
ときは端子15を正電源に接続し、端子16を接地する
か、端子15を接地し.端子16を負電源に接続する。
電源電圧が2種類のときは端子15を第1の電源に接続
し端子16を第2の電源に接続する。この入出力平衡型
増幅回路例の外部利得はRS/Bsである。このように
、外部利得が帰還路2の抵抗RSと抵抗RFの比により
決まるため集積化する際に混成集積回路構成とするのが
好ましい。もし半導体集積回路装置内に帰還路の抵抗R
Sと抵抗RFを収めると、外部利得は一義的に決まり,
汎用性に欠けることになり,また抵抗RSおよび抵抗R
Fに拡散抵抗を使用した場合は外部利得の精度も問題と
なる。このような入出力平衡増幅回路を従来の混成集積
回路装置として構成するには増幅回路1をビームリード
構造半導体集積回路とし6帰還路2を膜集積回路とし.
組立てて当該混成集積回路装置とするもので、ここでビ
ームリード構造半導体集積回路の端子配置としては第2
図の如き例が一般的である。端子21および端子22は
理想入出力平衡増幅回路のそれぞれ第1および第2の入
力端子を表わし,端子23および端子24はそれぞれ第
1および第2の出力端子を表わしている。端子25およ
び端子26は第1および第2の電源電圧端子である。第
2図のビームリード構造半導体集積回路と帰還路2を組
合せた混成集積回路装置の構成を第3図に示す。
FIG. 1 shows an example of a general input/output balanced amplifier circuit. The amplifier circuit 1 is an ideal input/output balanced amplifier circuit, and has a feedback amplifier circuit configuration with the feedback path 2. Terminal 11 and terminal 1
2 represents the first and second input terminals, respectively, and 6 terminals 13 and 14 represent the first and second output terminals, respectively. Terminal 15 and terminal 16 each represent a power supply voltage application terminal. When there is only one type of power supply voltage, connect terminal 15 to the positive power supply and ground terminal 16, or ground terminal 15. Connect terminal 16 to the negative power supply.
When there are two types of power supply voltages, terminal 15 is connected to the first power supply and terminal 16 is connected to the second power supply. The external gain of this input/output balanced amplifier circuit example is RS/Bs. In this way, since the external gain is determined by the ratio between the resistor RS and the resistor RF in the feedback path 2, it is preferable to use a hybrid integrated circuit configuration when integrating the circuit. If the feedback path resistance R in the semiconductor integrated circuit device
When S and resistance RF are included, the external gain is uniquely determined,
This results in a lack of versatility, and the resistors RS and R
When a diffused resistor is used for F, the accuracy of external gain also becomes a problem. To configure such an input/output balanced amplifier circuit as a conventional hybrid integrated circuit device, the amplifier circuit 1 is a beam lead structure semiconductor integrated circuit and the feedback path 2 is a film integrated circuit.
The hybrid integrated circuit device is assembled into the hybrid integrated circuit device, and the terminal arrangement of the beam lead structure semiconductor integrated circuit is as follows.
The example shown in the figure is common. Terminal 21 and terminal 22 represent the first and second input terminals, respectively, of the ideal input/output balanced amplifier circuit, and terminal 23 and terminal 24 represent the first and second output terminals, respectively. Terminal 25 and terminal 26 are first and second power supply voltage terminals. FIG. 3 shows the configuration of a hybrid integrated circuit device in which the beam lead structure semiconductor integrated circuit shown in FIG. 2 and the feedback path 2 are combined.

第3図の端子番号はそれぞれ第1図および第2図の端子
番号に対応している。第3図には重畳配線を2ケ所含ん
でいることは明らかである。かかる重畳配線を避けるた
め6こは6第2図におけるビームリード構造半導体集積
回路の端子23と端子25を置換し,端子24と端子2
6を置換すればよい。しかしなから,かかる端子配置は
入力端子21と出力端子23が相互に接近し,他の入力
端子22と他の出力端子24も相互に接近しているため
電気的および熱的に好ましくない。次に本発明による重
歇配線を避け、かつ電気的および熱的に好ましい混成集
積回路装置の一例を第4図に示す。第4図は第2図のビ
ームリード構造半導体集積回路を本発明に従い変更を加
え、空端子41と空端子42を追加し,さらに重畳配線
を避けるため膜導体14と13をビームリード構造半導
体集積回路1′の下面になるように形成したものである
。第4図において,斜線部分は膜基板に構成された膜導
体を表わし6破線による斜線部分はビームリード構造半
導体集積回路Vの下部に形成された相互配線のための膜
導体を表わす。第4図の端子番号は第3図にそれぞれ対
応している。第5図は第4図のY−Y′平面の断面図で
ありビームリード構造半導体集積回路1′と膜基板上の
膜導体が絶縁されていることを表わしている。このよう
に第1図の入出力平衡増幅回路例を混成集積回路装置と
するに際し6本発明による空端子を利用した実装構成に
よれば重量配線を除去でき,その効果は顕著である。第
2の実施例を第6図aおよびbに示す。
The terminal numbers in FIG. 3 correspond to the terminal numbers in FIGS. 1 and 2, respectively. It is clear that FIG. 3 includes overlapping wiring at two locations. In order to avoid such overlapping wiring, terminals 23 and 25 of the beam lead structure semiconductor integrated circuit in FIG. 2 are replaced, and terminals 24 and 2 are replaced.
6 should be replaced. However, such a terminal arrangement is electrically and thermally unfavorable because the input terminal 21 and the output terminal 23 are close to each other, and the other input terminal 22 and the other output terminal 24 are also close to each other. Next, FIG. 4 shows an example of a hybrid integrated circuit device according to the present invention which avoids double wiring and is electrically and thermally preferable. FIG. 4 shows the beam lead structure semiconductor integrated circuit shown in FIG. 2 modified according to the present invention by adding empty terminals 41 and 42, and in order to avoid overlapping wiring, film conductors 14 and 13 are integrated into the beam lead structure semiconductor integrated circuit. It is formed so as to be on the bottom surface of the circuit 1'. In FIG. 4, the shaded area represents the membrane conductor formed on the membrane substrate, and the area shaded by six broken lines represents the membrane conductor for interconnection formed under the beam lead structure semiconductor integrated circuit V. The terminal numbers in FIG. 4 correspond to those in FIG. 3, respectively. FIG. 5 is a sectional view taken along the Y-Y' plane of FIG. 4, and shows that the beam lead structure semiconductor integrated circuit 1' and the film conductor on the film substrate are insulated. As described above, when the input/output balanced amplifier circuit example of FIG. 1 is made into a hybrid integrated circuit device, heavy wiring can be eliminated by the mounting configuration using empty terminals according to the present invention, and the effect is remarkable. A second embodiment is shown in Figures 6a and b.

第6図aはビームリード構造半導体集積回路であり6第
6図bはその等価回路である。
FIG. 6a shows a beam lead structure semiconductor integrated circuit, and FIG. 6b shows its equivalent circuit.

端子64および端子68は空端子を表わし.端子67は
この集積回路のサブストレート端子を表わしている。第
7図に第6図aの集積回路と膜基板により構成された混
成集積回路装置の構成例を示す。第7図において端子6
1から端子68および端子6Vから端子68′はそれぞ
れ第6図aの複合回路に対応している。端子71および
端子72はそれぞれ第1および第2の入力端子であり端
子73および端子74はそれぞれ第1および第2の出力
端子である。端子75および端子76は電源電圧端子で
ある。77は定電流源である。
Terminal 64 and terminal 68 represent empty terminals. Terminal 67 represents the substrate terminal of this integrated circuit. FIG. 7 shows an example of the configuration of a hybrid integrated circuit device constituted by the integrated circuit shown in FIG. 6a and a membrane substrate. In Figure 7, terminal 6
1 to terminal 68 and terminal 6V to terminal 68' respectively correspond to the composite circuit of FIG. 6a. Terminal 71 and terminal 72 are first and second input terminals, respectively, and terminal 73 and terminal 74 are first and second output terminals, respectively. Terminal 75 and terminal 76 are power supply voltage terminals. 77 is a constant current source.

第7図において破線で示してあるのは第1の実施例と同
じく、前記複合回路の下部を用いた膜導体による配線を
示している。このように第2の実施例から空端子をビー
ムリード構造半導体回路に少なくとも1個所以上設けて
おくのは混成集積回路装置にとり重畳配線を解消するの
に非常に有効なことは明らかである。以上詳細に述べた
如く、本発明を用いればジアッパー線を使用せず電気的
および熱的に安定で組立の容易な混成集積回路装置を提
供できる。なお以上の説明ではビームリード型半導体集
積回路素子を実装した場合について示したが,ビームリ
ード型以外でも例えばバンプ型半導体素子についても全
く同様に本発明を適用できることは勿論である。
In FIG. 7, broken lines indicate wiring by membrane conductors using the lower part of the composite circuit, as in the first embodiment. It is clear from the second embodiment that providing at least one vacant terminal in the beam lead structure semiconductor circuit is very effective in eliminating overlapping wiring in a hybrid integrated circuit device. As described in detail above, by using the present invention, it is possible to provide a hybrid integrated circuit device that is electrically and thermally stable and easy to assemble without using zipper wires. In the above description, the case where a beam-lead type semiconductor integrated circuit element is mounted has been described, but it goes without saying that the present invention can be applied to semiconductor elements other than the beam-lead type, for example, bump type semiconductor elements in the same manner.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の集積回路素子を示す構成図6第2図はそ
の平面外観図.第3図.第4図および第5図は本発明の
第1の実施例の説明図、第6図A,bはそれぞれ第2の
実施例で用いた実装される集積回路の平面図および回路
図,第7図は本発明の第2の実施例による混成集積回路
の構成図である。
Figure 1 is a configuration diagram showing a conventional integrated circuit element. Figure 2 is a plan view of its external appearance. Figure 3. 4 and 5 are explanatory diagrams of the first embodiment of the present invention, FIGS. 6A and 6B are respectively a plan view and a circuit diagram of an integrated circuit to be mounted used in the second embodiment, and FIG. The figure is a configuration diagram of a hybrid integrated circuit according to a second embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 少なくとも1つの空端子を含む端子がほぼ同一面上
に形成された半導体素子が基板上に実装されてなる混成
集積回路装置において、前記空端子の少なくとも1つが
、前記基板上に設けられ、かつ前記半導体素子の下部を
走る配線導体に接続されていることを特徴とする混成集
積回路装置。
1. In a hybrid integrated circuit device in which a semiconductor element in which terminals including at least one vacant terminal are formed on substantially the same surface is mounted on a substrate, at least one of the vacant terminals is provided on the substrate, and A hybrid integrated circuit device, wherein the hybrid integrated circuit device is connected to a wiring conductor running under the semiconductor element.
JP52014375A 1977-02-10 1977-02-10 Hybrid integrated circuit device Expired JPS5935181B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52014375A JPS5935181B2 (en) 1977-02-10 1977-02-10 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52014375A JPS5935181B2 (en) 1977-02-10 1977-02-10 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5399465A JPS5399465A (en) 1978-08-30
JPS5935181B2 true JPS5935181B2 (en) 1984-08-27

Family

ID=11859289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52014375A Expired JPS5935181B2 (en) 1977-02-10 1977-02-10 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5935181B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61199492U (en) * 1985-06-03 1986-12-13

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60106363U (en) * 1983-12-22 1985-07-19 ソニー株式会社 printed wiring board
JPH07302963A (en) * 1995-02-10 1995-11-14 Ibiden Co Ltd Printed-wiring board for surface mounting

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61199492U (en) * 1985-06-03 1986-12-13

Also Published As

Publication number Publication date
JPS5399465A (en) 1978-08-30

Similar Documents

Publication Publication Date Title
US4074342A (en) Electrical package for lsi devices and assembly process therefor
JPS5935181B2 (en) Hybrid integrated circuit device
JPH01185943A (en) Semiconductor integrated circuit device
JP2824329B2 (en) Variable capacitance diode device
US4646125A (en) Semiconductor device including Darlington connections
JPS6127691A (en) Internal wiring structure of magnetoresistance element
JPH04127464A (en) Power supply capacitor cell for integrated circuit device of master slice layout
JPS5988863A (en) Semiconductor device
JPS584463B2 (en) Hand-held hand warmer
JPH0249731Y2 (en)
JPH0451488Y2 (en)
JPS5861652A (en) Semiconductor device
JPS6161259B2 (en)
JPH0223008Y2 (en)
JP2001203428A (en) Surge protection circuit
JPH02260561A (en) Semiconductor device
JPS6347248B2 (en)
JPH0342685Y2 (en)
JPS5889875A (en) Josephson integrated circuit
JPS6366066B2 (en)
JPS6081852A (en) Semiconductor device
JPS60120542A (en) Semiconductor device
JPS63304645A (en) Semiconductor integrated circuit
JPH0338052A (en) Semiconductor integrated circuit device and manufacture thereof
JPH0430541A (en) Semiconductor device