JPS6366066B2 - - Google Patents
Info
- Publication number
- JPS6366066B2 JPS6366066B2 JP58210350A JP21035083A JPS6366066B2 JP S6366066 B2 JPS6366066 B2 JP S6366066B2 JP 58210350 A JP58210350 A JP 58210350A JP 21035083 A JP21035083 A JP 21035083A JP S6366066 B2 JPS6366066 B2 JP S6366066B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- hole
- current
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/641—Combinations of only vertical BJTs
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 本発明は半導体集積回路に関する。[Detailed description of the invention] The present invention relates to semiconductor integrated circuits.
従来、第1図に示す様な電流源回路では、第1
のトランジスタ1のエミツタ3の面積及び抵抗5
の値を基準とし、第2のトランジスタ2のエミツ
タ4の面積をn倍とし抵抗6の値を1/nとして、
第1のトランジスタ1に流れるエミツタ電流のn
倍のエミツター電流が第2のトランジスタ2に流
れる様に構成されている。この為、トランジスタ
の形状、方向を揃え、素子間の整合をとつたり、
さらに温度分布を考慮して第2図に示した様に第
1のトランジスタ1のエミツタ面積を基準として
n/2倍のエミツタ面積になる様な2つの電位ト
ランジスタ2′及び2″を両側にレイアウトし、こ
れによつて第1図の第2のトランジスタ2を実現
し、第2のトランジスタ2′及び2″のエミツタ4
及び4′をスルーホール10,11を用いて配線
し、n倍のエミツタ面積の第2のトランジスタと
した。抵抗5,6には、配線50,51が横切つ
ている。この場合、トランジスタ2′及び2″のエ
ミツタ4及び4′の配線は、第2のトランジスタ
2′のエミツタ4を一層配線で直接抵抗6に接続
し、その一層配線の途中にスルーホール10を設
ける。トランジスタ2″のエミツタ4′にスルーホ
ール11を設け、そのスルーホール10及び11
を2層配線で接続する。第1のトランジスタ1は
直接、一層配線で抵抗5に接続している。スルー
ホールの抵抗をも考慮した第2図のレイアウトの
等価回路を第3図に示した。 Conventionally, in a current source circuit as shown in Fig. 1, the first
The area of the emitter 3 of the transistor 1 and the resistance 5
Based on the value of , the area of the emitter 4 of the second transistor 2 is multiplied by n, and the value of the resistor 6 is set to 1/n, and the emitter current flowing through the first transistor 1 is n.
The structure is such that twice the emitter current flows through the second transistor 2. For this reason, it is necessary to align the shape and direction of the transistors and achieve matching between elements.
Furthermore, considering the temperature distribution, two potential transistors 2' and 2'' are laid out on both sides so that the emitter area is n/2 times the emitter area of the first transistor 1, as shown in Figure 2. In this way, the second transistor 2 of FIG. 1 is realized, and the emitters 4 of the second transistors 2' and 2'' are
and 4' are wired using through holes 10 and 11 to form a second transistor with an emitter area n times larger. Wirings 50 and 51 cross the resistors 5 and 6. In this case, the wiring for the emitters 4 and 4' of the transistors 2' and 2'' is such that the emitter 4 of the second transistor 2' is directly connected to the resistor 6 by a single layer wiring, and a through hole 10 is provided in the middle of the first layer wiring. A through hole 11 is provided in the emitter 4' of the transistor 2'', and the through holes 10 and 11
Connect with two-layer wiring. The first transistor 1 is directly connected to the resistor 5 by a single layer wiring. FIG. 3 shows an equivalent circuit of the layout of FIG. 2, taking into account the resistance of the through holes.
第3図に於て抵抗5及び6の端40及び41と
各トランジスタのエミツタ3,4,4′間の電圧
降下即ちスルーホール抵抗による電圧降下Vthと
トランジスタのVBEによる電圧降下をVBErとし、
また、端子8と端子7間の電圧をVB、第1のト
ランジスタ1のエミツタ電流を、トランジスタ
2′及び2″のエミツタ電流を第1のトランジスタ
1のエミツタ電流のn/2倍、抵抗5,6は抵抗
値R及びR/n、スルーホール抵抗はRthとすると
各々トランジスタVBEは
トランジスタ1のVBE=VB−R5×I
トランジスタ2′のVBE=VB−2R6×n/2
トランジスタ2″の
VBE=VB−(2R6+Rth22+Rth23)×nI/2
となる。これより第1のトランジスタ1のVBE
と、トランジスタ2″のVBEには、スルーホール
抵抗Rthの電圧降下が含まれている事は明らかで
ある。この様にスルーホール抵抗の電圧降下によ
り、VBEが減少しn倍の電流比が精度よく実現出
来ないという欠点があつた。 In Figure 3, the voltage drop between the ends 40 and 41 of resistors 5 and 6 and the emitters 3, 4, and 4' of each transistor, that is, the voltage drop due to the through-hole resistor V th and the voltage drop due to the transistor V BE , is expressed as V BEr. year,
Also, the voltage between terminals 8 and 7 is V B , the emitter current of the first transistor 1 is n/2 times the emitter current of the first transistor 1, the emitter current of transistors 2' and 2'' is n/2 of the emitter current of the first transistor 1, and the resistor 5 is , 6 are the resistance values R and R/n, and the through-hole resistance is R th.The transistor V BE is as follows: V BE of transistor 1 = V B −R 5 ×I V BE of transistor 2′ = V B −2R 6 × V BE of n/2 transistor 2''=V B -(2R6+R th 22+R th 23)×nI/2. From this, V BE of the first transistor 1
It is clear that the voltage drop of the through-hole resistor R th is included in the V BE of the transistor 2''. In this way, due to the voltage drop of the through-hole resistor, V BE decreases and the current increases by n times. The drawback was that the ratio could not be achieved with high precision.
本発明の目的は、かかる問題点を解決し、スル
ーホール抵抗による電圧降下を揃え、VBEを等し
くする事により精度のよい電流比を得る回路を提
供することにある。 It is an object of the present invention to provide a circuit that solves these problems and obtains a highly accurate current ratio by equalizing voltage drops caused by through-hole resistors and equalizing V BE .
本発明の半導体集積回路は、基準の電流が流れ
る第1のトランジスタのエミツタから第1の基準
電位点への電圧降下を、基準のn倍の電流が流れ
る第2のトランジスタのエミツタから第1又は第
2の基準電位点との間に入るスルーホールの数を
第1のトランジスタのエミツタと第1の基準電位
点に入るスルーホールのn倍個にすることによ
り、第2のトランジスタのエミツタから第1又は
第2の基準電位点への電位降下と等しくしたこと
を特徴とする。 In the semiconductor integrated circuit of the present invention, the voltage drop from the emitter of the first transistor through which a reference current flows to the first reference potential point is reduced from the emitter of the second transistor through which a current n times the reference current flows to the first or second transistor. By increasing the number of through holes that enter between the emitter of the first transistor and the second reference potential point to n times the number of through holes that enter between the emitter of the first transistor and the first reference potential point, It is characterized in that the potential drop is equal to the potential drop to the first or second reference potential point.
以下に図面を用いて本発明について詳細に説明
する。 The present invention will be explained in detail below using the drawings.
第4図は第1図の回路に対するレイアウトの本
発明による一実施例である。 FIG. 4 is an embodiment of the layout for the circuit of FIG. 1 according to the present invention.
第4図においては第1のトランジスタ1のエミ
ツタ3は、スルーホール12を設け、二層配線及
びスルーホール13を経て一層配線により、抵抗
5と接続する第1のトランジスタ1、n倍のエミ
ツタ電流の流れるトランジスタをそれぞれn/2の
エミツタ電流の流れる第2のトランジスタ2及び
第3のトランジスタ2′の2つに分ける。配線5
0,51が抵抗5,6を横切る為そのエミツタ4
及び4′は、n/2倍個のスルーホール10,1
1、二層配線をへてn/2倍個のスルーホール14
に接続され、一層配線で抵抗6に接続される。こ
のレイアウトを等価回路に示すと第5図の様にな
る。今、スルーホール抵抗20〜25の抵抗値を
それぞれrthとし、抵抗6及び5の抵抗値をR,
R/nとする、端子8と端子nの電圧をVBとし、第
1のトランジスタ2″のエミツタ電流33をn/2I
である。第5図を説明するため第6図を考える。
第6図に於て、aは基準となる第1のトランジス
タ1のエミツタ3につながる配線の等価回路であ
る。bは第2のトランジスタ2のエミツタ4につ
ながる配線の等価回路を示す。ここでスルーホー
ル抵抗による電位降下Vthで第6図のaのVtr31
と第6図のbのVtr30とを比べると、第6図の
aのVtr31は
Vtr31=rth×I
第6図のbのVtr30は
Vtr30=rth×2/n×nI/2=rth×I
となり、スルーホール抵抗による電圧降下Vtrは
同様にしてVtr30′,31′も等しくなる。この
電位降下は一層から二層に用いる時のスルーホー
ル抵抗によるもの30,31と二層から一層に用
いる時のスルーホール抵抗によるもの30′,3
1′とがあり、あたかもVBEを減少させる様な影
響をあたえる、スルーホールの電位降下はこのふ
たつの和でありVtr35及び36になる。この電
圧降下の和Vtr35及び36は、Vtr30,31及
び30′,31′が等しいので等しい。ここで第5
図に再び戻り基準となる第1のトランジスタ1の
エミツタ3と端子40間の電圧降下35と第2ト
ランジスタ2′及び第3のトランジスタ2″のエミ
ツタ4及び4′と端子41間の電位降下36とは
等しくまたひとつのスルーホールに流れる電流も
同一であるので、スルーホール自身による発熱も
一定となる。 In FIG. 4, the emitter 3 of the first transistor 1 is provided with a through hole 12, and connected to the resistor 5 through two-layer wiring and a through-hole 13 through one-layer wiring, and the emitter current of the first transistor 1 is n times The transistor through which n/2 flows is divided into two transistors, a second transistor 2 and a third transistor 2', through which n/2 emitter current flows. Wiring 5
Since 0,51 crosses resistors 5,6, its emitter 4
and 4' are n/2 times the number of through holes 10,1
1. It is connected to n/2 times as many through holes 14 through two-layer wiring, and connected to the resistor 6 through one-layer wiring. This layout is shown in an equivalent circuit as shown in FIG. Now, let the resistance values of through-hole resistors 20 to 25 be r th , and the resistance values of resistors 6 and 5 be R,
R/n, the voltage at terminal 8 and terminal n is V B , and the emitter current 33 of the first transistor 2'' is n/2I. To explain FIG. 5, consider FIG.
In FIG. 6, a is an equivalent circuit of wiring connected to the emitter 3 of the first transistor 1 serving as a reference. b shows an equivalent circuit of wiring connected to the emitter 4 of the second transistor 2. Here, the potential drop V th due to the through-hole resistance is V tr 31 in a of Fig. 6.
Comparing with V tr 30 in b of Fig. 6, V tr 31 in a in Fig. 6 is V tr 31 = r th ×I, and V tr 30 in b in Fig. 6 is V tr 30 = r th × 2/n×nI/2=r th ×I, and the voltage drop V tr due to the through-hole resistance is similarly equal for V tr 30' and 31'. This potential drop is due to the through-hole resistance when using from the first layer to the second layer 30, 31, and due to the through-hole resistance when using from the second layer to the single layer 30', 3
1', and the potential drop of the through hole, which has an effect as if to reduce V BE , is the sum of these two, and becomes V tr 35 and 36. The sums of voltage drops V tr 35 and 36 are equal because V tr 30, 31 and 30', 31' are equal. Here the fifth
Returning to the diagram again, the voltage drop 35 between the emitter 3 of the first transistor 1 and the terminal 40, which serves as a reference, and the potential drop 36 between the emitters 4 and 4' of the second transistor 2' and the third transistor 2'' and the terminal 41 Since the current flowing through each through hole is also the same, the heat generated by the through hole itself is also constant.
これまでに詳細に説明した様に各々トランジス
タのエミツタと抵抗の間には、基準となるトラン
ジスタのエミツタと端子40間と同じ電圧降下を
生じるのでn倍のエミツタ電流をとる場合スルー
ホール抵抗のエラーが含まれる事なく、またひと
つのスルーホールに同一電流を流す事により、発
熱に対して均一になるので、電流による抵抗の変
化も同一となり、スルーホールを入れる事による
電流の整合に対する影響はなくなる。この為n倍
の電流を得る回路を得る事が容易にできるという
効果がある。 As explained in detail so far, the same voltage drop occurs between the emitter of each transistor and the resistor as between the emitter of the reference transistor and terminal 40, so if the emitter current is n times larger, the error in the through-hole resistor occurs. By passing the same current through one through hole, the heat generation becomes uniform, so the change in resistance due to the current is also the same, and there is no effect on current matching due to the insertion of through holes. . For this reason, there is an effect that it is possible to easily obtain a circuit that obtains n times as much current.
第1図はカレントミラーの一例を示す回路図、
第2図は、第1図の一従来例の半導体集積回路を
示す部分平面図、第3図は第2図の等価回路図、
第4図は第1図の本発明による一実施例の半導体
集積回路を示す部分平面図、第5図は第4図の等
価回路、、第6図aは第1のトランジスタのエミ
ツタにつながる配線の等価回路、同図bは、第2
のトランジスタにつながる配線の等価回路を示
す。
1,2,2′……トランジスタ、3,4,4′…
…エミツタ、5,6……抵抗、7,8……端子、
10,11,12,13,14……スルーホー
ル、20,21,22,23,24,25……ス
ルーホール抵抗、30,31……スルーホールに
よる電圧降下、32,33……エミツタ電流、3
4……二層配線、35,36……エミツタと抵抗
間の電圧、50,51……アルミ配線。
Figure 1 is a circuit diagram showing an example of a current mirror.
2 is a partial plan view showing a conventional semiconductor integrated circuit shown in FIG. 1, FIG. 3 is an equivalent circuit diagram of FIG. 2,
4 is a partial plan view showing a semiconductor integrated circuit according to an embodiment of the present invention shown in FIG. 1, FIG. 5 is an equivalent circuit of FIG. 4, and FIG. 6a is a wiring connected to the emitter of the first transistor. The equivalent circuit of
The equivalent circuit of the wiring connected to the transistor is shown. 1, 2, 2'...transistor, 3, 4, 4'...
...Emitter, 5, 6...Resistor, 7, 8...Terminal,
10, 11, 12, 13, 14... Through hole, 20, 21, 22, 23, 24, 25... Through hole resistance, 30, 31... Voltage drop due to through hole, 32, 33... Emitter current, 3
4...Two-layer wiring, 35, 36... Voltage between emitter and resistor, 50, 51... Aluminum wiring.
Claims (1)
準の電流が流れる第1のトランジスタのエミツタ
から第1の基準電位点への電圧降下と、基準のn
倍の電流が流れる第2のトランジスタのエミツタ
から前記第1の基準電位点への電圧降下を、第1
のトランジスタのエミツタと前記第1の基準電位
点との間に入るスルーホールのn倍個のスルーホ
ールを第2のトランジスタのエミツタと、第1の
基準電位点間に入れたことにより等しくしたこと
を特徴とする半導体集積回路。1 In a semiconductor integrated circuit using multilayer wiring, the voltage drop from the emitter of the first transistor through which the reference current flows to the first reference potential point, and the reference n
The voltage drop from the emitter of the second transistor through which twice the current flows to the first reference potential point is
The number of through holes inserted between the emitter of the second transistor and the first reference potential point is made equal by n times the number of through holes inserted between the emitter of the second transistor and the first reference potential point. A semiconductor integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58210350A JPS60102764A (en) | 1983-11-09 | 1983-11-09 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58210350A JPS60102764A (en) | 1983-11-09 | 1983-11-09 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60102764A JPS60102764A (en) | 1985-06-06 |
| JPS6366066B2 true JPS6366066B2 (en) | 1988-12-19 |
Family
ID=16587939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58210350A Granted JPS60102764A (en) | 1983-11-09 | 1983-11-09 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60102764A (en) |
-
1983
- 1983-11-09 JP JP58210350A patent/JPS60102764A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60102764A (en) | 1985-06-06 |
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