JPS5937579B2 - Semiconductor device with metal protrusions - Google Patents
Semiconductor device with metal protrusionsInfo
- Publication number
- JPS5937579B2 JPS5937579B2 JP54084642A JP8464279A JPS5937579B2 JP S5937579 B2 JPS5937579 B2 JP S5937579B2 JP 54084642 A JP54084642 A JP 54084642A JP 8464279 A JP8464279 A JP 8464279A JP S5937579 B2 JPS5937579 B2 JP S5937579B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- electrode terminal
- semiconductor device
- film
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
半導体素子上に設けられた電極端子から外部端子へ電気
的接続を行なう手段として従来のワイヤーボンディング
法に替り、近年ワイヤレスボンディング法が注目されて
きている。DETAILED DESCRIPTION OF THE INVENTION In recent years, a wireless bonding method has been attracting attention in place of the conventional wire bonding method as a means for electrically connecting an electrode terminal provided on a semiconductor element to an external terminal.
このワイヤレスボンディング法は前記電極端子上に外部
端子である多数の電極リードを一度に接続出来る(いわ
ゆるギャングボンディング)ため、量産化、信頼性向上
が期特出来る。ワイヤレスボンディング法として種々の
方式があるが、本発明は半導体素子の電極端子上へバリ
アメタルを介して金属突起物を形成し、前記金属突起物
と外部リード端子とを加熱、加圧する事によつて接続す
るフィルムキャリヤ方式等に用いられる半導体装置に関
するものである。This wireless bonding method allows a large number of electrode leads, which are external terminals, to be connected to the electrode terminals at once (so-called gang bonding), so mass production and improved reliability can be achieved. There are various wireless bonding methods, but the present invention involves forming metal protrusions on the electrode terminals of a semiconductor element via a barrier metal, and heating and pressurizing the metal protrusions and external lead terminals. The present invention relates to a semiconductor device used in a film carrier method, etc., which is connected by a wire.
まず、従来の半導体素子上に金属突起物を形成した装置
の構造、製造方法を第1図で説明する。First, the structure and manufacturing method of a conventional device in which metal protrusions are formed on a semiconductor element will be explained with reference to FIG.
熱酸化膜、を有する半導体素子2上にアルミニウム配線
パターンが設けられ、このアルミニウム配線パターンは
同一材料で構成されるアルミニウム電極端子3と接続さ
れる。更に前記アルミニウム配線パターンを保護するた
めに全面にCVDSiO2膜4を被着せしめ、アルミニ
ウム電極端子3上のみを光蝕刻法によつて開孔する。次
いでCr一Cu等の複数層からなるバリヤメタル5を真
空蒸着法により連続蒸着によつて形成し、更にこのバリ
アメタルをメッキ電極として選択的にAu、Cu等の金
属突起物6を10〜30μmの高さに形成する。そして
バリアメタル5を選択的に除去し、第1図の半導体装置
が形成される。次に金属突起物6と例えばSnメッキさ
れたCuリード゛端子11とを位置合せし、加圧、加熱
すれば、金属突起物がAuであれば、Au−Snの共晶
によつて、接触面附近は合金化し、第2図のごとく外部
に機械的、電気的な接続を得る事が出来る。An aluminum wiring pattern is provided on a semiconductor element 2 having a thermal oxide film, and this aluminum wiring pattern is connected to an aluminum electrode terminal 3 made of the same material. Further, in order to protect the aluminum wiring pattern, a CVDSiO2 film 4 is deposited on the entire surface, and holes are formed only on the aluminum electrode terminals 3 by photolithography. Next, a barrier metal 5 consisting of multiple layers of Cr-Cu, etc. is formed by continuous vacuum deposition, and this barrier metal is used as a plating electrode to selectively coat metal protrusions 6 of Au, Cu, etc. with a thickness of 10 to 30 μm. Form to height. Then, the barrier metal 5 is selectively removed, and the semiconductor device shown in FIG. 1 is formed. Next, by aligning the metal protrusion 6 and, for example, the Sn-plated Cu lead terminal 11, and applying pressure and heat, if the metal protrusion is Au, contact will be established due to the Au-Sn eutectic. The area near the surface is alloyed, and mechanical and electrical connections to the outside can be obtained as shown in Figure 2.
ところがこの加圧、加熱する工程によつて、金属突起物
6に著しく圧力が加わる。However, due to this pressurizing and heating process, significant pressure is applied to the metal protrusion 6.
この圧力裔お虫常、金属突起物6の平面積が30×50
μm程度のもので約20Vの圧力を必要とする。すなわ
ち1300に9/cwiもの圧力が加わる。この圧力が
金属突起物6に対して全加圧が垂直12に加わつたり、
加圧治具の横すベーあるいはリード゛端子11の横すベ
ーによつて金属突起物6の横方向13に加圧される。本
発明者らの検討によれば前者の圧力の場合にはCVDS
iO,膜4が金属突起物6と電極端子3との間にはさま
れて、クラツク6′が発生することが判明した。更に後
者の圧力の場合には、金属突起物6が軟らかい電極端子
3を横方向におしやり(変形)、このために堅(℃VD
SK)2膜4にクラツク6′l)1発生する。そして、
クラツク6′より外部から腐蝕性溶液が浸入すれば金属
突起物6の下にある電極端子3は腐蝕され、金属突起物
6の附着強度を著じるしく低下さすばかりでなく、電気
的不良をも発生させる結果になつていた。In this case, the flat area of the metal protrusion 6 is 30 x 50.
A pressure of approximately 20V is required for a diameter of about μm. That is, a pressure of 9/cwi is applied to 1300. This pressure is applied to the metal protrusion 6 in the vertical direction 12,
Pressure is applied in the lateral direction 13 of the metal protrusion 6 by the horizontal base of the pressing jig or the horizontal base of the lead terminal 11 . According to the inventors' study, in the case of the former pressure, CVDS
It was found that the iO film 4 was caught between the metal protrusion 6 and the electrode terminal 3, causing cracks 6'. Furthermore, in the case of the latter pressure, the metal protrusion 6 forces (deforms) the soft electrode terminal 3 in the lateral direction, thereby causing it to become hard (°CVD
A crack 6'l)1 occurs in the SK)2 film 4. and,
If a corrosive solution enters from the outside through the crack 6', the electrode terminal 3 under the metal protrusion 6 will be corroded, which will not only significantly reduce the adhesion strength of the metal protrusion 6 but also cause electrical failure. It also resulted in the occurrence of
本発明は外部リードとの接続の際の加圧によつて生じる
CVDSiO2膜のクラツクを積極的に防止し、信頼性
の高い金属突起物を有する半導体装置を提供するもので
ある。The present invention actively prevents cracks in the CVDSiO2 film caused by pressure during connection with external leads, and provides a semiconductor device having highly reliable metal protrusions.
第3図によつて本発明の一実施例にかかる半導体装置お
よびその製造方法を説明する。A semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be explained with reference to FIG.
半導体素子(図示せず)が形成されたSi等の半導体基
板21に設けた酸化膜22上に半導体基板21内に形成
した各機能素子群を電気的に接続するためにアルミニウ
ム配線パターン(図示せず)が形成され、基板21の端
部のアルミニウム配線パターンは電極端子23となる。
次にアルミニウム配線パターンを電気的あるいは機械的
に保護するためにCVDSiO,膜24が全面に被着さ
れ、前記電極端子23上には外部との接続のために端子
23よりも大き目に光蝕刻法によりCVDSiO2膜2
4に開孔部25が形成される(第3図A,b)。An aluminum wiring pattern (not shown) is formed on an oxide film 22 provided on a semiconductor substrate 21 made of Si or the like on which semiconductor elements (not shown) are formed in order to electrically connect each functional element group formed in the semiconductor substrate 21. ) is formed, and the aluminum wiring pattern at the end of the substrate 21 becomes the electrode terminal 23.
Next, a CVDSiO film 24 is deposited on the entire surface of the aluminum wiring pattern to electrically or mechanically protect it, and a film 24 made of CVDSiO is deposited on the entire surface of the electrode terminal 23 using photoetching to form a film larger than the terminal 23 for connection with the outside. CVDSiO2 film 2
An opening 25 is formed in 4 (FIG. 3A, b).
次に開孔部25を含め全面にCr−Cu,Cr一Ni等
で構成されるバリヤメタル層26を真空蒸着法により連
続して形成し、光蝕刻法により前記CVDSiO,の開
孔部25よりも大きい領域にバリヤメタル層26を残存
させる(第3図C,d)。Next, a barrier metal layer 26 made of Cr-Cu, Cr-Ni, etc. is continuously formed on the entire surface including the openings 25 by vacuum evaporation, and the barrier metal layer 26 is formed on the entire surface including the openings 25 by photolithography. The barrier metal layer 26 is left in a large area (FIG. 3C, d).
この工程により電極端子23の全領域とCVDSiO2
膜240一部の領域を覆う如くにバリヤメタル層26が
形成される。次いでバリヤメタル層26上に選択的に電
解メツキ法によりAu,Cu等の金属突起物27を形成
すれば第3図eの構造を得る事が出来る。Through this step, the entire area of the electrode terminal 23 and the CVDSiO2
A barrier metal layer 26 is formed to cover a portion of the film 240. Next, by selectively forming metal protrusions 27 of Au, Cu, etc. on the barrier metal layer 26 by electrolytic plating, the structure shown in FIG. 3e can be obtained.
第3図eの如くの構成であれば、金属突起物27と電極
端子23との間にCVDSiO2膜が介在していないと
ともに、第2図で説明した様に外部リードと金属突起物
との接合の際に生じる電極端子23の変形に伴なうCV
DSiO2のクラツク発生がない。したがつてアルミニ
ウム配線パターンと接続されている電極端子23の腐蝕
が発生しないから金属突起物の強度の低下および電気的
不良等による信頼性の低下が生じない。以上のように、
本発明は電極端子部の上に絶縁膜がないため、この保護
用絶縁膜のクラツクの発生をなくすることができ、金属
突起物を有する半導体装置に大きく寄与するものである
。With the configuration as shown in FIG. 3e, there is no CVDSiO2 film interposed between the metal protrusion 27 and the electrode terminal 23, and the connection between the external lead and the metal protrusion is prevented as explained in FIG. CV due to deformation of the electrode terminal 23 that occurs during
No cracks occur in DSiO2. Therefore, corrosion of the electrode terminals 23 connected to the aluminum wiring pattern does not occur, so that there is no reduction in the strength of the metal protrusions and reliability due to electrical defects. As mentioned above,
Since the present invention does not have an insulating film on the electrode terminal portion, it is possible to eliminate the occurrence of cracks in the protective insulating film, and this invention greatly contributes to semiconductor devices having metal protrusions.
第1図は従来の金属突起物を有する半導体装置の断面図
、第2図は従来の構成で接合時に発生したCVDSiO
,膜のクラツクによる電極端子の腐蝕を示す断面図、第
3図は本発明の一実施例にかかる半導体装置の製造工程
図でA,c,eは断面図、B,dはそれぞれA,cの平
面図である。
21・・・・・・半導体基板、22・・・・・・酸化膜
、23・・・・・・電極端子、24・・・・・・CVD
SiO,膜、25・・・・・・開孔部、26・・・・・
・バリアメタル層、27・・・・・・金属突起物。Figure 1 is a cross-sectional view of a conventional semiconductor device with metal protrusions, and Figure 2 is a conventional configuration with CVDSiO generated during bonding.
, a sectional view showing corrosion of an electrode terminal due to cracks in the film, and FIG. FIG. 21... Semiconductor substrate, 22... Oxide film, 23... Electrode terminal, 24... CVD
SiO, membrane, 25...opening, 26...
- Barrier metal layer, 27...metal protrusion.
Claims (1)
護する絶縁膜が前記Al配線パターンの電極端子部より
も大きい開孔部を前記電極端子部近傍に有すると共に、
前記開孔部近傍に被着形成されりバリヤメタルの領域が
、前記開孔部よりも大きく、かつ金属突起物と前記バリ
ヤメタルとの接触面が前記開孔部よりも小さい事を特徴
とする金属突起物を有する半導体装置。1. An insulating film that protects an Al wiring pattern formed on a semiconductor element has an opening larger than an electrode terminal portion of the Al wiring pattern near the electrode terminal portion, and
A metal protrusion formed in the vicinity of the aperture, wherein a region of the barrier metal is larger than the aperture, and a contact surface between the metal protrusion and the barrier metal is smaller than the aperture. A semiconductor device that has an object.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54084642A JPS5937579B2 (en) | 1979-07-04 | 1979-07-04 | Semiconductor device with metal protrusions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54084642A JPS5937579B2 (en) | 1979-07-04 | 1979-07-04 | Semiconductor device with metal protrusions |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS568850A JPS568850A (en) | 1981-01-29 |
| JPS5937579B2 true JPS5937579B2 (en) | 1984-09-11 |
Family
ID=13836338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54084642A Expired JPS5937579B2 (en) | 1979-07-04 | 1979-07-04 | Semiconductor device with metal protrusions |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5937579B2 (en) |
-
1979
- 1979-07-04 JP JP54084642A patent/JPS5937579B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS568850A (en) | 1981-01-29 |
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