JPS593758B2 - Multiple envelope signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for generating an envelope signal for controlling the pitch, timbre, volume, etc. of a musical tone signal of an electronic musical instrument.
To provide a multiple envelope signal generator capable of simultaneously generating a large number of envelope waveforms having a plurality of time divisions and having different time constants for partial waveforms in each time division by operating in double time division multiplexing. The purpose is to

Conventionally, music synthesizers use ADSR signals as envelope signals.

Here, A means the attack section, D means the decay section, S means the sustain section, and R means the release section. In addition to this, ADRR waveforms have also been proposed.
(99647, Japanese Patent Application No. 49-125002) In many conventional devices, the time constants of partial waveforms in each time segment of ADSR and ADRR are set using separate variable resistors.

Therefore, in order to create many types of ADSR waveforms,
Either reset the settings each time using the variable resistor above, or
It was necessary to provide many types of predetermined fixed resistances and to switch between them. Also, in general, music synthesizers
Better sound can be created by using separate envelope signals for timbre control and volume control, but in conventional systems, two sets of envelope signals are generated in order to generate two ADSR signals. This required a container, which was extremely inconvenient. The present invention provides an excellent multiple envelope signal generator that can generate a plurality of envelope signals and can electrically set the time constants of the partial waveforms as desired.

First, an overview of the present invention will be explained. According to the present invention, the time constant of each partial waveform of the envelope signal is set by a charging/discharging circuit using a control resistor and a capacitor, a filter using a multiplier and an integrator, or the like. Then, in order to charge and discharge the power supply, a charging power source and a discharging power source are connected to the control resistor and the multiplier, and a control signal (voltage, current, digital code, etc.). In addition, the application of the charging power source and the discharging power source and the application of the control signal are performed by each of the above A
In addition to being switched for each time segment of the DSR signal,
The pulses of the multiplexing signal source are switched to be time division multiplexed. The number of capacitors to be multiplexed is equal to the number of capacitors to be multiplexed, and they are switched depending on the type of envelope signal. As a result, the control resistors and multipliers are used while being switched by control signals that are multiplexed in two ways: waveform multiplexing based on time divisions and time division multiplexing.
Next, we will outline its configuration.

The multiple envelope signal generator of the present invention includes an envelope generating means for generating an envelope signal by charging and discharging the voltages of a plurality of charging/discharging capacitors, a setting means for setting the charging/discharging speed, and a charging/discharging power supply. , comprising a control means including a multiplexed signal source and a logic circuit, wherein the control means performs switching control of the charging/discharging power source and setting of the charging/discharging speed synchronously, and the setting means is time-divided. The capacitor is characterized in that it is operated in a multiplexed manner so that the capacitors generate separate envelope signals. More specifically, the charging/discharging power source includes at least one charging power source, at least one discharging power source, and a changeover switch, and the setting means includes a time constant setting circuit and a control signal source for setting the value of the time constant. The envelope generating means includes a first multiplexer, the envelope generating means includes the plurality of capacitors and an analog multiplexer selectively connecting the capacitors, and the control means includes the multiplexed signal source, the logic circuit, the voltage comparator, and a second a multiplexer, applies the charging power source and the discharging power source to the changeover switch to perform selection switching, and applies the output of the changeover switch to a time constant circuit mainly composed of the time constant setting circuit and the capacitor. The voltage comparator compares the output of the envelope generating means based on the charge/discharge voltage of the capacitor with a predetermined comparison voltage to obtain a comparison pulse. A trigger pulse generated by the above logic circuit is applied to the logic circuit, each state of the sequence created by the trigger pulse and the comparison pulse is memorized, and multiplexed sets of logic outputs are outputted. The output is multiplexed by the second multiplexer and applied to the changeover switch, the logic output and the output of the multiplexed signal source are added to the first multiplexer, the output of the control signal source is multiplexed, and the output is multiplexed at the above time. The charging and discharging time constants are sequentially switched by applying the voltage to the constant setting means, and the 1,000 yapacitor is configured such that one of them is selectively connected by applying the output of the multiplexed signal source to the analog multiplexer,
Envelope signals of the number of multiplexed waveforms specified by the charging power source, discharging power source, and control signal source are obtained in a time-division multiplexed form or in a parallel form. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic electrical connection diagram of an embodiment of the present invention.
In this embodiment, three types of ADSR type envelope signals are generated simultaneously. In FIG. 1, 100 is a multiplexed signal source, and a three-phase multiplexed signal φ1
, φ2, φ3 collectively generate 3φ. Charging power supply VCC
The first discharge power supplies S, VS2, VS3 and the second discharge power supply (ground) are applied to the changeover switch 16. 1st
The discharge power supplies VS.1, S2, and VS3 are time-division multiplexed by an analog multiplexer 14 and sent via a pusher 15 to a field effect transistor (hereinafter referred to as FE) of a changeover switch 16.
T) applied to the QD. A charging power source Vcc and a second discharging power source are connected to FETQA and QR, respectively. This 2
The two power supplies are common to the three envelope waveforms and are therefore not multiplexed. The other ends of the FETs QA, QD, and QR are connected to each other and to one end of a control resistor 20 forming a time constant setting circuit of the time constant circuit 200. The time constant circuit 200 is a FET in the analog multiplexer 21.
Three capacitors C which are sequentially switched by a switch
1, C2, C3 and the control resistor 20, the first-order low-pass filter or integrator is constructed with a thousand-yapacitor C.
The inter-terminal voltages VCl, VC2, and VC3 of I, C2, and C3 are output from the buffer 22 to the output terminal 27 via the multiplexer 21. In this case, the output V of the buffer 22
Ovt is a multiplexed envelope signal as described below. The multiplexed envelope signal VOvt is demultiplexed by an analog demultiplexer 28,
Output terminals 24, 25, as three types of envelope signals
26, respectively. The multiplexed envelope signal VOvt is further applied to the voltage comparator 23 and compared with the comparison voltage Vp, and the multiplexed envelope signal VOvt is
A positive pulse CM is output every time vt exceeds the comparison voltage Vp. Since the positive pulse CM is time-division multiplexed, it is applied to the digital demultiplexer 10 to demultiplex it, convert it into three comparison pulses CM1, CM2, and CM3, and apply them to the logic circuit 400. The logic circuit 400 uses the comparison pulses CMl, CM2, CM3 and the trigger pulse KG generated by pressing a key on a keyboard as human information, and outputs a pulse corresponding to the time division of the envelope signal. Configured for signals. In other words, the logic circuit 400 includes three RS flip-flops 3, 4, and 5 with clear terminals CL, and AND gates 7,
8, 9, an inverter 6, and a differentiating circuit 2 for detecting the rising edge of the trigger pulse KG. Logic circuit 400 is not multiplexed and has attack pulses Al and A corresponding to the time divisions of each envelope waveform.
2, A3, decay pulses Dl, D2, D3 and a common release pulse RE. Release pulse RE
is output in common to each envelope waveform. 5
Attack pulses Al, A2, and A3 are multiplexed three times by the digital multiplexer 18 and applied to the gate of FETQA, turning FETQA ON and OFF.

The decay pulses Dl, D2, and D3 are applied to the digital multiplexer 17, multiplexed, and applied to the gate of FET QD, turning FET QD8OM and OFF. Since there is only one type of release pulse RE, it is the same as multiplexing without multiplexing, and it is directly applied to the gate of FETQR. VA applied to analog selectors 11, 12, 13}VRl (5VA29VD29VR2
and VA39VD3, VR3 are three sets of control signal sources, which are voltage sources in this embodiment.

These control signal sources are controlled by the control resistor 20 depending on their voltage values.
Before being applied, first multiplexing is performed by analog selectors 11, 12, and 13, and second multiplexing is performed by analog multiplexer 19. It is done. First, taking the analog selector 11 as an example, the V
Select Al and V by decay pulse D. VRl is selected by the release pulse RE. The attack pulse A1 becomes 81' only in the attack time segment of the ADSR signal, and the decay pulse D1 becomes 81' only in the attack time segment of the ADSR signal.
It is 81" only in the decay and sustain time sections of the signal, and the release pulse RE is 61" in the non-key press time and release section. Therefore, the output of the analog selector 11 is 81" for each of the first envelope. Control signals Al, Dl, and VRl corresponding to the time divisions are selected sequentially. Analog selectors 12 and 13 also operate in the same way as analog selector 11. Outputs of these analog selectors 11, 12, and 13 are sent to analog multiplexer 19. This multiplexed control signal switches and controls the resistance value of the control resistor 20 one after another in a time division manner.Next, each component in FIG. 1 will be explained.

Figure 2a shows a circuit example of the digital multiplexers 17 and 18, and three-phase multiplexed signals of φ1, φ2, and φ3 as shown in Figure 2b are applied to one terminal of each of the three AND gates. However, the digital signals to be multiplexed are applied to each of the remaining input terminals, one for each of the three input terminals in total, and the outputs of the three AND gates are added to the OR gate to calculate the logical sum of them. It is composed of FIG. 3 is a circuit example of the digital demultiplexer 10,
A multiplexed signal 3φ is applied to one input terminal of each of the three AND gates, a multiplexed digital signal is applied to each of the remaining input terminals, and a demultiplexed signal is obtained from the output of the AND gate. It is configured so that Fourth
The figure shows a circuit example of analog selectors 11, 12, and 13.

Control signals VA, VD, V are applied to the drains of each of the three FETs.
R is applied.

An attack pulse A1, a decay pulse D1, and a release pulse R are applied to the gates of the three FETs for VA, VD, and VR.

The sources of each FET are commonly connected. In this way, analog human power VA, VD, and VR are sequentially multiplexed. The configuration of the analog selector shown in FIG. 4 can also be used as the analog multiplexer 19. In this case, the analog signals to be multiplexed may be applied as analog manual input, and the multiplexed signal 3φ may be applied in place of each pulse of the attack pulse A1, the decay pulse D1, and the release pulse R. Figure 5 shows the analog demultiplexer 28
This is an example of a circuit. This corresponds to the input and output of the analog selector shown in FIG. 4 being reversed. Each of the three output terminals is provided with a circuit that combines low-pass filtering, smoothing, and hold functions using a resistor r and a capacitor C, and when connected to the output terminals 24, 25, and 26, three smooth ADSR signals are output separately. It can be taken out.

Next, the operation of this embodiment will be explained in two stages.

First, as a first step, the sequential operation for creating each time segment of the ADSR signal will be explained without fully considering multiplexing, and then, as a second step, the multiplexing operation will be explained. First, the process of generating the first ADSR signal will be explained.

The first ADSR signal waveform occurs at φ1.
The control signal sources associated with this are VAl, VDl, VSl,
VRl, logic circuit related pulses are CM,,Al,Dl
, REl output signal voltage is VCl. FIG. 6 shows each waveform. First, when no key is pressed, KG is 80°, so flip-flop 3 is cleared.

Therefore, A1 is 60'' and D is 0-REbabi. Therefore, the analog selector 11 selects VRl and applies it to the control resistor 20 through the analog multiplexer 19 at φ1. The changeover switch 16 is a FETQR
only becomes ON, and the charge of the capacitor C1 is discharged through the analog multiplexer 21 and the control resistor 20 at φ1. Therefore, the output voltage VOv of the buffer 22
t is 0V. Therefore, the output CM of the voltage comparator 23 is "0", and the output CM of the digital multiplexer 10
l is also 10゛. When the key is pressed and KG becomes 1°, the set pulse S or the flip-flop 3 is set via the differentiating circuit 2. Therefore, A1 is 61-D1
”, RE also becomes 80°. At this time, VAl is applied to the control resistor 20 at φ1.
Output ゛. Therefore, the changeover switch 16 selects the charging voltage Vcc at φ1. Since capacitor C1 is selected at φ1, the resistance value R of control resistor 20
The time constant of Al and capacitor C1 begins. This charge is φ
This is done only in 1. At φ2 and φ3, the capacitor C1 holds the previous charge. Time constant RA,C
When l is small, the first φ1 is sufficient to charge the battery, as shown by VCl in FIG. If the time constant RAlC is large, VOl rises to a sufficiently large voltage after passing through φ1 several times. When Vc exceeds the comparison voltage Vp, the comparison pulse CM becomes ``V''. When the comparison pulse CM becomes 1", CMl also becomes "r" at the timing of φ1. Therefore, the flip-flop 3 is reset. This is the attack interval. When it is reset, A1 becomes 1.
0-D1 becomes F', RE becomes O', and is in the decay and sustain sections. In the control resistor 20, at φ1,
Control voltage VDl is applied through analog selector 11 and analog multiplexer 19, and the resistance value becomes RDl. Selector switch 16 is FETQA, QR or 0FF,F
ETQD becomes 0N, and the first discharge power supply VSl, VS2
, VS3, VS1 is selected for φ1. Therefore, the charge on capacitor C1 is equal to the time constant RDlC
It is discharged to voltage S1 at 1. The discharge process is a decay period, and the period after sufficient discharge is a sustain period. Next, when the key is released and KG becomes ``O'' again, flip-flop 3 is cleared and A1 becomes ``O''.
”, D1 becomes O”, RE becomes 1”. Therefore, the control resistance value becomes RRl and FETQR becomes 0N as before the key was pressed.
Therefore, the charge of capacitor C1 is equal to the time constant RRlC
The output voltage C1 eventually returns to 0V. The above is the operation in which the first ADSR signal is generated sequentially. All of the above operations are performed in the time slots of the multiplexed signal φ. For φ2 and φ3, φ
It should be noted that since the charge of the capacitor C1 at 1 is held, the resistance value of the control resistor 20 is substantially tripled. Next, the multiplexing operation will be explained in general. The same operation as in the above-mentioned φ1 is performed also in φ2 and φ3. Therefore, in the human power and output of the buffer 22, a signal is generated in which the waveform of the charging/discharging process is multiplexed in accordance with the time slots φ1, φ2, and φ3, as shown in VOvt in FIG. .
If we look at the operations involved in multiplexing in detail, we must note that the following operations occur. First, K.G.
If the time when the signal becomes 6F is at time slot φ, the first ADSR signal immediately starts to rise, but the rises of the second and third ADSR signals at time slots φ2 and φ3 are delayed. Therefore, the frequency of the multiplexed signal should be sufficiently high. Next, if the timing at which the output voltages Cl, C2, and VC3 exceed the comparison voltage Vp coincides with each time slot of the ADSR signal, the comparison pulse CM is generated within that time slot, so the decay period immediately begins. . Therefore, the maximum value of the output voltages VCl, VC2, and VC3 does not exceed P, but when they do not match the time slots or when the comparison pulse CM is not sufficiently generated within the time slot, the generation of the comparison pulse CM is as follows. Delayed until time slot. Therefore, the attack period increases by the delay time, and the output voltage C,,V
C2 and VO3 exceed the comparison voltage Vp. When the attack time constant is large, there is no practical problem because the next time slot is reached before the comparison voltage P is significantly exceeded. In addition, the input terminal of buffer 22, capacitor Cl, C2
If a limiter, such as a constant voltage diode Dz, is provided at the upper terminal of , C3 to prevent the voltage from exceeding the comparison voltage Vp, the above concern becomes unnecessary. (Example of) Ale VA2j
VA3 and DPVD2jVO3 and Rl, VR2, R3 3
Each of the sets is connected to an analog multiplexer 33, 32, 3
1, respectively, and then the analog selector 34
This is sequential multiplexing.

FIG. 8 is a schematic electrical wiring diagram of another embodiment of the present invention. In the embodiment shown in FIG. 8, key trigger signals KGl, KG2, KG using three independent keys are
3, three ADSR signals are generated at different timings. and,
The waveforms of the three ADSR signals in each time segment differ only in the time of generation or switching, but have the same time constant. Therefore, the control signals A, VD, VS
, only one set of VR is available. And the control signal Vs
are directly applied to FET QD without being multiplexed, and control signals A, D, and R are multiplexed in a single manner by an analog selector 34. Logic circuit 401 is significantly different from the embodiment of FIG. logic circuit 401
consists of three completely identical basic parts, each of which is a differentiating circuit 2-1 (2-2, 2-3), a flip-flop 3-1 (3-2, 3-3), and an inverter 6-1. 1(
6-2, 6-3), And Gate J Yoko P (7-2, 7-
3). The operation of this basic part is the first
Differential circuit 2, flip-flop 3, inverter 6,
The operation is exactly the same as when the trigger pulse KG and comparison pulse CMl are input to the AND gate 7.
There are three sets of the above basic parts, each with a trigger pulse K.
Gl, KG2, KG3 and comparison pulses CMl, CM2, C
M3 is input independently, and a set of attack pulse, decay pulse, and release pulse (Al, Dl,
Rl), (A2, D2, R2), (A3, D3, R3)
is generated. Attachment pulses Al, A2, and A3 are multiplexed by a digital multiplexer 18 and applied to FETQA and an analog selector 34. daycapulse dl
, D2, and D3 are multiplexed by the digital multiplexer 17 and applied to the FET QD and the analog selector 34.
Release pulses R1, R2, and R3 are multiplexed by a digital multiplexer 29 and applied to the FETQR and analog multiplexer 34. Since there are three trigger pulses, there are three release pulses R1 to R3 in this embodiment. Therefore, the release pulses Rl, Rsi, and R3 must also be multiplexed as described above. In this embodiment, the other parts are the same as the configuration and operation shown in FIG. 1, so explanations thereof will be omitted. In this embodiment, an ADSR signal is generated at φ1 for the trigger pulse KG, and an ADSR signal is generated at φ2 for the trigger pulse KG2.
An SR signal is created, and for trigger pulse KG3, φ
! ADSR signals are created using αν.Recently, electronic organs and music synthesizers do not have sound sources for all keys, but instead use sound sources with a number of channels corresponding to the number of fingers on the hand (for example, 10 channels), tone filters, and gates. A so-called generator assigner system has been proposed and commercialized. (Special Public Interest Publication No. 49-13409
8) In such a system, envelope signals for the number of channels described above must be generated at independent timings. This embodiment can be used in such cases. Control signal sources VA, V that set the waveform of the ADSR signal
There is an advantage that D, s, and R can be set electrically, and that they can be set commonly and simultaneously for each channel. Also,
The embodiment of FIG. 8 may be further complicated as follows.

Depending on whether the pitch range of the key is high or low, pitch range information representing the pitch range is generated, and the voltages of the control signal sources A, VD, V8, and VR are switched based on this information. The switching is
Of course, at each of the time slots φ1 to φ3 corresponding to the trigger pulses KG1 to KG3, the range information of the key at that time is supplied to the control signal source.
As a method of switching the control signal source, range information in the form of voltage may be provided to something like the control resistor 20. Also,
The control signal source may be used as an input power source for a multi-bright DAC (multiplying digital-to-analog converter), and the control signal source voltage may be switched by providing digital range information. The pitch information may be converted into data via a table such as a ROM, or in the case of analog voltage,
It may be converted to a desired voltage by a nonlinear circuit. In this way, it becomes possible to generate an optimal envelope signal depending on the sound range. For example, it is possible to generate an envelope signal that rises slowly for low tones and quickly for high tones. The embodiment shown in FIG. 8 is a method of multiplexing envelope signals corresponding to different keys.

The embodiment of FIG. 1 is a method for multiplexing a plurality of envelope signals in response to one key operation. The present invention
Necessarily, a combination of both the operations of FIG. 1 and the operations of FIG. It can also be used to generate envelopes. That is, for M independent keys, N envelope signals are simultaneously generated for each key. For this purpose, MXN may be multiplexed as a whole.
When M:Li-N=3, it becomes as follows. First, each of the three basic parts of the logic circuit 401 in FIG. 8 is configured like the logic circuit 400 in FIG. 1.

With this configuration, there will be nine flip-flops and nine AND gates each. Corresponding to N=3, three control signal sources are required each for attack, decay, sustain, and release, as in FIG. The three sets of control signal sources are respectively analog multiplexers 33 and 33 in FIG.
32, 31 and the analog multiplexer 14 in FIG. Ru.

Furthermore, the N=3 decay pulses and attack pulses multiplexed by the digital multiplexers 17 and 18 in FIG. M-3 is multiplexed by 0), which has the same number but is different in this case. Nine capacitors are required corresponding to MXN=3X3=9, and triple multiplexing is performed twice.
For this purpose, four analog multiplexers such as 21 may be used, or an analog multiplexer including nine FETs may be used. Since the output voltage VOvt is multiplexed nine times, the analog demultiplexer 28 and digital demultiplexer 10 have one input and nine outputs. As the multiplexed signal source, one in which each of the 3φ signals shown in FIG. 2b has three phases, that is, nine pulse trains of substantially nine phases may be used. Expansion of these multiplexing systems and accompanying configuration changes can be easily made based on the basic idea of the present invention. In the present invention, for example, in the embodiment shown in FIG.
i, VSl, VRi) (121,2,3,...
), for example, k sets, and if these are switched and given using a brisset switch, various sets of 3 types of envelope signals can be generated by selecting up to 3 sets from the k sets. You can create things just by flipping a switch.

To generate the m sets of control signals, a well-known method such as a method using resistance division can be used. To select only three switches from a plurality of brisset switches, a method similar to the generator assigner described above can be used.
When envelope signals are generated using such a large number of preset control signal sources, the advantage of time-division multiplexing of control resistors as in the present invention is maximized. Things that can be used as the control resistor 20 include, for example, a resistor between the source and drain of a field effect transistor, a photocoupler using a Cds photocell and a light emitting diode, and the like.

FIG. 9 shows an example of a control resistor 20 whose resistance value is switched by a digital code. 8 resistors R, 2r, 4r,
8r, l6r, 32r, 64r, and l28r are connected in series, and a switch using an FET is provided in parallel to each resistor, and the FE
The 8-bit data applied to the gate of T
to 0N or 0FF, and 2 from OΩ to 255rΩ.
Create 56 resistance values.

To use this digitally controlled resistor 20-1, the control signal source must be a digital code. Therefore, a digital multiplexer 43 is used in place of the analog multiplexer 19, and it is necessary to multiplex control signals in digital code format (all 8 bits).
FIG. 10 shows another embodiment of the time constant circuit.

A charging/discharging power source is connected to the negative input terminal of the multiplier 51 through a changeover switch 16 via attenuators of 10KΩ and 100Ω. The output of multiplier 51 is applied to an integrator. The integrator is composed of an operational amplifier 52, three thousand capacitors Cl, C2, and C3, an analog multiplexer 21, and two resistors of 100Ω. The output of the integrator is negatively fed back to the positive input terminal of the multiplier 51 via an attenuator with resistors of 10KΩ and 100Ω. The multiplier 51 is, for example, a CA manufactured by RCA, USA.
An integrated circuit named 3O8OA may be used. When a control current is added from the gain control terminal 53, the gain of the multiplier 51 changes in proportion to the current value. Time constant circuit 20
0-1 operates as a first-order low-pass filter as a whole.
When the control current is changed, the cutoff frequency changes proportionally, so the charging/discharging time constant can be controlled by the current. In FIG. 11, the buffer 22 (FIG. 1) is not multiplexed and Bl,
Using three buffers B2 and B3, connect terminals 24, 25,
This is an example in which the demultiplexed envelope signal is directly taken out at No. 26.

Although FETQl, Q2, and Q3 are multiplexers, it is better to think of them as sample-and-hold switches. It is preferable that the human power current of the buffers B1 to B3 be as large as possible. In this case, it is also necessary to prepare three voltage comparators 23 and directly output the comparison pulses CM1, CM2, CM3 in parallel without time division multiplexing. FIG. 12 shows a part of the shape of the ridge envelope to which the present invention can be applied.

KG is the trigger pulse generated by pressing the key, ADSR is
This is the waveform explained in FIGS. 1 and 8. In addition to this, ADR
As shown by R, Attack, Decay, 1st release,
It is also possible to create a waveform composed of time segments of the second release. Since there is already a known example of this method, it is sufficient to combine it with the present invention. (Japanese Patent Application No. 49-125002) Furthermore, it is also possible to create a very simple device consisting of an attack and a release as shown in AR. In this case, most of the voltage comparators and logic circuits become unnecessary. In addition, waveforms with various sequences can be generated by increasing the types of charging power supplies, discharge power supplies, comparison voltage VP1 voltage comparators, and constructing corresponding logic circuits. The present invention can also be applied to. In the present invention, except for the output resistors Cl, C2, and C3, the control resistor 20, and the multiplier 51, the remaining parts can be easily integrated into an integrated circuit.

As a result, a compact system that generates a large number of envelope signals of a wide variety of types simultaneously or in parallel can be realized. In the embodiments shown in FIGS. 1 and 8, the voltage comparator 23 is operated by time division multiplexing, but voltage comparators are provided at the output terminals 24, 25, and 26 of the analog demultiplexer 28, respectively, for independent comparison. Pulse CMl, CM2
, CM3 may be generated and applied to the logic circuit 400.

In this way, the requirements for response speed, settling time, slew rate, etc. of the cage pressure comparator are relaxed. Furthermore, in the embodiments shown in FIGS. 1 and 8, we have so far described the case where the output of the analog demultiplexer 28 is used, but the timbre filter and gate that operate in response to the envelope signal perform similar multiplexing operations. , the multiplexed envelope signal, that is, the output V of terminal 27
It is also possible to use Ovt as is.

In addition, as shown in Fig. 1, multiple envelope signals generated simultaneously, that is, outputs appearing at terminals 24, 25, and 26, are used to modulate the pitch of the sound, the other to control the timbre, and the remaining one to modulate the pitch of the sound. Each may be used separately to control the volume.

The present invention uses a time constant circuit to perform double multiplexing of sequential multiplexing and time division multiplexing to generate multiple envelope signals simultaneously or in parallel. The following effects can be obtained.

Envelope waveform control can be made common by changing at least one voltage or code.

Therefore, one or one set of manipulators for waveform control is sufficient. Also, the preset function can be easily realized. Since the time constant circuit is used in a time-sharing manner, there is essentially less or no variation compared to using separate time constant circuits. It is easy to integrate circuits by using as few components as possible with complex configurations and operating principles, such as control resistors, and by using simple components such as digital circuits and switch circuits that are less likely to cause variations.

[Brief explanation of drawings]

FIG. 1 is a schematic electrical connection diagram of an embodiment of the multiple envelope signal generator of the present invention, FIGS. 2 to 5 are specific connection diagrams of each component of the embodiment shown in FIG. 1 is a timing chart illustrating the operation of the embodiment shown in FIG. 1, FIG. 7 is a block diagram showing another embodiment of one of the components of the embodiment shown in FIG. 9 is a diagram showing a specific configuration example of the control resistor, FIGS. 10 and 11 are diagrams showing a specific example of the time constant circuit, and FIG. FIG. 12 is a diagram of various envelope signal waveforms obtained by the present invention. 100... Multiplexed signal source, 200...
Time constant circuit, 400...Logic circuit, 11, 12
, 13... Analog selector, 16...
・Selector switch, 10, 17, 18... Digital multiplexer, 19... Analog multiplexer, 23... Voltage comparator, Vcc...
...Charging power supply, VSl to VS3...Discharging power supply (control signal source), Vp...Comparison power supply, A1 to V
A3, VDl~D3, VR, ~VR3...Control power supply (control signal source).

Claims (1)

[Scope of Claims] 1 Envelope generating means for generating an envelope signal by charging and discharging the voltages of a plurality of charging/discharging capacitors, a setting means for setting the charging/discharging speed, a charging/discharging power supply, and multiplexing a control means including a signal source and a logic circuit, the control means synchronously controls switching of the charging/discharging power source, setting the charging/discharging speed, and switching the charging/discharging capacitor; A multiple envelope signal generator, characterized in that the setting means is time-division multiplexed to cause the capacitors to generate separate envelope signals. 2. In the statement of claim 1, the charging/discharging power source includes at least one charging power source, at least one discharging power source, and a changeover switch, and the setting means sets a time constant setting circuit and the value of the time constant. The envelope generating means includes the plurality of capacitors and an analog multiplexer selectively connecting the capacitors, and the control means includes the multiplexed signal source, the logic circuit, and the voltage comparator. and a second multiplexer, which applies the charging power source and the discharging power source to the changeover switch to perform selection switching, and connects the changeover switch to a time constant circuit mainly composed of the time constant setting circuit and the capacitor. The voltage comparator compares the output of the envelope generating means based on the charge/discharge voltage of the capacitor with a predetermined comparison voltage to obtain a comparison pulse. A trigger pulse generated in accordance with the key is applied to the logic circuit, each state of a sequence created by the trigger pulse and comparison pulse is memorized, and several sets of multiplexed logic outputs are generated. The logic output is multiplexed by the second multiplexer and applied to the changeover switch, and the logic output and the output of the multiplexed signal source are added to the first multiplexer to output the control signal source. is applied to the time constant setting means to switch the charging/discharging time constant one after another, and one of the capacitors is selectively connected by applying the output of the multiplexed signal source to the analog multiplexer. a multiplexed envelope signal configured to obtain envelope signals of a multiplexed number of waveforms specified by the charging power source, the discharging power source, and the control signal source in a time division multiplexed form or in a parallel form; generator. 3. A multiple envelope signal generator according to claim 2, characterized in that the time constant setting circuit is constructed using a control resistor or a multiplier. 4. In the statement of claim 3, a voltage controlled resistor is used as the control resistor, a predetermined fixed or variable power source is used as the control signal source, and the control resistor and the capacitor form part of a charging/discharging circuit. A multiple envelope signal generator that generates charging and discharging waveforms. 5. Claim 3 provides that the output of the multiplier is supplied to an integrating circuit including the capacitor, and the output of the integrating circuit is fed back to the multiplier to form a variable time constant circuit as a whole. Multi-envelope signal generator. 6. In claim 3, a digitally controlled resistor is used as the control resistor, a predetermined fixed or variable digital code is used as the control signal source, and the digital code is multiplexed by the second multiplexer. A multiple envelope signal generator that digitally controls the resistance value of the digitally controlled resistor. 7 In the statement of claim 2, the output signals of a time constant circuit multiplexed as a voltage comparator are sequentially time-divisionally compared to output a time-division multiplexed comparison pulse, and the comparator A multiple envelope signal generator configured to demultiplex a comparison pulse and apply it to a logic circuit. 8 In the statement of claim 2, voltage comparators are provided corresponding to the number of multiplexed voltage comparators, and the output signal of the time constant circuit is demultiplexed and applied to each voltage comparator, and the respective voltages are A multiple envelope signal generator, wherein a comparison pulse output from a comparator is applied to reset a flip-flop included in the logic circuit. 9. The multiple envelope signal generator according to claim 2, which uses a voltage limiting circuit as a time constant circuit that prevents the charging voltage from exceeding a predetermined voltage. 10. The multiple envelope signal generator according to claim 2, wherein a plurality of types of control signal sources are provided, some of which are selected according to the operation of a preset switch. 11. In claim 2, the logic circuit has at least a flip-flop, the flip-flop is set by the rising edge of the trigger pulse, the flip-flop is reset by the comparison pulse, and the flip-flop is reset by the rising edge of the trigger pulse. or clear, and has a configuration in which the negative logic of the trigger pulse, the output of the flip-flop, the AND of the negative logic of the output of the flip-flop and the trigger pulse are output as a logic output,
A multiple envelope signal generator having the above configuration as many as the number of multiplexed envelopes. 12. The multiple envelope signal generator according to claim 2, which applies a common trigger pulse to the logic circuit to generate a plurality of envelope signals at the same time. 13. A multiple envelope signal according to claim 2, wherein a plurality of trigger pulses are applied to a logic circuit to generate a plurality of envelope signals in parallel according to the timing of each of the trigger pulses. generator. 14 In the description of claim 2, a plurality of trigger pulses are applied to the logic circuit to generate a plurality of envelope signals in parallel according to the timing of each of the trigger pulses, and furthermore, each trigger pulse is A multiple envelope signal generator that simultaneously generates multiple envelope signals for pulses. 15. A multiple envelope signal generator according to claim 2, comprising a demultiplexer that demultiplexes a multiplexed envelope signal into a plurality of independent envelope signals.