JPS5939070B2 - pattern recognition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a pattern recognition device, particularly for recognizing printed characters, which uses a weighted standard pattern obtained by weighting a standard pattern corresponding to a standard figure to perform matching. In the pattern recognition device, only the binary standard pattern is stored in the standard pattern memory without storing the weighted standard pattern in the standard pattern memory, and weighting is performed from the binary standard pattern at the time of matching. The present invention relates to a pattern recognition device that is configured to generate a standard pattern based on a standard pattern, thereby reducing the storage capacity of the standard pattern memory.

For example, in the recognition of printed characters, standard patterns and
The standard pattern stored in the memory and the recognition target character pattern obtained from the recognition target characters are compared by a so-called superimposition method.

In this case, even if the standard pattern and the character pattern to be recognized have exactly the same size and the patterns themselves are considered to be exactly the same, the overlay method is used to check whether the patterns match each other or not. If this is attempted, the problem of misalignment will occur as is known in the art. That is, when the above two patterns are superimposed in the correct positional relationship, the two patterns are detected as 100% matching, but for example, 1
If the two patterns are overlapped with a horizontal position shift by the mesh amount, even if the two patterns match 100%, a mismatch will occur at the location where the position shift occurs between the two patterns. It is detected as if there is an apparent mismatch between the two patterns. In general, the result of a mismatch state caused by such a positional shift and the result of a mismatch state where a mismatch occurs in the original pattern itself cannot be distinguished in the superposition of binary patterns.

However, the weighting that has been done in the past! By adopting this method, it becomes possible to distinguish between the two. In other words, in weighting, the weight is set to "O", "1", "
A standard pattern L is used such that the weight increases to 2'', and the weight decreases to 0, -1, and -2 as the weight moves away from the white area. In this way, even if the positional shift occurs to some extent during the superimposition, the mismatch caused by the positional shift has a small weight, so the total of the "weighted mismatch" will be a small value. If there is a mismatch in the original pattern itself of the - side, the above sum will be a large value because the mismatch will occur at a location with a large weight. For this reason, weighting has been conventionally applied to the standard pattern. In other words, a weighted standard pattern is prepared in which a lower weight is given to meshes located at character boundaries, and higher weights are given as the distance from the character boundary increases, and the weighted standard pattern is compared with the character pattern to be recognized. Do it like this. In this case, if weighting is performed as described above, a plurality of bits of information will be required for each mesh, and the storage capacity of the standard pattern memory will become extremely large. The present invention aims to solve the above-mentioned problems, and the pattern recognition device of the present invention weights a standard pattern corresponding to a standard figure and scans the weighted standard pattern and the figure to be recognized. In the pattern recognition device that performs matching with the recognition target figure pattern obtained from the standard figure, a standard pattern memory stores a binary standard pattern corresponding to the standard figure, and a weighting process is performed based on the contents of the standard pattern memory. a weighted mask generation circuit; and a matching circuit that receives the weighted standard pattern generated by the weighted mask generation circuit and the recognition target graphic pattern and performs a comparison between the two, and the weighted mask. When m><n mesh observation windows are superimposed on the binary standard pattern, the generating circuit generates the corresponding binary standard pattern corresponding to the pattern of the binary standard pattern observed by the observation window. It is configured to generate a predetermined weight for one predetermined mesh in the pattern, and to compare the weighted standard pattern generated by the weight mask generation circuit with the recognition target graphic pattern. It is characterized by the fact that

This will be explained below with reference to the drawings. 1A and 1B are explanatory diagrams for explaining a binary standard pattern and a weighted standard pattern according to the present invention, FIG. Figures and Figure 4A
, B, and C are explanatory diagrams for explaining processing aspects by the weighting circuit according to the present invention, and FIG. 5 shows the configuration of an embodiment of the weighting circuit.

As shown in Figure 1A, one standard figure has black mesh (represented by graphical logic "1") concentrated in the center, and white mesh (represented by graphical logic "O") in the other areas.
When we assume that we have a binary standard pattern 1 as shown in FIG. 1B, we prepare a weighted standard pattern 2 as shown in FIG.

Then, a comparison is made with a recognition target graphic pattern (not shown). The weighted standard pattern 2 shown in FIG. 1B can be considered to be generated as follows.

That is, in the binary standard pattern 1 shown in FIG. 1A, (
i) Give weight "O" to meshes that touch the figure frame, (4) Give weight "o" to meshes that touch black areas.
(Iii) weight [
(IV) A weight of "1" is assigned to a black mesh whose distance from the black mesh with a weight of "O" is equivalent to, for example, one mesh, and (V) a black mesh with a weight of "0" is assigned a weight of "1". For example, a weight of "2" is assigned to a black mesh whose distance from the mesh is equal to or more than 2 meshes, and (V1) weight [
For example, a weight of [-1] is assigned to a white mesh whose distance from the white mesh with "0" is equivalent to one mesh, and !
}For white meshes whose distance from the white mesh with weight "0" is, for example, 2 meshes or more, weight "-2"
Grant. When using the weighted standard pattern 2 generated in this way, recognition can be performed that is less susceptible to positional deviation during verification as described above.

However, each mesh of the weighted standard pattern requires three bits of information. Therefore, the storage capacity required for the standard pattern memory is three times that required for storing the binary standard pattern 1 shown in FIG. 1A. In the present invention, a binary standard pattern 1 as shown in FIG. 1A is stored on the standard pattern memory,
At the time of comparison, a weighted standard pattern 2 as shown in FIG. 1B is generated from the binary standard pattern 1, and then the comparison is performed.

FIG. 2 shows the configuration of an embodiment of the present invention, in which 1MEM is a binary standard pattern memory, 3 is a weight mask generation circuit,
4-0 and 4-1 are weighting circuits, 5 is an inversion circuit, 6
7 is a sum circuit, 7 is a black area/white area determining circuit, 8 is a matching circuit, and S is binary standard pattern 1 mesh information, in which the pattern as shown in FIG. What is output, ZO, Zl, Z2, represents 3-bit information corresponding to one mesh of the weighted standard pattern 2 (shown in FIG. 1B).

In the case of the present invention, a binary standard pattern 1 as shown in FIG.
is stored in the binary standard pattern memory 1MEM.

Needless to say, binary standard pattern memory 1MEM
Other binary standard patterns are also stored in V) 3, and one mesh information corresponding to each binary standard pattern is sequentially read out as shown in FIG. Binary standard pattern 1
#0 is led to a weighting circuit 4-0, which weights the black mesh points shown in the binary standard pattern 1 and generates an output of 2 bits XO xl for each mesh.

Further, the binary standard pattern 1 is led to the #1 weighting circuit 4-1 through the inverting circuit 5, and is weighted corresponding to the white mesh points shown in the binary standard pattern 1. , yl. Note that the processing manner and configuration of the weighting circuit 4 will be described later with reference to FIGS. 3 to 5. The respective outputs of the weighting circuits 4-0 and 4-1 are led to a summation circuit 6, and the summation circuit 6 is connected to the first
3-bit information ZO, Zl, Z2 is led to the matching circuit 8 corresponding to each mesh of the weighted standard pattern 2 as shown in FIG.

On the other hand, the figure pattern to be recognized (not shown) is the video signal VI.
It is guided in the form of a DEO to a black area/white area determining circuit 7, and the determining circuit 7 supplies mesh information that distinguishes black areas and white areas to a matching circuit 8. The matching circuit 8 compares the mesh information with the 3-bit information ZO, Zl, and Z2, and outputs one standard pattern name that matches best. Hereinafter, the processing mode and configuration of the weighting circuit 4 will be explained with reference to FIGS. 3 to 5.

Note that the weighting circuits 4-0 and 4-1 have exactly the same configuration except that the input information is inverted, and the explanation will be continued below for the weighting circuit 4-0. As shown in FIG. 2, the binary standard pattern 1 is sequentially input to the weighting circuit 4-0 in the form of one mesh (one bit) information S.

As a result, the weighting circuit 4-0 scans, for example, a 5×5 mesh observation window w in the direction of arrow B as shown in FIG. It can be thought of as weighting. In the case of the illustrated observation window W1, a weight [0] is assigned to the central mesh surrounded by the illustrated circle, and in the case of the illustrated observation window W2, a weight of ``0'' is assigned to the central mesh, and the illustrated observation In the case of window W3, a weight of "1" is given to the central mesh. FIG. 4A shows an observation window w of 5×5 meshes, and what kind of pattern the meshes [11” to “55] in the figure have when assigning weights to the mesh [33] in the center of the figure. In other words, FIG. 4B shows an example of a pattern in which the mesh of the standard pattern corresponding to mesh "33" has a weight of "2", and (1) mesh "33" is logical. 1, and (6) mesh “23”, “34”, “43”
, "32" are both theory 1, and (111) meshes "13", "24", etc.
...Since "22] is both logic "1],
A weight of "2" is given to the standard pattern mesh corresponding to mesh "33". That is, when conditional expression A is logical 1,
At that point, a weight of "2" is given to the mesh of the binary standard pattern to which the mesh "33" of the observation window w corresponds. FIG. 4C shows an example of a pattern in which the mesh of the standard pattern corresponding to mesh "33" has a weight of "1", and (!V) mesh "33" is logical 1, and ~ ) Metsuyu [33], “34”, “43
], [32] are both logic “1”, and (Vi
mesh[13], ``24'', ``35'', ``4(,
If any one of "53", "42", "31", and "22" is logic "O", mesh "3" is set.
A weight of "1" is given to the mesh of the standard pattern corresponding to "3". That is, when conditional expression B is logical "1", a weight of "1" is given to the mesh of the binary standard pattern to which mesh "33" of observation window w corresponds at that time. Furthermore, the above conditional expression A. If none of B is logical 1,
At that point, a weight "O" is given to the mesh of the binary standard pattern to which the mesh "33" of the observation window w corresponds.In the case of the #1 weighting circuit 4-1, the mesh "33" of the observation window w corresponds to the mesh of the binary standard pattern. In the binary standard pattern 1, the input signal is supplied in such a manner that a mesh which is a logic 1 becomes a logic 0, and a mesh which is a logic 0 becomes a logic 1.

Therefore, the mesh that satisfies the above conditional expression A has a weight of "-".
2" is given, and the mesh that satisfies conditional expression B is given a weight of "
-1'' is assigned, and conditional expression A. It may be considered that a weight of [0] is given to meshes that do not satisfy any of B.
FIG. 5 shows the configuration of an embodiment of the weighting circuit 4-0 (or 4-1).

The input 1-bit information S (or S) is sent to shift registers 9-1, 9-2, . . .
9-5 and are sequentially shifted. For example, the area within the thick line frame in binary standard pattern 1 shown in Figure 3 is 13×
17 meshes and is scanned by the observation window w as shown by arrow B in FIG. 3, each shift register 9-1, 9-2,...・・・・・・
, 9-5 can be considered to have a shift stage of 17 steps each. For this reason, for example, as shown in FIG.
Value standard pattern 1 advances upward from the lower right corner of the diagram and then advances upward from the bottom edge shifted one mesh to the left.
・・・・・・・・・・・・・・・..., the values of each mesh are read out and sequentially inputted as information S to the shift registers 9-1 to 9-5. During this time, the value of "11" shown in FIG. , "12", ...・・・・・・
......When observing the value of the above information S that has arrived at the positions pointed at "54" and "55", a 5x5 mesh observation window W as shown in Fig. 4A will appear. Therefore, if the binary standard pannon 1 shown in FIG. 3 is shifted from the bottom to the bottom and one mesh to the left as shown by the arrow B in the figure, it is the same as scanning from the bottom to the bottom. From this, when one mesh information S corresponding to the mesh [55] of the observation window w shown in FIG.・・・・・・・・・
・・・・・・・・・Metsushi ``11'' all at once from 9-5
, [12], ・・・・・・・・・・・・・・・ ``55
” is supplied to the weighting circuit 4-0, the values of each of the 25 meshes observed by the observation window w at the time (position) are sent to the weighting circuit 4-0 all at once. This means that it was supplied to The weighting circuit 4-0 includes an A condition determining circuit 10A and a B condition determining circuit 10.
B, and it is checked whether conditional expression A and conditional expression B shown in FIG. 4 are satisfied.

When the A conditional expression is satisfied, the A condition determining circuit 10
A outputs a logic 1. Further, when the B conditional expression is satisfied, the B condition determining circuit 10B outputs logic 1. A configuration for this can be considered to be achieved by, for example, a configuration in which the ROM is indexed using the supplied values of meshes [11'' to [55] as addresses. Decode circuit 1
0C is based on the outputs of both decision circuits 10A and 10B, and when the weight is "2", "1" or "0",
[10], [01], or "00" is output as O (or y1, YO). The summation circuit 6 shown in FIG. 2 generates 3-bit information ZO, Zl, Z2 based on the following conditions.

That is, ノ (However, "or logic") Therefore, the outputs ZO, Zl, Z2 from the sum circuit 6 are as follows.
(A) "000", "001" or [ as Z2, Zl, ZO for the black mesh in the binary standard pattern
010'' and indicates the weight [0'', r1'', or 2.

(B) For the white mesh in the binary standard pattern, either "000", "101", or "110" is emitted as Z2, Zl, ZO, and the weight is "O", [-1],
or "-2".As explained above, according to the present invention, although the weighted standard pattern 2 is used for matching, the standard pattern shown in FIG.
It is sufficient for the memory 1MEM to store the binary standard pattern 1 corresponding to each standard figure. Therefore, the memory capacity of the memory can be reduced by 1% compared to the case where the weighted standard pattern 2 is stored.

[Brief explanation of the drawing]

1A and 1B are explanatory diagrams for explaining a binary standard pattern and a weighted standard pattern according to the present invention, and FIG. FIG. 3 and FIGS. 4A, B, and C are explanatory diagrams illustrating processing aspects by the weighting circuit according to the present invention, and FIG. 5 shows the configuration of an embodiment of the weighting circuit. In the figure, 1 is a binary standard pattern, 2 is a weighted standard pattern, 1MEM is a standard pattern memory, 3 is a weight mask generation circuit, 4-0 and 4-1 are weighting circuits, respectively.
5 is an inversion circuit, 6 is a summation circuit, 8 is a matching circuit, "Z
"O, Zl, Z2" represents 3-bit information corresponding to one mesh of the weighted standard pattern.

Claims (1)

[Claims] 1. A pattern recognition device that weights a standard pattern corresponding to a standard figure and matches the weighted standard pattern with a figure pattern to be recognized obtained by scanning the figure to be recognized. a standard pattern memory storing a binary standard pattern corresponding to the standard figure;
A weighted mask generation circuit performs weighting processing based on the contents of the standard pattern memory, and a weighted standard pattern generated by the weighted mask generation circuit and the recognition target graphic pattern are inputted, and a weighting process is performed between the two. and a matching circuit that performs matching, and the weight mask generation circuit is configured to generate the binary values observed by the observation window when an m×n mesh observation window is superimposed on the binary standard pattern. It is configured to generate a predetermined weight for one predetermined mesh in the pattern in accordance with a pattern on the standard pattern, and the weighted standard pattern generated by the weight mask generation circuit and A pattern recognition device characterized in that a comparison is made with the graphic pattern to be recognized. 2. The weight mask generation circuit includes a weighting circuit corresponding to the black area of the binary standard pattern and a weighting circuit corresponding to the white area of the binary standard pattern. The pattern recognition device according to item 1.