JPS5939903B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having the functions of both a MOS transistor and a bipolar transistor.

FIG. 1 is a cross-sectional view of a conventional bipolar transistor incorporated into a MOS integrated circuit.

In Fig. 1, A, B, and C are bipolar transistors;
D is an n-channel MOS transistor, E is a p-channel MOS transistor, and 1 is a semiconductor substrate having n-type conductivity and serves as a collector region. 2, 3, and 4 are base regions formed at the same time as the P-well 26, and 5 is a highly doped n-type conductive region for connecting the collector electrode.

6, 7, and 8 are emitter regions consisting of n-type diffusion regions, n
The square regions 27 and 28 are the drain and source regions of the n-channel MOS transistor D, and are formed simultaneously.

9, 10, and 11 are highly doped p-type conductive regions for connecting the base electrode of the p-channel MOS transistor E.
The drain and source 29 and 30 are formed simultaneously.

12 is an insulating film, 13, 14, 15, 16, 17, 18,
19, 33, 34, and 35 are electrodes, and 31 and 32 are polycrystalline silicon serving as gates.

In the above integrated circuit, bipolar transistors A and B
, C base regions 2, 3, and 4 are MOS transistor P
Since it is formed simultaneously with the well 26, the threshold voltage V
The impurity concentration is set to 1017at0mS to avoid increasing T.
/C-ITL or less is normal.

For example, in the case of a silicon gate n-channel MOS transistor, the impurity in the P-well 26 must be about 2×10 16 a oms//cwL. However, in this configuration, the base width is wider than that of a normal planar bipolar transistor due to the breakdown voltage of the MOS transistor, and the DC current amplification factor β cannot be increased. In addition, even if β is increased by further lowering the impurity concentration in base regions 2, 3, and 4 to increase the emitter injection efficiency, the average lifetime of minority carriers will be reduced due to defects in the base region due to the wide base width. In other words, the width becomes shorter than the base width, and β varies depending on the element. Also, in the case of a reverse transistor in which the n-type substrate 1 is the emitter and the nf diffusion layers 6, 7, and 8 are the collectors, the n-type substrate 1 generally needs to be of low concentration due to limitations such as the threshold voltage of the p-channel MOS transistor. Therefore, the inverse β becomes small and normal operation as a transistor cannot be obtained.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks of the conventional semiconductor integrated circuit having both MOS transistors and bipolar transistors, and to obtain bipolar transistors with a simple configuration that have a high DC current amplification rate and less variation. This is what we are trying to do. In particular, since the MOS transistor has a low threshold voltage, the above-mentioned drawbacks can be effectively eliminated when both the P-well and the n-type substrate have an impurity concentration of 1017 at0 ms//CTil or less.

Now, in FIG. 2, which shows the manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention, FIGS. 2A to 2D show the same reference numerals as those in FIG.

First, as shown in FIG. 2a, an n-channel M is formed on an n-type substrate 1.
P well 26 and p type region 10 for OS transistor
0 and a silicon gate 31 is formed.

This p-type region 100 becomes the base region of bipolar transistors A and B. That is, the base region of the transistors is formed in common. Thereafter, as shown in b, the high concentration n-type conductive regions 101 and 102 are selectively diffused. At this time, as shown in b, the high concentration n-type region 101
, 102 do not need to reach the bottom of the p-type region 100. Next, in the n-channel MOS transistor D, the source and drain 27, 28, in the bipolar transistors A, B, the emitters (or collectors) 6, 7 made of high concentration n-type conductive regions, and the region 5 for taking out the collector electrode. , forming highly doped p-type conductive regions 9 and 10 for taking out the base electrode.

Due to the diffusion process at this time, the previously formed n
The + regions 101 and 102 are further diffused, and the p-type region 10
0, and p-type base regions 2 and 3 are formed separately. After this, as shown in d, the electrodes 13, 14, 15, 1
6, 17, 18, 23, 24, 33, 34,
Bipolar transistors A, B (!: n-channel MO
An S transistor D is formed on the same semiconductor substrate. In the above method, the base region is not initially separated and the p-type region 10
0, and then n+ type regions 101, 10.
2 to reach the bottom of the p-type region 100 to separate the p-type base regions 2 and 3, and form the n+-type region 101.
is a separation region between each base region and a collector electrode region. Note that the n+ region 102 is used only for extracting the collector electrode. Although only transistors A, B, and D are shown in FIG. 2, it goes without saying that any number of transistors may be used. In the bipolar transistor manufactured by the above method, the collector region can be fully utilized not only under the base regions 2 and 3 but also on the side surfaces, and the collector electrode can be formed from each side surface of each transistor with a minimum occupied area. This makes it possible to reduce the collector series resistance of each transistor.

In addition, the substrate 1 is used as an emitter and the n+ type diffusion region 6 is
, 7 as collectors, the n+ type regions 101 and 102 exist on the sides of the base regions 2 and 3, which act as emitter regions and increase the emitter injection efficiency, resulting in an inverse β
This increases the resistance, which is advantageous in terms of transistor circuit design.

Note that it is of course not limited to providing an n+ region similar to 101 on the left side of transistor A in FIG. Furthermore, n+ type regions 101 and 10 which become n+ separation layers
By forming the n+ diffusion regions provided in the 2 and P-wells into an annular shape, the series resistance can be more effectively lowered and the inverse β can be increased.

As described above, according to the present invention, a bipolar transistor with stable and excellent characteristics can be obtained in an integrated circuit including both MOS1 bipolar transistors.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit in which a bipolar transistor is constructed in a MOS type integrated circuit, and FIGS. 2A to 2D are cross-sectional views of the manufacturing process of the MOS and bipolar transistors in the MOS type integrated circuit. A, B... Bipolar transistor, D...
...MOS transistor, 1...n-type semiconductor substrate, 2, 3...p-type base region, 6,7...
...n+ type diffusion region (emitter region), 26...
...P well, 27, 28...n+ type source, drain region, 100...p type region, 101
, 102...n+ type area.

Claims (1)

[Claims] 1. By forming a p-type region on an n-type semiconductor substrate at the same time as a P-well of a MOS transistor, and selectively forming an n-type region so as to reach the substrate from a part of the surface of this p-type region, 1. A method of manufacturing a semiconductor integrated circuit device, comprising: dividing a p-type region to form base regions of a plurality of bipolar transistors.