JPS5943808B2 - Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer - Google Patents
Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a waferInfo
- Publication number
- JPS5943808B2 JPS5943808B2 JP56144690A JP14469081A JPS5943808B2 JP S5943808 B2 JPS5943808 B2 JP S5943808B2 JP 56144690 A JP56144690 A JP 56144690A JP 14469081 A JP14469081 A JP 14469081A JP S5943808 B2 JPS5943808 B2 JP S5943808B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- silicon
- temperature
- lamp
- tubular lamp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3238—Materials thereof being insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3242—Structure
- H10P14/3244—Layer structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明はウェハー上のアモルファスシリコンもしくは多
結晶シリコンをエピタキシャル成長させる方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for epitaxially growing amorphous or polycrystalline silicon on a wafer.
上記方法については、既にいくつかの文献に紹介されて
いるところであるが、従来最も一般的な方法は、厚さ４
０００Ａのアモルファスシリコン（以下α−Ｓｉ）の層
を、例えは６００’Ｃの電気炉で約８０分間加熱する電
気炉法であるが、比較的長い時間の加熱なので、生産性
の点で実用的でない。The above method has already been introduced in several documents, but the most common method to date is
The electric furnace method heats a layer of 000A amorphous silicon (hereinafter referred to as α-Si) in an electric furnace at 600'C for about 80 minutes, but since the heating time is relatively long, it is not practical in terms of productivity. Not.
また、温度を上げることにより結晶成長速度は上昇する
が、シリコンのウェハーに「反り」が発生したり、汚染
されたり、したがつて生産の歩留が悪い等の欠点があり
、最近ではレーザビームで短時間照射する方法が研究さ
れている。しかしながら、このレーザビームによる方法
の場合は、小さなビームスポットでα−Ｓｉの層を走査
する関係で、走査線と走査線との間に生ずる境界区域に
成長ムラが生じたり、走査線の間隔を小さくすれば時間
がかゝるうえに過剰加熱部分が生じたりーする欠点が指
摘されている。そのため、最も新しいＩＣ回路方式と言
われる「三次元積層型ＩＣ回路の生産には使用できない
とされている。本発明の目的はウェハー上のアモルファ
スシリコンもしくは多結晶シリコンをエピタキシャル成
長させる方法において、比較的短時間で、しかもウェハ
ーを損傷させることなくα−Ｓｉの全域を成長ムラなく
実行する新規な方法を提供することにあり、その特徴と
するところは、（イ）複数の管状ランプを管軸を平行も
しくはほぼ平行にして、エピタキシャル成長させるべき
シリコンの通路に対して平行なもしくはほぼ平行平面内
に配置し、（ロ）シリコンの表面が１１０００Ｃ〜１４
００℃の温度に加熱されるように少なくとも４秒間以上
管状ランプも点灯し、←→ 次に、特定の管状ランプを
過入力点灯せしめて、シリコンの表面の一部を局部的に
１４１０℃〜１４８０℃に昇温させ、（ニ）シリコンを
、管状ランプの管軸に対して直角方向に、管状ランプに
対して相対的に少なくとも０．１ＣＴｆＬ／秒以上の速
度で移動させる、工程を含むことにある。In addition, although increasing the temperature increases the crystal growth rate, it has drawbacks such as warping and contamination of silicon wafers, resulting in poor production yields. A method of irradiating for a short period of time is being researched. However, in the case of this method using a laser beam, since the α-Si layer is scanned with a small beam spot, uneven growth occurs in the boundary area between the scanning lines, and the spacing between the scanning lines is It has been pointed out that if the size is made smaller, it will take more time and overheating may occur. Therefore, it is said that it cannot be used in the production of three-dimensional stacked IC circuits, which are said to be the newest IC circuit methods. The purpose is to provide a new method for uniformly growing α-Si over the entire area in a short time and without damaging the wafer. (b) The surface of the silicon is between 11000C and 1400C.
The tubular lamp is also turned on for at least 4 seconds so that it is heated to a temperature of 00°C, and then the specific tubular lamp is turned on with excessive power to locally heat a part of the silicon surface to 1410°C to 1480°C. °C, and (d) moving the silicon at a speed of at least 0.1 CTfL/sec or more relative to the tubular lamp in a direction perpendicular to the tube axis of the tubular lamp. be.
以下、実施例を参照しながら本発明を説明する。The present invention will be described below with reference to Examples.
第１図は、本発明に使用する管状ランプの一例の説明図
であつて、具体的には定格消費電力１ｋＷのハロゲン白
熱電球である。図において、１はバルブ、２はシール部
、３は、シール部に埋設された金属箔、４及び５は、前
記箔から導出される外導線及び内導線であり、内導線５
，５間には、管軸に沿つて長さ約１６ｃｍのフイラメン
ト６が張架されている。７は、フイラメント６を管軸に
支えるためのアンカーであり、バルブ内には稀ガスと共
に微量のハロゲンを含み、上記電球は小型長寿命の特性
を有するものとして知られている。FIG. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, specifically a halogen incandescent lamp with a rated power consumption of 1 kW. In the figure, 1 is a valve, 2 is a seal portion, 3 is a metal foil embedded in the seal portion, 4 and 5 are an outer conductor wire and an inner conductor wire led out from the foil, and an inner conductor wire 5.
, 5, a filament 6 having a length of about 16 cm is stretched along the tube axis. Reference numeral 7 denotes an anchor for supporting the filament 6 on the tube shaft, and the bulb contains rare gas and a trace amount of halogen, and the bulb is known to have a small size and long life.
第２図は、上記管状ランプ１００の複数を、管軸を平行
にして、エピタキシャル成長させるべきα−Ｓｉの層を
具えたウエハ一８の通路上に対して平行な平面Ｓ内に配
置し、上方をミラー９で覆つた、本発明方法を実施する
ための加熱炉の一例の要部の説明図である。図示の如く
、ウエハ一８は、管状ランプ１００の管軸に対して直角
方向（矢印方向）に走行するものである。第３図は、エ
ピタキシャル成長させるべきα一Ｓｉの層を具えたウエ
ハ一８の一例の説明図であつて、具体的には、ウエハ一
は単結晶シリコン（以下Ｓ−Ｓｌ）、１０は、例えばＳ
ｌＯ２やＳｉ３Ｎ３の如き絶縁層、１１はα−Ｓｉの層
であり、厚みは夫々約０．５ｍｍ１約０．２μｍ１約１
１Ｔｍで、ウエハ一８の直径は約１０ｃｍである。FIG. 2 shows a plurality of the above-mentioned tubular lamps 100 arranged in a plane S parallel to the path of a wafer 18 having a layer of α-Si to be epitaxially grown, with the tube axes parallel to each other. FIG. 2 is an explanatory diagram of the main parts of an example of a heating furnace for carrying out the method of the present invention, in which the heating furnace is covered with a mirror 9. As shown, the wafer 18 runs in a direction perpendicular to the tube axis of the tubular lamp 100 (in the direction of the arrow). FIG. 3 is an explanatory diagram of an example of a wafer 18 provided with a layer of α-Si to be epitaxially grown. Specifically, wafer 1 is single crystal silicon (hereinafter referred to as S-Sl), S
An insulating layer such as 1O2 or Si3N3, 11 is a layer of α-Si, and the thickness is about 0.5 mm, about 0.2 μm, about 1
At 1 Tm, the diameter of the wafer 18 is about 10 cm.
こ＼で、絶縁層１０には、第４図に拡大図示した如く、
巾数μｍ程度の溝１２が、約５０〜５００μｍの間隔で
設けられており、α−Ｓｉ層１１とウエハ一８とは溝１
２を介して接触している。したがつて、α−Ｓｉの層を
エピタキシャル成長させた場合、Ｓ〜Ｓｌの層が、絶縁
層１０を介して「積層」されたものとなる。三次元積層
型１Ｃ回路の製造に際しては適宜絶縁層内にスルーホー
ルを設け上下のＳ−Ｓｉ層を電気的に接続して、三次元
積層型ＩＣ回路の製作が可能となる。さて、ウエハ一８
を加熱炉に挿入し、ランプ１００を点灯せしめると、α
−Ｓｌの層は３〜５秒程度で１１００℃〜１４００℃に
略均一に昇温するので、しばらくその温度で保持せしめ
、後、ウエハ一の一番端部のランプ１００ａのみ過入力
点灯し、例えば定格消費電力１ｋＷの場合、１．２ｋＷ
程度で点灯し、その直下を、ウエハ一の全域が通過する
ようにウエハ一を移動させる。Here, the insulating layer 10 has, as shown in an enlarged view in FIG.
Grooves 12 with a width of about several μm are provided at intervals of about 50 to 500 μm, and the α-Si layer 11 and the wafer 18 are connected to the grooves 12.
Contact is made through 2. Therefore, when an α-Si layer is epitaxially grown, S to Sl layers are “stacked” with the insulating layer 10 in between. When manufacturing a three-dimensionally stacked 1C circuit, a through hole is appropriately provided in the insulating layer to electrically connect the upper and lower S-Si layers, thereby making it possible to manufacture a three-dimensionally stacked IC circuit. Now, wafer 18
is inserted into the heating furnace and the lamp 100 is turned on, α
- The temperature of the Sl layer rises almost uniformly to 1100° C. to 1400° C. in about 3 to 5 seconds, so it is held at that temperature for a while, and then only the lamp 100a at the end of the wafer is turned on with excessive input. For example, if the rated power consumption is 1kW, 1.2kW
The wafer 1 is moved so that the entire area of the wafer 1 passes directly under it.
α−Ｓｉの層は、直下に来た部分のみ１４１００Ｃ−１
４８０℃になり、その部分がエピタキシャル成長させら
れる。つまり、ゾーンメルテイングやゾーンリフアイニ
ング操作のように、エピタキシャル成長は、ウエハ一の
走行に応じて、過入力点灯しているランプ１００ａの直
下に到達する順に、部分的に少しマ進行し、最後に全域
にまたがつて完成する。この場合、炉内雰囲気はアルゴ
ンが良く、成長の始点となる結晶核は、溝を介して接触
しているＳ一Ｓｉがその役割を果している。上記エピタ
キルアル成長は、シリコンの融点近傍で行うのが良く、
全域同時に、長時間、１４１０℃〜１４８０℃に昇温す
ると、ウエハ一が熔融したり、「反り」などが生ずる欠
点があるが、ゾーンリフアイニングのような方法で進行
させると、ウエハ一を損傷させず、「反り］なども生ず
ることなくα−Ｓｉの層の全域のエピタキシャル成長が
完成し、しかも成長ムラもない。The α-Si layer is 14100C-1 only in the part directly below it.
The temperature reaches 480° C., and that portion is epitaxially grown. In other words, like zone melting and zone refining operations, epitaxial growth progresses a little in parts as the wafer moves, reaching just below the lamp 100a that is turned on due to excessive input, and finally It will be completed across the entire area. In this case, the atmosphere in the furnace is preferably argon, and the Si-Si contacts through the grooves play the role of crystal nuclei that serve as starting points for growth. The above epitaxial growth is preferably performed near the melting point of silicon,
If the temperature is raised to 1410°C to 1480°C for a long time in the entire area at the same time, there is a drawback that the wafer may melt or "warp". The epitaxial growth of the entire area of the α-Si layer is completed without damage or "warpage", and there is no uneven growth.
温度制御の方は、ランプの消費電力、ランプ間の相互距
離、ランプとウエハ一の離間距離等で１１０００Ｃ〜１
４８０℃の範囲で比較的自由に選択でき、上記、１１０
０℃Ｃ−１４０００Ｃに一時的に保持したのは、全域を
同時に、室温から直接成長温度に昇温させるよりも昇温
ムラによる成長ムラ、ウエハ一の変形が少ないものが得
られるからであり、一種の「サーマルアシスト法」であ
る。前記の一時的保持時間は、少なくとも４秒以上あれ
ば良い。そして、ウエハ一の移動速度は、成長温度とし
て、融点近傍の１４１００Ｃ〜１４８０℃を選ぶ関係で
、０．１ＣＴＬ／秒以上の速度で過入カランプ１００ａ
の直下を通過させるのが良く、それより遅いと過剰加熱
部分が生じたり、ウエハ一を損傷するので好ましくない
。また、熔融表面が表面張力により盛りあがり、それが
そのま＼冷却し、表面に凹凸が生ずる欠点も現われてく
る。たゾし、あまり早いと、成長が不十分な区域が生ず
ることがあり、移動速度の上限は８ＣＴＩＬ／秒にした
方が良い。ところで、本発明の方法においては、加熱源
として、点灯・消灯、定格点灯・過入力点灯いづれの切
り替え作業に応じて殆んど瞬時に全放射光が追随して変
化する管状ランプを利用するものであるから、温度の制
御が容易に実行できること、ランプであるので加熱源が
劣化しても交換や保守も容易、ウエハ一の汚染もなく、
「反り」等の変形防止にも極めて有利である。前記実施
例では、ハロゲン白熱電球を示したが、キセノンロング
アークランプの如き放電灯を利用しても、同じ利点を有
する。本発明は以上の説明からも理解できるように、ウ
エハ一上のアモルフアスシリコンもしくは多結晶シリコ
ンをエピタキシャル成長させる方法において）
（イ）複数の管状ランプを管軸を平行もしくはほぼ平行
にして、エピタキシャル成長させるべきシリコンの通路
に対して平行もしくはほぼ平行な平面内に配置し、（ロ
）シリコンの表面が１１０００Ｃ〜１４０００Ｃの温度
に加熱されるように少なくとも４秒間以上管状ランプを
点灯し、（ハ）次に、特定の管状ランプを過入力点灯せ
しめて、シリコンの表面の一部を局部的に１４１０℃〜
１４８０℃に昇温させ、（ニ）シリコンを、管状ランプ
の管軸に対して直角方向に、管状ランプに対して相対的
に少なくとも０，１ｃｍ／秒以上の速度で移動させるこ
とによつて、比較的短時間で、しかもウエハ一上のα−
Ｓｉの全域を、成長ムラなく、しかもウエハ一を損傷さ
せることなくエピタキシャル成長させるものであり、反
り、汚染もない成長方法が提供できる。For temperature control, the power consumption of the lamps, the mutual distance between the lamps, the distance between the lamps and the wafer, etc. is 11000C~1.
It can be selected relatively freely within the range of 480°C, and the above, 110
The reason why the temperature was temporarily held at 0° C.-14000° C. was because it resulted in less uneven growth due to uneven heating and less deformation of the wafer than when the entire area was heated directly from room temperature to the growth temperature at the same time. This is a type of "thermal assist method." The temporary holding time may be at least 4 seconds or longer. The moving speed of the wafer is set at 14100 to 1480°C near the melting point as the growth temperature, so the moving speed of the wafer is set at a speed of 0.1 CTL/sec or more.
It is best to pass the wafer directly under the wafer.If it is slower than that, excessive heating may occur or the wafer may be damaged, so it is not preferable. Another disadvantage is that the molten surface bulges due to surface tension, which then cools, resulting in unevenness on the surface. However, if the moving speed is too fast, areas with insufficient growth may occur, so it is better to set the upper limit of the moving speed to 8 CTIL/sec. By the way, in the method of the present invention, a tubular lamp is used as a heating source, and the total emitted light changes almost instantaneously in accordance with the switching operation of turning on/off, rated lighting, and over-input lighting. Therefore, the temperature can be easily controlled, and since it is a lamp, it is easy to replace and maintain even if the heating source deteriorates, and there is no contamination of the wafer.
It is also extremely advantageous in preventing deformation such as "warpage". Although a halogen incandescent lamp is shown in the above embodiment, a discharge lamp such as a xenon long arc lamp may also be used with the same advantages. As can be understood from the above description, the present invention relates to a method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer. (a) Epitaxially growing a plurality of tubular lamps with their tube axes parallel or nearly parallel. (b) turn on the tubular lamp for at least 4 seconds so that the surface of the silicon is heated to a temperature of 11,000 C to 14,000 C; (c) To do this, a specific tubular lamp was turned on with excessive power, and a part of the silicon surface was locally heated to 1410℃~
(d) by moving the silicon at a speed of at least 0.1 cm/sec or more relative to the tubular lamp in a direction perpendicular to the tube axis of the tubular lamp; In a relatively short period of time, α-
It is possible to epitaxially grow Si over the entire area without uneven growth and without damaging the wafer, and it is possible to provide a growth method that is free from warping and contamination.
第１図は、本発明に使用する管状ランプの一例の説明図
、第２図は、本発明を実行するための加熱炉の一例の要
部の説明図、第３図はウエハ一の説明図、第４図は、ウ
エハ一の拡大説明図である。FIG. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, FIG. 2 is an explanatory diagram of essential parts of an example of a heating furnace for carrying out the present invention, and FIG. 3 is an explanatory diagram of a wafer. , FIG. 4 is an enlarged explanatory view of the wafer.
Claims (1)
シリコンをエピタキシャル成長させる方法において、（
イ）複数の管状ランプを管軸を平行もしくはほぼ平行に
して、エピタキシャル成長させるべきシリコンの通路に
対して平行もしくはほぼ平行な平面内に配置し、（ロ）
シリコンの表面が１１００℃〜１４００℃の温度に加熱
されるように少なくとも４秒間以上管状ランプを点灯し
、（ハ）次に、特定の管状ランプを過入力点灯せしめて
、シリコンの表面の一部を局部的に１４１０℃〜１４８
０℃に昇温させ、（ニ）シリコンを、管状ランプの管軸
に対して直角方向に、管状ランプに対して相対的に少な
くとも０．１ｃｍ／秒以上の速度で移動させる。 工程を含むことを特徴とする、ウェハー上のアモルファ
スシリコンもしくは多結晶シリコンをエピタキシャル成
長させる方法。[Claims] 1. A method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer,
(b) A plurality of tubular lamps are arranged with their tube axes parallel or approximately parallel to each other in a plane parallel or approximately parallel to the channel of the silicon to be epitaxially grown;
A tubular lamp is turned on for at least 4 seconds so that the surface of the silicon is heated to a temperature of 1100°C to 1400°C. Locally 1410℃~148℃
The temperature is raised to 0° C., and (d) the silicon is moved at a speed of at least 0.1 cm/sec or more relative to the tubular lamp in a direction perpendicular to the tube axis of the tubular lamp. A method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer, the method comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144690A JPS5943808B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144690A JPS5943808B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846618A JPS5846618A (en) | 1983-03-18 |
| JPS5943808B2 true JPS5943808B2 (en) | 1984-10-24 |
Family
ID=15367991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56144690A Expired JPS5943808B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5943808B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6049626U (en) * | 1983-09-13 | 1985-04-08 | ニチデン機械株式会社 | infrared heating device |
| JPH0615787B2 (en) * | 1986-08-11 | 1994-03-02 | 積水化学工業株式会社 | Exterior wall panel seal structure |
| JP2009164321A (en) * | 2008-01-04 | 2009-07-23 | Advanced Lcd Technologies Development Center Co Ltd | Method for manufacturing semiconductor device, manufacturing apparatus thereof, crystallization method, crystallizer, the semiconductor device and display device |
-
1981
- 1981-09-16 JP JP56144690A patent/JPS5943808B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5846618A (en) | 1983-03-18 |
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