JPS5943812B2 - Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer - Google Patents
Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a waferInfo
- Publication number
- JPS5943812B2 JPS5943812B2 JP56144695A JP14469581A JPS5943812B2 JP S5943812 B2 JPS5943812 B2 JP S5943812B2 JP 56144695 A JP56144695 A JP 56144695A JP 14469581 A JP14469581 A JP 14469581A JP S5943812 B2 JPS5943812 B2 JP S5943812B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- silicon
- temperature
- parallel
- lamp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3238—Materials thereof being insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3242—Structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明はウェハー上のアモルファスシリコンもしくは多
結晶シリコンをエピタキシャル成長させる方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for epitaxially growing amorphous or polycrystalline silicon on a wafer.
上記方法については、既にいくつかの文献に紹介され
ているところであるが、従来最も一般的な方法は、厚さ
4000λのアモルファスシリコン(以下α−Si)の
層を、例えば600℃の電気炉で約80分間加熱する電
気炉法であるが、比較10的長い時間の加熱なので、生
産性の点で実用的でない。The above method has already been introduced in several documents, but the most common method to date is to deposit a layer of amorphous silicon (hereinafter referred to as α-Si) with a thickness of 4000λ in an electric furnace at 600°C, for example. Although the electric furnace method heats for about 80 minutes, it is a comparatively long heating time, so it is not practical in terms of productivity.
また、温度を上げることにより結晶成長速度は上昇する
が、シリコンのウェハーに「反り」が発生したり、汚染
されたり、したがつて生産の歩留が悪い等の欠15点が
あり、最近ではレーザビームで短時間照射する方法が研
究されている。In addition, although increasing the temperature increases the crystal growth rate, there are disadvantages such as "warping" of silicon wafers, contamination, and therefore poor production yields. A method of short-term irradiation with a laser beam is being researched.
しかしながら、このレーザビームによる方法の場合は、
小さなビームスポットでα−51の層を走査する関係で
、走査線と走査線との間に生ずる境界区域に成長ムラが
生じ20たり、走査線の間隔を小さくすれば時間がかか
るうえに過剰加熱部分が生じたりする欠点が指摘されて
いる。そのため、最も新しいIC回路方式と言われる「
三次元積層型IC回路」の生産には使用できないとされ
ている。25本発明の目的は、ウェハー上のアモルファ
スシリコンもしくは多結晶シリコンをエピタキシャル成
長させる方法において、比較的短時間で、しかもウェハ
ーを損傷させることなくα−Siの全域を成長ムラなく
実行する新規な方法を提供すること30にあり、その特
徴とするところは、げ)複数の管状ランプを管軸を平行
もしくはほぼ平行にして、エピタキシャル成長させるべ
きシリコンの通路に対して平行もしくはほぼ平行な、か
つ該通路を挟む位置の2つの平面内に配置し、35(口
)シリコンの表面が1100℃〜1、400℃の温度に
加熱されるよう、一方の平面内の管状ランプを少なくと
も4秒間以上点灯し、(ハ)他方の平面内の管状ランプ
の少なくとも1本を点灯して、シリコンの表面の一部を
局部的に1410′C〜1480℃に昇温せしめ、(ニ
)その後、他方の平面内の点灯されるべき管状ランプを
隣接する順に切り替えてエピタキシャル成長されるべき
全域を141『C〜1480℃に昇温させる、工程を含
むことにある。However, in the case of this laser beam method,
Because the α-51 layer is scanned with a small beam spot, uneven growth occurs in the boundary area between the scan lines20, and reducing the spacing between the scan lines takes time and causes excessive heating. It has been pointed out that some defects may occur. Therefore, it is said to be the newest IC circuit system.
It is said that it cannot be used in the production of "three-dimensional stacked IC circuits." 25 The purpose of the present invention is to provide a novel method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer, which can uniformly grow the entire area of α-Si in a relatively short time and without damaging the wafer. To provide 30, the characteristics are as follows: (1) A plurality of tubular lamps are arranged with their tube axes parallel or nearly parallel to a passageway of silicon to be epitaxially grown, and the passageway is parallel or nearly parallel to the passageway of the silicon to be epitaxially grown; Place it in two planes at the sandwiching position, and turn on the tubular lamp in one plane for at least 4 seconds so that the surface of the 35 (mouth) silicon is heated to a temperature of 1100 ° C to 1,400 ° C. C) Turn on at least one of the tubular lamps in the other plane to locally raise the temperature of a part of the silicon surface to 1410'C to 1480C; (d) Then turn on the lamp in the other plane. The present invention includes a step of heating the entire area to be epitaxially grown to 141° C. to 1480° C. by switching the tubular lamps to be grown in adjacent order.
以下、実施例を参照しながら本発明を説明する。The present invention will be described below with reference to Examples.
第1図は、本発明に使用する管状ランプの一例の説明図
であつて、具体的には定格消費電力1kWのハロゲン白
熱電球である。図において、1はバルブ、2はシール部
、3は、シール部に埋設された金属箔、4及び5は、前
記箔から導出される外導線及び内導線であり、内導線5
,5間には、管軸に沿つて長さ約16C!RLのフイラ
メント6が張架されている。7は、フイラメント6を管
軸に支えるためのアンカーであり、バルブ内には稀ガス
と共に微量のハロゲンを含み、上記電球は小型長寿命の
特性を有するものとして知られている。FIG. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, specifically a halogen incandescent lamp with a rated power consumption of 1 kW. In the figure, 1 is a valve, 2 is a seal portion, 3 is a metal foil embedded in the seal portion, 4 and 5 are an outer conductor wire and an inner conductor wire led out from the foil, and an inner conductor wire 5.
, 5 has a length of about 16C along the tube axis! The RL filament 6 is stretched. Reference numeral 7 denotes an anchor for supporting the filament 6 on the tube shaft, and the bulb contains rare gas and a trace amount of halogen, and the bulb is known to have a small size and long life.
第2図は、上記管状ランプ100の複数を、管軸を平行
にして、エピタキシャル成長させるべきα−Siの層を
具えたウエハ一8の通路Pに対して平行な、かつ該通路
を挟む位置の2つの平面SぃS2内に配置し、上方及び
下方をミラー9で覆つた、本発明方法を実施するための
加熱炉の一例の要部の説明図である。第3図は、エピタ
キシャル成長させるべきα一Siの層を具えたウエハ一
8の一例の説明図であつて、具体的には、ウエハ一は単
結晶シリコン(以下S−S!)、10は、例えばSiO
2やSi3N4の如き絶縁層、11はα−Slの層であ
り、厚みは夫々約0.5n.約0.2μm1約1μmで
、ウエハ一8の直径は約10C771である。FIG. 2 shows a plurality of the above-mentioned tubular lamps 100, with their tube axes parallel to each other, at positions parallel to and sandwiching the passage P of a wafer 18 having a layer of α-Si to be epitaxially grown. FIG. 2 is an explanatory view of the essential parts of an example of a heating furnace for carrying out the method of the present invention, which is arranged in two planes S-S2 and whose upper and lower sides are covered with mirrors 9. FIG. 3 is an explanatory diagram of an example of a wafer 18 provided with a layer of α-Si to be epitaxially grown. Specifically, wafer 1 is single crystal silicon (hereinafter referred to as S-S!), 10 is For example, SiO
2 and Si3N4, and 11 is an α-Sl layer, each having a thickness of about 0.5 nm. The diameter of the wafer 18 is about 10C771, with a diameter of about 0.2 μm and about 1 μm.
ここで、絶縁層10には、第4図に拡大図示した如く、
巾数μm程度の溝12が、約50〜500p.mの間隔
で設けられており、α−Sl層11とウエハ一8とは溝
12を介して接触している。したがつて、α−Siの層
をエピタキシャル成長させた場合、s−Siの層が、絶
縁層10を介して「積層」されたものとなる。三次元積
層型1C回路の製造に際しては適宜絶縁層内にスルーホ
ールを設け上下のs−Si層を電気的に接続して、三次
元積層型IC回路の製作が可能となる。さて、ウエハ一
8を加熱炉に挿入し、一方の平面S2内のランプ100
を点灯せしめると、ウニハ一及びα−Siの層は3〜5
秒程度で1100゜C〜140『Cに略均一に昇温する
ので、しばらくその温度で保持せしめ、後、他方の平面
S1内の、ウエハ一の一番端部のランプ100aのみ点
灯し、順次隣接する右側のランプ(第2図参照)を切替
選択して点灯するとα−S1層は所定時間の間だけ左側
から部分的に少しずつ、1410℃〜1480℃の温度
になるら頂度、ゾーンメルテイングやゾーンリフアイニ
ング操作のように、部分部分処理して行くものであつて
14100C〜1480℃に保たれる所定時間は、ラン
プの消費電力、ランプ間の相互距離、ランプとウエハ一
との離間距離、切替選択速度によつて種々の値が選べる
が、上記ゾーンが少なくとも0.1C!TL/秒以上で
移動するよう順次切替選択する。Here, in the insulating layer 10, as shown in an enlarged view in FIG.
The groove 12 with a width of about several μm has a width of about 50 to 500 p.m. The α-Sl layer 11 and the wafer 18 are in contact with each other via the grooves 12. Therefore, when an α-Si layer is epitaxially grown, s-Si layers are “stacked” with the insulating layer 10 in between. When manufacturing a three-dimensionally stacked 1C circuit, a through hole is appropriately provided in the insulating layer to electrically connect the upper and lower s-Si layers, thereby making it possible to manufacture a three-dimensionally stacked IC circuit. Now, the wafer 18 is inserted into the heating furnace, and the lamp 100 in one plane S2 is
When the light is turned on, the layer of Uniha and α-Si is 3 to 5.
The temperature rises almost uniformly from 1100°C to 140°C in about seconds, so it is held at that temperature for a while, and then only the lamp 100a at the end of the wafer in the other plane S1 is turned on, and then When the adjacent right lamp (see Figure 2) is switched on and turned on, the α-S1 layer gradually changes from the left side for a predetermined period of time, and when the temperature reaches 1410°C to 1480°C, it reaches the top and the zone. For partial processing such as melting or zone refining operations, the predetermined time for which the temperature is maintained at 14100C to 1480C depends on the power consumption of the lamps, the mutual distance between the lamps, and the distance between the lamps and the wafer. Various values can be selected depending on the separation distance and switching selection speed, but the above zone is at least 0.1C! Sequentially switch and select to move at TL/sec or more.
この選択速度は、実際には加熱炉が設計されれば実験的
に決めることができる。この場合、炉内雰囲気はアルゴ
ンが良く、成長の始点となる結晶核は溝を介して接触し
ているs−Siがその役割を果している。上記エピタキ
シャル成長は、シリコンの融点近傍で行うのが良く、全
域同時に、長時間、1410℃〜1480℃に昇温する
と、ウエハ一が熔融したり、「反り]などが生ずる欠点
があるが、ゾーンリフアイニングのような方法で進行さ
せると、ウエハ一を損傷させず、「反り」なども生ずる
ことなくα−Siの層の全域のエピタキシャル成長が完
成し、しかも成長ムラもない。温度制御の方は、ランプ
の消費電力、ランプ間の相互距離、ランプとウエハ一の
離間距離等で1100℃〜1480℃の範囲で比較的自
由に選択でき、上記、11000C〜1400℃に一時
的に保持したのは、全域を同時に、室温から直接成長温
度に昇温させるよりも昇温ムラによる成長ムラ、ウエハ
一の変形が少ないものが得られるからであり、一種の「
サーマルアシスト法」である。前記の一時的保持時間は
、少なくとも4秒以上あれば良い。This selection speed can actually be determined experimentally once the heating furnace is designed. In this case, the atmosphere in the furnace is preferably argon, and the s-Si that is in contact with the crystal nucleus, which is the starting point of growth, through the groove plays its role. The above epitaxial growth is preferably performed near the melting point of silicon, and if the temperature is raised to 1410°C to 1480°C for a long time over the entire area at the same time, the wafer may melt or "warp" may occur. When proceeding by a method such as lining, the epitaxial growth of the entire area of the α-Si layer is completed without damaging the wafer or causing "warpage", and there is no uneven growth. Temperature control can be relatively freely selected within the range of 1100°C to 1480°C depending on the power consumption of the lamps, the mutual distance between the lamps, the distance between the lamp and the wafer, etc. The reason for this is that it is possible to obtain a product with less uneven growth due to uneven heating and less deformation of the wafer than by raising the temperature of the entire area directly from room temperature to the growth temperature at the same time.
Thermal Assist Method”. The temporary holding time may be at least 4 seconds or more.
そして、ゾーンの移動速度は、成長温度として、融点近
傍の1410動C−1480を選ぶ関係で、0.1CT
fL/秒以上の速度になるようにランプ100aを隣接
する順に切り替え選択するのが良く、それより遅いと過
剰加熱部分が生じたり、ウエハ一を損傷するので好まし
くない。また、熔融表面が表面張力により盛りあがり、
それがそのまま冷却し、表面に凹凸が生ずる欠点も現わ
れてくる。ただし、あまり早いと、成長が不十分な区域
が生ずることがあり、移動速度の上限は8鑞/移にした
方が良い。ところで、本発明の方法においては、加熱源
として、点灯・消灯、定格点灯・過入力点灯いずれの切
り替え作業に応じて殆んど瞬時に全放射光が追随して変
化する管状ランプを利用するものであるから、温度の制
御が容易に実行できること、ランプであるので加熱源が
劣化しても交換や保守も容易、ウエハ一の汚染もなく、
「反り」等の変形防止にも極めて有利である。The moving speed of the zone is 0.1 CT, with the growth temperature chosen as 1410 kinematic C-1480 near the melting point.
It is preferable to switch the lamps 100a in adjacent order so as to achieve a speed of fL/sec or more; if the speed is slower than that, excessive heating may occur or the wafer may be damaged, so it is not preferable. In addition, the molten surface bulges due to surface tension,
As it cools, defects such as unevenness on the surface appear. However, if it is too fast, there may be areas where the growth is insufficient, so it is better to set the upper limit of the movement speed to 8 wires/movement. By the way, in the method of the present invention, a tubular lamp is used as a heating source, and the total emitted light changes almost instantaneously depending on whether the lamp is switched on/off, rated lighting, or over-input lighting. Therefore, the temperature can be easily controlled, and since it is a lamp, it is easy to replace and maintain even if the heating source deteriorates, and there is no contamination of the wafer.
It is also extremely advantageous in preventing deformation such as "warpage".
前記実施例では、ハロゲン白熱電球を示したが、キセノ
ンロングアークランプの如き放電灯を利用しても、同じ
利点を有する。本発明は以上の説明からも理解できるよ
うに、ウエハ一上のアモルフアスシリコンもしくは多結
晶シリコンをエピタキシャル成長させる方法において、
(イ)複数の管状ランプを管軸を平行もしくはほぼ平行
にして、エピタキシャル成長させるべきシリコンの通路
に対して平行もしくはほぼ平行な、かつ該通路を挟む位
置の2つの平面内に配置し、(ロ)シリコンの表面が1
100′C〜1400温度に加熱されるよう、一方の平
面内の管状ランプを少なくとも4秒間以上点灯し、(ハ
)他方の平面内の管状ランプの少なくとも1本を点灯し
て、シリコンの表面の一部を局部的に1410てC〜1
480℃に昇温せしめ、(ニ)その後、他方の平面内の
点灯されるべき管状ランプを隣接する順に切り替えてエ
ピタキシャル成長されるべき全域を1410エC〜14
80℃に昇温させる、ことによつて、比較的短時間で、
しかもウエハ一上のα−Siの全域を、成長ムラなく、
しかもウエハ一を損傷させることなくエピタキシャル成
長させるものであり、反り、汚染もない成長方法が提供
できる。Although a halogen incandescent lamp is shown in the above embodiment, a discharge lamp such as a xenon long arc lamp may also be used with the same advantages. As can be understood from the above description, the present invention is a method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer.
(b) A plurality of tubular lamps are arranged in two planes with their tube axes parallel or nearly parallel, parallel or almost parallel to the passage of silicon to be epitaxially grown, and at positions sandwiching the passage. ) The surface of silicon is 1
(c) Turn on at least one of the tubular lamps in the other plane for at least 4 seconds to heat the surface of the silicon to a temperature of 100'C to 1400C; Partially 1410C~1
(d) Then, the tubular lamps to be lit in the other plane are switched in the order of adjacent ones, and the entire area to be epitaxially grown is heated to 1410°C to 14°C.
By raising the temperature to 80°C, in a relatively short time,
Moreover, the entire area of α-Si on the wafer can be grown evenly.
Moreover, epitaxial growth is performed without damaging the wafer, and a growth method that is free from warping and contamination can be provided.
第1図は、本発明に使用する管状ランプの一例の説明図
、第2図は、本発明を実行するための加熱炉の一例の要
部の説明図、第3図はウエハ一の説明図、第4図は、ウ
エハ一の拡大説明図である。FIG. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, FIG. 2 is an explanatory diagram of essential parts of an example of a heating furnace for carrying out the present invention, and FIG. 3 is an explanatory diagram of a wafer. , FIG. 4 is an enlarged explanatory view of the wafer.
Claims (1)
シリコンをエピタキシャル成長させる方法において、(
イ)複数の管状ランプを管軸を平行もしくはほぼ平行に
して、エピタキシャル成長させるべきシリコンの通路に
対して平行もしくはほぼ平行な、かつ該通路を挟む位置
の2つの平面内に配置し、(ロ)シリコンの表面が11
00℃〜1400℃の温度に加熱されるよう、一方の平
面内の管状ランプを少なくとも4秒間以上点灯し、(ハ
)他方の平面内の管状ランプの少なくとも1本を点灯し
て、シリコンの表面の一部を局部的に1410℃〜14
80℃に昇温せしめ、(ニ)その後、他方の平面内の点
灯されるべき管状ランプを隣接する順に切り替えてエピ
タキシャル成長されるべき全域を1410℃〜1480
℃に昇温させる、工程を含むことを特徴とする、ウェハ
ー上のアモルファスシリコンもしくは多結晶シリコンを
エピタキシャル成長させる方法。1 In a method of epitaxially growing amorphous silicon or polycrystalline silicon on a wafer, (
(b) A plurality of tubular lamps are arranged in two planes with their tube axes parallel or nearly parallel, parallel or nearly parallel to the passageway of the silicon to be epitaxially grown, and at positions sandwiching the passageway; The surface of silicon is 11
(c) At least one of the tubular lamps in the other plane is turned on so that the silicon surface is heated to a temperature between 00°C and 1400°C for at least 4 seconds; locally at 1410℃~14
The temperature was raised to 80°C, and (d) the tubular lamps to be lit in the other plane were switched in the order of adjacent ones to heat the entire area to be epitaxially grown to 1410°C to 1480°C.
A method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer, the method comprising the step of raising the temperature to ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144695A JPS5943812B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144695A JPS5943812B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846623A JPS5846623A (en) | 1983-03-18 |
| JPS5943812B2 true JPS5943812B2 (en) | 1984-10-24 |
Family
ID=15368116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56144695A Expired JPS5943812B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5943812B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6060712A (en) * | 1983-09-13 | 1985-04-08 | Nichiden Mach Ltd | Infrared ray heating method |
-
1981
- 1981-09-16 JP JP56144695A patent/JPS5943812B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5846623A (en) | 1983-03-18 |
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