JPS5948533B2 - Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer - Google Patents
Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a waferInfo
- Publication number
- JPS5948533B2 JPS5948533B2 JP56144692A JP14469281A JPS5948533B2 JP S5948533 B2 JPS5948533 B2 JP S5948533B2 JP 56144692 A JP56144692 A JP 56144692A JP 14469281 A JP14469281 A JP 14469281A JP S5948533 B2 JPS5948533 B2 JP S5948533B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- wafer
- lamps
- tubular
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3238—Materials thereof being insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3242—Structure
- H10P14/3244—Layer structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明はウェハー上のアモルファスシリコンもしくは多
結晶シリコンをエピタキシャル成長させる方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for epitaxially growing amorphous or polycrystalline silicon on a wafer.
上記方法については、既にいくつかの文献に紹介されて
いるところであるが、従来最も一般的な方法は、厚さ4
000Λのアモルファスシリコン(以下α−Si)の層
を、例えば600℃の電気炉で約80分間加熱する電気
炉法であるが、比較的長い時間の加熱なので、生産性の
点で実用的でない。The above method has already been introduced in several documents, but the most common method to date is
The electric furnace method heats a layer of 000 Λ amorphous silicon (hereinafter referred to as α-Si) in an electric furnace at, for example, 600° C. for about 80 minutes, but since the heating time is relatively long, it is not practical in terms of productivity.
また、温度を上げることにより結晶成長速度は上昇する
が、シリコンのウェハーに「反り」が発生したり、汚染
されたり、したがつて生産の歩留が悪い等の欠点があり
、最近ではレーザビームで短時間照射する方法が研究さ
れている。しかしながら、このレーザビームによる方法
の場合は、小さなビームスポットでα−Siの層を走査
する関係で、走査線と走査線との間に生ずる境界区域に
成長ムラが生じたり、走査線の間隔を小さくすれば時間
がかかるうえに過剰加熱部分が生じたりする欠点が指摘
されている。そのため、最も新しいIC回路方式と言わ
れる「三次元積層型IC回路」の生産には使用できない
とされている。本発明の目的は、ウェハー上のアモルフ
アスシ・リコンもしくは多結晶シリコンをエピタキシャ
ル成長させる方法において、比較的短時間で、しかもウ
ェハーを損傷させることなくα−Siの全域を成長ムラ
なく実行する新規な方法を提供することにあり、その特
徴とするところは、フ (イ)複数の管状ランプを管軸
を平行もしくはほぼ平行にして、エピタキシャル成長さ
せるべきシリコンの通路に対して平行もしくはほぼ平行
な、かつ該通路を挟む位置の2つの平面内に配置し、5
(口)シリコンの表面が1100℃〜1400℃の温度
に加熱されるよう、両方の平面内の管状ランプを少なく
とも4秒間以上点灯し、(ハ)シリコンの表面に面する
方の平面内の管状ランプの少なくとも1本を過入力点灯
して、シリコンの表面の一部を局部的に1410℃〜1
480℃に昇温せしめ、(ニ)シリコンを、管状ランプ
の管軸に対して直角方向に、管状ランプに対して相対的
に少なくとも0.1cm/秒以上の速度で移動させる、
工程を含むことにある。In addition, although increasing the temperature increases the crystal growth rate, it has drawbacks such as warping and contamination of silicon wafers, resulting in poor production yields. A method of irradiating for a short period of time is being researched. However, in the case of this method using a laser beam, since the α-Si layer is scanned with a small beam spot, uneven growth occurs in the boundary area between the scanning lines, and the spacing between the scanning lines is It has been pointed out that if the size is made smaller, it will take more time and may cause excessive heating. Therefore, it is said that it cannot be used in the production of "three-dimensional stacked IC circuits," which are said to be the newest IC circuit method. An object of the present invention is to provide a new method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer, which can uniformly grow the entire area of α-Si in a relatively short time and without damaging the wafer. (a) A plurality of tubular lamps are arranged so that their tube axes are parallel or almost parallel to a path of silicon to be epitaxially grown, and the path is parallel or almost parallel to the path of silicon to be epitaxially grown. placed in two planes sandwiching 5
(1) Turn on the tubular lamps in both planes for at least 4 seconds so that the surface of the silicon is heated to a temperature of 1100°C to 1400°C; (c) Turn on the tubular lamps in the plane facing the silicon surface At least one of the lamps is turned on with excessive power to locally heat a part of the silicon surface to 1,410°C to 1,410°C.
(d) moving the silicon at a speed of at least 0.1 cm/sec or more relative to the tubular lamp in a direction perpendicular to the tube axis of the tubular lamp;
It involves a process.
以下、実施例を参照しながら本発明を説明する。The present invention will be described below with reference to Examples.
第1図は、本発明に使用する管状ランプの一例の説明図
であつて、具体的には定格消費電力1KWのハロゲン白
熱電球である。FIG. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, specifically a halogen incandescent lamp with a rated power consumption of 1 KW.
図において、1はバルブ、2はシール部、3は、シール
部に埋設された金属箔、4及び5は、前記箔から導出さ
れる外導線及び内導線であり、内導線5、5間には、管
軸に沿つて長さ約16cmのフイラメント6が張架され
ている。7は、フイラメント6を管軸に支えるためのア
ンカーであり、バルブ内には稀ガスと共に微量のハロゲ
ンを含み、上記電球は小型,長寿命の特性を有するもの
として知られている。In the figure, 1 is a valve, 2 is a seal part, 3 is a metal foil embedded in the seal part, 4 and 5 are an outer conductor wire and an inner conductor wire led out from the foil, and between the inner conductor wires 5 and 5. A filament 6 with a length of about 16 cm is stretched along the tube axis. Reference numeral 7 denotes an anchor for supporting the filament 6 on the tube shaft.The bulb contains rare gas and a trace amount of halogen, and the bulb is known for its small size and long life.
第2図は、上記管状ランプ100の複数を、管軸を平行
にして、エピタキシャル成長させるべきα−Siの層を
具えたウエハ一8の通路Pに対して平行な、かつ該通路
を挟む位置の2つの平面S1、;S2内に配置し、上方
及び下方をミラー9で覆つた、本発明方法を実施するた
めの加熱炉の一例の要部の説明図である。図示の如く、
ウエハ一8は、管状ランプ100の管軸に対して直角方
向(矢印方向)に走行するものであり、平面S1、S2
.間の距離は6cInである。第3図は、エピタキシャ
ル成長させるべきα−Siの層を具えたウエハ一8の一
例の説明図であつて、具体的には、ウエハ一は単結晶シ
リコン(以下s−Si)、10は、例えばSiO2やS
i3N4の如き絶縁層、11はα−Siの層であり、厚
みは夫々約0.5mm、約0.2μm、約1μmで、ウ
エハ一8の直径は約10cmである。FIG. 2 shows a plurality of the above-mentioned tubular lamps 100, with their tube axes parallel to each other, at positions parallel to and sandwiching the passage P of a wafer 18 having a layer of α-Si to be epitaxially grown. FIG. 2 is an explanatory view of the essential parts of an example of a heating furnace for carrying out the method of the present invention, which is arranged in two planes S1 and S2 and whose upper and lower sides are covered with mirrors 9. As shown,
The wafer 18 runs in a direction perpendicular to the tube axis of the tubular lamp 100 (in the direction of the arrow), and runs along planes S1 and S2.
.. The distance between them is 6 cIn. FIG. 3 is an explanatory diagram of an example of a wafer 18 provided with a layer of α-Si to be epitaxially grown. Specifically, wafer 1 is single crystal silicon (hereinafter referred to as s-Si), SiO2 and S
The insulating layer 11, such as i3N4, is a layer of α-Si, and its thickness is about 0.5 mm, about 0.2 μm, and about 1 μm, respectively, and the diameter of the wafer 18 is about 10 cm.
ここで、絶縁層10には第4図に拡大図示した如く、巾
数μm程度の溝12が、約50〜500μmの間隔で設
けられており、α一Si層11とウエハ一8とは溝12
を介して接触している。したがつて、α−Siの層をエ
ピタキシャル成長させた場合、S−Siの層が、絶縁層
10を介して「積層」されたものとなる。三次元積層型
1C回路の製造に際しては適宜絶縁層内にスルーホール
を設け上下のS−Si層を電気的に接続して、三次元積
層型1C回路の製作が可能となる。さて、ウエハ一8を
加熱炉に挿入し、両方の平面内のランプ100を点灯せ
しめると、ウエハ一及びα−Si層は3〜5秒程度で1
100℃〜1400℃に略均一に昇温するので、しばら
くその温度で保持せしめ、後、他方の平面S1内の、ウ
エハ一の一番端部のランプ100aのみ過入力点灯し、
その直下を、ウエハ一の全域が通過するようにウエハ一
を移動する。α−Siの層は、直下に来た部分のみ14
10℃〜1480℃になり、その部分がエピタキシャル
成長させられる。つまり、ゾーンメルテイングやゾーン
リフアイニング操作のように、エピタキシャル成長は、
ウエハ一の走行に応じて、過入力点灯しているランプ1
00aの直下に到達する順に、部分的に少しずつ進行し
、最後に全域にまたがつて完成する。この場合、、炉内
雰囲気はアルゴンが良く、成長の始点となる結晶核は、
溝を介して接触しているs−Siがその役割を果してい
る。上記エピタキシャル成長は、シリコンの融点近傍で
行うのが良く、全域同時に、長時間、1410℃〜14
80℃に昇温すると、ウエハ一が熔触したり、「反り」
などが生ずる欠点があるが、ゾーンリフアイニングのよ
うな方法で進行させると、ウエハ一を損傷させず、「反
り」なども生ずることなくα−Siの層の全域のエピタ
キシャル成長が完成し、しかも成長ムラもない。Here, as shown in an enlarged view in FIG. 4, the insulating layer 10 is provided with grooves 12 having a width of about several μm at intervals of approximately 50 to 500 μm, and the α-Si layer 11 and the wafer 18 are connected to the grooves. 12
are in contact through. Therefore, when an α-Si layer is epitaxially grown, S-Si layers are “stacked” with the insulating layer 10 in between. When manufacturing a three-dimensionally laminated 1C circuit, a through hole is appropriately provided in the insulating layer to electrically connect the upper and lower S-Si layers, thereby making it possible to manufacture a three-dimensionally laminated 1C circuit. Now, when the wafer 18 is inserted into the heating furnace and the lamps 100 in both planes are turned on, the wafer 1 and the α-Si layer are heated up in about 3 to 5 seconds.
Since the temperature rises almost uniformly from 100° C. to 1400° C., the temperature is maintained for a while, and then only the lamp 100a at the end of the wafer 1 on the other plane S1 is turned on due to excessive input power.
Wafer 1 is moved so that the entire area of wafer 1 passes directly below it. The α-Si layer is only the part directly below14
The temperature is 10° C. to 1480° C., and that portion is epitaxially grown. That is, like zone melting and zone refining operations, epitaxial growth
Lamp 1 lights up due to excessive input as wafer 1 moves.
In order to reach directly below 00a, it progresses little by little in parts, and finally it is completed over the entire area. In this case, the atmosphere in the furnace is preferably argon, and the crystal nucleus, which is the starting point of growth, is
The s-Si in contact through the groove plays this role. The above epitaxial growth is preferably carried out near the melting point of silicon, simultaneously over the entire area and for a long period of time at 1410°C to 14°C.
When the temperature rises to 80℃, the wafer may melt or warp.
However, when proceeding with a method such as zone refinement, the epitaxial growth of the entire α-Si layer can be completed without damaging the wafer or causing "warpage". There is no uneven growth.
温度制御の方は、ランプの消費電力、ランプ間の相互距
離、ランプとウエハ一の離間距離等で1100℃〜14
80℃の範囲で比較的自由に選択でき、上記、1100
℃〜1400℃に一時的に保持したのは、全域を同時に
、室温から直接成長温度に昇温させるよりも昇温ムラに
よる成長ムラ、ウエハ一の変形が少ないものが得られる
からであり、一種の「サーマルアシスト法」である。前
記の一時的保持時間は、少なくとも4秒以上あれば良い
。For temperature control, the power consumption of the lamps, the mutual distance between the lamps, the distance between the lamps and the wafer, etc. can range from 1100℃ to 14℃.
It can be selected relatively freely within the range of 80°C, and the above, 1100°C
The reason for temporarily holding the temperature between 1400°C and 1400°C is that it is possible to obtain a product with less uneven growth due to uneven heating and less deformation of the wafer than by raising the temperature of the entire area directly from room temperature to the growth temperature at the same time. This is the "thermal assist method". The temporary holding time may be at least 4 seconds or more.
そして、ウエハ一の移動速度は、成長温度として、融点
近傍の1410℃〜1480℃を選ぶ関係で、0.1c
m/秒以上の速度で過入力ランプ100aの直下を通過
させるのが良く、それより遅いと過剰加熱部分が生じた
り、ウエハ一を損傷するので好ましくない。また、熔融
表面が表面張力により盛りあがり、それがそのまま冷却
し、表面に凹凸が生ずる欠点も現われてくる。ただし、
あまり早いと、成長が不十分な区域が生ずることがあり
、移動速度の上限は8cm/秒にした方が良い。ところ
で、本発明の方法においては、加熱源として、点灯・消
灯、定格点灯・過入力点灯いずれの切り替え作業に応じ
て殆んど瞬時に全放射光が追髄して変化する管状ランプ
を利用するものであるから、温度の制御が容易に実行で
きること、ランプであるので加熱源が劣化しても交換や
保守も容易、ウエハ一の汚染もなく、「反り」等の変形
防止にも極めて有利である。The moving speed of the wafer is 0.1c, since the growth temperature is selected from 1410°C to 1480°C, which is near the melting point.
It is preferable to pass directly under the over-input lamp 100a at a speed of m/sec or more; if it is slower than that, excessive heating may occur or the wafer may be damaged, so it is not preferable. Another problem is that the molten surface bulges due to surface tension, which then cools down, resulting in unevenness on the surface. however,
If the moving speed is too fast, areas with insufficient growth may occur, so it is better to set the upper limit of the moving speed to 8 cm/sec. By the way, in the method of the present invention, a tubular lamp is used as a heating source, and the total emitted light changes almost instantaneously in accordance with the switching operation of turning on/off, rated lighting, and excessive input lighting. Since it is a wafer, the temperature can be easily controlled, and since it is a lamp, it is easy to replace and maintain even if the heating source deteriorates, there is no contamination of the wafer, and it is extremely advantageous in preventing deformation such as "warping". be.
前記実施例では、ハロゲン白熱電球を示したが、キセノ
ンロングアークランプの如き放電灯を利用しても、同じ
利点を有する。本発明は以上の説明からも理解できるよ
うに、ウエハー上のアモルフアスシリコンもしくは多結
晶シリコンをエピタキシャル成長させる方法において、
(イ腹数の管状ランプを管軸を平行もしくはほぼ平行に
して、エピタキシャル成長させるべきシリコンの通路に
対して平行もしくはほぼ平行な、かつ該通路を挟む位置
の2つの平面内に配置し、(ロ)シリコンの表面が11
00℃〜1400℃の温度に加熱されるよう、両方の平
面内の管状ランプを少なくとも4秒間以上点灯し、(−
一)シリコンの表面に面する方の平面内の管状ランプの
少なくとも1本を過入力点灯して、シリコンの表面の一
部を局部的に1410℃〜1480℃に昇温せしめ、(
:シリコンを、管状ランプの管軸に対して直角方向に、
管状ランプに対して相対的に少なくとも0.1cm/秒
以上の速度で移動させる、ことによつて、比較的短時間
で、しかもウエハ一上のα−Siの全域を、成長ムラな
く、しかもウエハ一を損傷させることなくエピタキシャ
ル成長させるものであり、反り、汚染もない成長方法が
提供できる。Although a halogen incandescent lamp is shown in the above embodiment, a discharge lamp such as a xenon long arc lamp may also be used with the same advantages. As can be understood from the above description, the present invention is a method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer.
(The tube axes of the tube lamps are parallel or almost parallel, and they are arranged in two planes that are parallel or almost parallel to the channel of the silicon to be epitaxially grown, and at positions sandwiching the channel. ) The surface of silicon is 11
Turn on the tubular lamps in both planes for at least 4 seconds so that they are heated to a temperature between 00°C and 1400°C (-
1) At least one of the tubular lamps in the plane facing the silicon surface is turned on with excessive power to locally raise the temperature of a part of the silicon surface to 1410°C to 1480°C, (
: Silicone is placed in a direction perpendicular to the tube axis of the tubular lamp.
By moving the lamp at a speed of at least 0.1 cm/sec relative to the tubular lamp, the entire area of α-Si on the wafer can be grown evenly and evenly on the wafer in a relatively short time. This method enables epitaxial growth without damaging the substrate, and provides a growth method that is free from warping and contamination.
第1図は、本発明に使用する管状ランプの一例の説明図
、第2図は、本発明を実行するための加熱炉の一例の要
部の説明図、第3図はウエハ一のj説明図、第4図は、
ウエハ一の拡大説明図である。
図において、100は管状ランプ、8はウエハ一、9は
ミラー、10は絶縁層、11はα−Siの層、12は溝
を夫々示す。Fig. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, Fig. 2 is an explanatory diagram of main parts of an example of a heating furnace for carrying out the present invention, and Fig. 3 is an explanatory diagram of an example of a wafer. Figure 4 is
FIG. 1 is an enlarged explanatory view of a wafer. In the figure, 100 is a tubular lamp, 8 is a wafer, 9 is a mirror, 10 is an insulating layer, 11 is an α-Si layer, and 12 is a groove.
Claims (1)
シリコンをエピタキシャル成長させる方法において、(
イ)複数の管状ランプを管軸を平行もしくはほぼ平行に
して、エピタキシャル成長させるべきシリコンの通路に
対して平行もしくはほぼ平行な、かつ該通路を挟む位置
の2つの平面内に配置し、(ロ)シリコンの表面が11
00℃〜1400℃の温度に加熱されるよう、両方の平
面内の管状ランプを少なくとも4秒間以上点灯し、(ハ
)シリコンの表面に面する方の平面内の管状ランプの少
なくとも1本を過入力点灯して、シリコンの表面の一部
を局部的に1410℃〜1480℃に昇温せしめ、(ニ
)シリコンを、管状ランプの管軸に対して直角方向に、
管状ランプに対して相対的に少なくとも0.1cm/秒
以上の速度で移動させる、工程を含むことを特徴とする
、ウェハー上のアモルファスシリコンもしくは多結晶シ
リコンをエピタキシャル成長させる方法。1 In a method of epitaxially growing amorphous silicon or polycrystalline silicon on a wafer, (
(b) A plurality of tubular lamps are arranged in two planes with their tube axes parallel or nearly parallel, parallel or nearly parallel to the passageway of the silicon to be epitaxially grown, and at positions sandwiching the passageway; The surface of silicon is 11
(c) At least one of the tubular lamps in the plane facing the silicon surface is turned on for at least 4 seconds so that the lamps are heated to a temperature between 00°C and 1400°C; The input light is turned on to locally raise the temperature of a part of the silicon surface to 1410°C to 1480°C, and (d) the silicon is heated in a direction perpendicular to the tube axis of the tubular lamp.
A method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer, the method comprising the step of moving at a speed of at least 0.1 cm/sec or more relative to a tubular lamp.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144692A JPS5948533B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144692A JPS5948533B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846620A JPS5846620A (en) | 1983-03-18 |
| JPS5948533B2 true JPS5948533B2 (en) | 1984-11-27 |
Family
ID=15368043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56144692A Expired JPS5948533B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5948533B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2939787B2 (en) * | 1994-07-12 | 1999-08-25 | 克爾 萩原 | Method of manufacturing PCa plate for building, PCa plate for building, and mounting method of PCa plate for building |
-
1981
- 1981-09-16 JP JP56144692A patent/JPS5948533B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5846620A (en) | 1983-03-18 |
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