JPS5944636B2 - display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device in which a liquid crystal panel and a shift register for driving the panel are integrated.

Display devices of this type can compactly integrate multiple display digits, and the input terminals to the display panel are connected to the power supply line, data input terminal, write clock terminal, and common digit voltage that alternately drives the liquid crystal panel. It has great advantages such as being able to use a book. It also has the advantage of being able to take out the final output of the shift register and connect it to the data input terminal to form a closed loop and display the same information in alternating drive while memorizing it.

This has a large memory saving effect. but,
Writing to reverse the contents of the shift register is required periodically every half cycle of alternating drive, but this causes inconvenience when it is desired to write information other than the periodic writing. In other words, in memory operation, the shift register forms a closed loop immediately after writing is completed, and the contents are reversed every half cycle of the common digit voltage. Therefore, if information is written at a timing other than regular writing, the common digit voltage Two writes are performed during the same half-cycle, and the memory continues to be inverted, resulting in a display with an inverted pattern. Despite the above-mentioned problems, there is a strong demand for applications such as the application of such display devices to stopwatches to temporarily store timed lap times.

In this case, if the common digit voltage is 50H2, the periodic writing is once every half cycle, 100 times per second, which is 1/1
It is impossible to display lap times in the 000 second range. In addition, it cannot meet the demand for writing and storing information that changes faster than the period of the common digit voltage.

The present invention improves this point and makes it possible to write and store information at any timing in addition to regular writing.

The present invention will be described in detail below based on the drawings.

FIG. 1 is a schematic diagram of a display panel in which a liquid crystal panel and a shift register are integrated.

Serial information DO is written into a shift register whose parallel output drives each segment of the sun.

In FIG. 1, two shift registers SR handle four digits each. Each SR requires 28 bits (7 bits x 4 digits). COM is the common digit voltage of the liquid crystal panel, CL
is a clock pulse for shifting SR.

Further, D is the final output of the final stage SR and is used for memory operation.

FIG. 2 shows periodic writing W to SR for COM, and CL occurs during this period.

The position of W with respect to COM may be at the beginning or end of COM, but if it is placed at the end, a latch is provided at each output of the shift register so that the write W is latched, so that the W information is not constant. can prevent half-lit display. Therefore, in FIG. 2, w is placed at the end of COM. Furthermore, by providing a latch, the width of W relative to COM can be increased to increase the amount of information to be written, or conversely, the frequency of CL can be lowered by the increased width of W to reduce current consumption. Figure 3 is a circuit diagram of the principle of memory operation. In memory mode, when M becomes 6H, the transmission gate, TG, switches from 2 to 3, and the shift register input passes through exclusive gate 1 instead of DATA. A closed loop is formed with the final output DI.

Then, the write period W is selected by the AND gate 5 and the OR gate 4, and the input exclusive gate 1
As a result, D is inverted, and alternating driving of the same display becomes possible. Furthermore, when no memory is used, DATA is input to the exclusive gate 1, lighting information is written in the opposite phase to COM, and non-lighting information is written in the same phase as COM. COM
The reason COM is used instead is that COM is inverted immediately after writing and holds half a cycle of display. AND gate 6 indicates that CL occurs during period W.

The principle of a display device in which a shift register and a liquid crystal panel are integrated has been explained above with reference to FIGS. 1 to 3, which are conventional examples.

Next, even if a write is attempted during a period other than a regular write W, the information written at the regular timing and stored in memory by this write will be reversed by the immediately following W within the same half cycle. After that, normal memory operations will result in an inverted pattern being displayed.

FIG. 4 is a circuit diagram of an embodiment of the present invention that solves this problem, and FIG. 5 shows the timing of FIG. 4.

X is an interrupt input that points to memory. When the signal be done. Signal C is summed with regular write signal W at OR gate 12 to form write signal B. At the same time, the output of FF8 becomes signal M, and the shift register becomes a memory operation. The reason why it is synchronized with φ is to prevent the write time from becoming indefinite due to random overlap with W. However, as it is, it is not possible to prevent the above-mentioned phenomenon in which the display becomes a reverse pattern, so it can be removed as follows.

First, the output of FF7 is clocked with φ and sent (all FFs are positive triggers).The output signal D of FF9 is sent to the next stage FF1.
Enter O. Next, the AND gate 14 multiplies the signal D by the FFLO, the inverted output signal E of the FFLO sent by W, and the signal M, to form the output signal A. The output signal A is inverted by the inverter 15 and the signal A
is formed. Write signal B is masked by signal A in AND gate 13 . In this way, the periodic write signal W, which is instructed by X and immediately after the memory operation is started by M, is removed once. As a result, information can be stored at any timing without creating a reversal pattern. In this way, write signal W/ is formed. Further, this arbitrary writing may overlap with regular writing. When FF9 overlaps with W and outputs X, FFIO operates immediately at the falling edge of the overlapped W to prevent mask output A from not being output. The W obtained in this way is used for actual writing. As described above, in the present invention, a non-regular write signal is supplied to the shift register in addition to the regular write, and when the non-regular write signal is generated, the supply of the regular write signal to the shift register is prohibited. Apart from regular writing, information can be written to the memory at any timing, and since writing is not performed twice during the same half cycle of the common digit voltage signal, the memory can be reversed and continued. Therefore, even if non-periodic information is included, the display can be displayed normally without changing to an inverted pattern.

[Brief explanation of the drawing]

1 to 3 are principle diagrams of the conventional example. 4 and 5 are examples of the present invention. SR...
・・Shift register, COM・・・・Common digit voltage,
W・・・・・・Regular writing period, Wζ・・・・・・
Write period according to the present invention, M... Memory signal, 2, 3... Transmission gate, 7
~10...D-type flip-flop.

Claims (1)

[Claims] 1. A liquid crystal is sandwiched between a segment electrode and a common electrode, and a means for supplying an alternating current signal that is inverted at regular intervals to the common electrode, and a periodic display within a regular writing period that occurs every half cycle of the alternating current signal. In a display device having a storage means that inverts and stores information every half cycle and supplies the displayed information to the segment electrodes, when an irregular information signal is generated, an irregular writing period outside the writing period occurs. means for supplying the non-periodic information signal to the storage means within a period of time; and means for stopping supply of the periodic display information to the storage means during the cycle of the AC signal in which the non-regular writing period occurs. A display device comprising: