JPS5944787B2 - MOS type ROM - Google Patents
MOS type ROMInfo
- Publication number
- JPS5944787B2 JPS5944787B2 JP57226187A JP22618782A JPS5944787B2 JP S5944787 B2 JPS5944787 B2 JP S5944787B2 JP 57226187 A JP57226187 A JP 57226187A JP 22618782 A JP22618782 A JP 22618782A JP S5944787 B2 JPS5944787 B2 JP S5944787B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- source
- gate
- fet
- drain regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は絶縁ゲート形半導体集積回路装置特にＭＯＳ型
のＲＯＭ（ＲｅａｄＯｎｌｙＭｅｍｏワ）に関す・る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate type semiconductor integrated circuit device, particularly a MOS type ROM (Read Only Memory).
ＲＯＭをＭＯＳ素子で構成するには、通常、１ビットＩ
ＦＥＴとし、ゲートの部分の酸化膜のうちＦＥＴとして
使用する領域を薄く、接続しない領域を厚くしておくこ
とにより、゛１’’、゛ｏ” 。To configure a ROM with MOS elements, usually one bit I
By making the oxide film on the gate part of the FET thinner in the region used as the FET and thicker in the non-connected region, ゛1'', ゛o'' can be achieved.
の区別をする方法が用いられる。たとえば、第１図に示
すようなＲＯＭの素子配列は、デバイス上では第２図に
示すような構成をもつている。A method is used to distinguish between For example, the element arrangement of a ROM as shown in FIG. 1 has a configuration as shown in FIG. 2 on the device.
ここではアルミニウムゲート構造のＭＯＳの場合が示さ
れており、アドレス１、２、３がアルミニウム層１１、
１２、１３で、また出力１、２、３が拡散層２１、２２
、２３でそれぞれ形成されている。なお、第２図中、３
１、３２は接地用の拡散層を示す。さて、斜線を施こし
た部分４１、４２、４３がＦＥＴとして使用するゲート
部分の薄い酸化膜の領域となる。すなわち、第３図に第
２図の■−■線に沿つた断面図を示すように、ｐ＋拡散
層２１、２２、２３、３１、３２が形成されたＮ型Ｓｉ
基板５上には酸化膜（ＳｉＯ２）６が形成されているが
、その膜６のうち上記ＦＥＴとして使用する部分４１、
４２のそれは１００ＯＡ程度と薄く、その他の部分のそ
れは、寄生ＭＯＳを防止するため、１μｍ程度と厚くそ
れぞれ形成されている。従つて、その酸化膜６の表面は
凹凸が激しく、それによる段差部分で上層のアルミニウ
ム層１２（１１、１３）が断線することがあり、また酸
化膜６が厚いため素子を小形化することが困難であつた
。そこで、本発明の目的は、上記Ｓｉ基板５上を覆う酸
化膜表面を平担化すると共にそれを薄くすることにより
、上記アルミニウム層１２（１１、１３）の断線を防止
すると共に素子の占有面積を小さくすることにある。Here, the case of a MOS with an aluminum gate structure is shown, and addresses 1, 2, and 3 are the aluminum layer 11,
12 and 13, and the outputs 1, 2, and 3 are the diffusion layers 21 and 22.
, 23, respectively. In addition, in Figure 2, 3
1 and 32 indicate diffusion layers for grounding. Now, the hatched areas 41, 42, and 43 are the thin oxide film regions of the gate portion used as the FET. That is, as shown in FIG. 3, which is a cross-sectional view taken along the line ■-■ in FIG.
An oxide film (SiO2) 6 is formed on the substrate 5, and a portion 41 of the film 6 to be used as the FET,
42 is as thin as about 100 OA, and the other parts are as thick as about 1 μm to prevent parasitic MOS. Therefore, the surface of the oxide film 6 is highly uneven, and the upper aluminum layer 12 (11, 13) may be disconnected at the stepped portion, and the oxide film 6 is thick, making it difficult to downsize the device. It was difficult. Therefore, an object of the present invention is to flatten the surface of the oxide film covering the Si substrate 5 and make it thinner, thereby preventing disconnection of the aluminum layer 12 (11, 13) and occupying an area of the device. The goal is to make it smaller.
以下、本発明の構成を図面を参照して具体的に説明する
。Hereinafter, the configuration of the present invention will be specifically explained with reference to the drawings.
第４図および第５図はそれぞれ上記第１図に示すＲＯＭ
を本発明により形成した場合の上面図およびそのＶ−Ｖ
線に沿つた断面図を示す。これらの図に示すように、本
発明では、Ｎ形Ｓｉ基板５上に熱拡散法により所定のｐ
＋拡散層２１、２２、２３、３１、３２を形成した後、
その上面を覆う酸化膜をすべてエッチングし除去して、
新たに１００ＯＡ程度（あるいはそれ以下）のゲート酸
化膜６’を形成する。そしてその酸化膜６’上からフォ
トレジストをマスクとして、第４図になし地伏に示す、
ＦＥＴを形成しない部分７にＮ形（基板５と同導電形）
の不純物イオンを打込む。なお、その後酸化膜６′上に
アルミニウム層１１，１２，１３を形成するのは、従来
と同様である。すなわち本発明では、ゲート酸化膜６′
を薄く形成することにより基板５上に多数のＦＥＴを形
成できるようにした後、ＦＥＴを形成する必要のない部
分７のゲート酸化膜６′下にＮ形不純物層を形成し、そ
れにより所定のＲＯＭを得る。なお、本発明はアルミニ
ウムゲート構造のＭＯＳのみならずシリコンゲート構造
等の他のＭＯＳにも適用できる。Figures 4 and 5 are the ROMs shown in Figure 1 above, respectively.
A top view when formed according to the present invention and its V-V
A cross-sectional view along the line is shown. As shown in these figures, in the present invention, a predetermined p
+ After forming the diffusion layers 21, 22, 23, 31, 32,
All the oxide film covering the top surface is etched and removed.
A new gate oxide film 6' of about 100 OA (or less) is formed. Then, using a photoresist as a mask from above the oxide film 6', as shown in FIG.
N type (same conductivity type as substrate 5) in portion 7 where no FET is formed
Implant impurity ions. Note that the formation of aluminum layers 11, 12, and 13 on the oxide film 6' is the same as in the conventional method. That is, in the present invention, the gate oxide film 6'
After making it possible to form a large number of FETs on the substrate 5 by forming the FET thinly, an N-type impurity layer is formed under the gate oxide film 6' in the portion 7 where no FET is required, thereby forming a predetermined area. Get ROM. Note that the present invention can be applied not only to MOSs with an aluminum gate structure but also to other MOSs such as a silicon gate structure.
上述のように、本発明に従つた絶縁ゲート形半導体集積
回路装置によれば、Ｓｉ基板５上のゲート酸化膜６′の
表面が平坦化するため、その上のアルミニウム層１１，
１２，１３の断線が防止でき、またＦＥＴを必要としな
い部分７のゲート酸化膜６′下にいわゆるチヤン不ルス
トツパ一が形成されるため、酸化膜６／および拡散マス
ク等を薄く形成でき、パターン加工を微細化できる。As described above, according to the insulated gate type semiconductor integrated circuit device according to the present invention, since the surface of the gate oxide film 6' on the Si substrate 5 is flattened, the aluminum layer 11,
12 and 13 can be prevented, and a so-called channel failure stopper is formed under the gate oxide film 6' in the portion 7 where the FET is not required, the oxide film 6/ and diffusion mask etc. can be formed thinly, and the pattern can be Processing can be miniaturized.
第１図はＲＯＭの素子配列の一例を示す図、第２図およ
び第３図はそれぞれ上記第１図のＲＯＭを構成した従来
装置の上面図およびその−線に沿つた断面図、第４図お
よび第５図は上記第１図のＲＯＭを本発明に従つて構成
した場合の上面図およびそのＶ−Ｖ線に沿つた断面図で
ある。
１１，１２，１３・・・アルミニウム層、２１，２２，
２３，３１，３２・・・Ｐ＋拡散層、４１，４２，４３
・・・ＦＥＴとして使用する部分の酸化膜、５・・・Ｎ
形Ｓｉ基板、６，６′・・・酸化膜、７・・・ＦＥＴを
形成する必要のない（チャンネルストツパ一を形成する
）部分。FIG. 1 is a diagram showing an example of the element arrangement of a ROM, FIGS. 2 and 3 are a top view and a cross-sectional view taken along the - line of a conventional device constituting the ROM shown in FIG. 1, respectively, and FIG. 4 5 is a top view and a sectional view taken along the line V-V of the ROM shown in FIG. 1 constructed according to the present invention. 11, 12, 13... aluminum layer, 21, 22,
23, 31, 32...P+ diffusion layer, 41, 42, 43
...Oxide film of the part used as FET, 5...N
type Si substrate, 6, 6'... oxide film, 7... portion where it is not necessary to form a FET (forming a channel stopper).
Claims (1)
、ドレイン領域と、上記ソース、ドレイン領域を横切る
列方向で上記半導体基板上にゲート絶縁膜を介して形成
されたゲート電極と、上記ソース、ドレイン領域及び上
記ゲート電極とで構成され行列状に配置された複数の絶
縁ゲート型電界効果トランジスタと、少くとも上記複数
の絶縁ゲート型電界効果トランジスタの１つはそのソー
ス、ドレイン領域間に上記基板と同一導電型の半導体一
領域を有し、かつこの半導体領域上にゲート電極が延在
していることを特徴とするＭＯＳ型ＲＯＭ。1 A pair of source and drain regions arranged in the row direction on the surface of the semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate insulating film in the column direction crossing the source and drain regions, and the source , a plurality of insulated gate field effect transistors arranged in rows and columns each including a drain region and the gate electrode, and at least one of the plurality of insulated gate field effect transistors has the above structure between its source and drain regions. A MOS type ROM characterized in that it has a semiconductor region of the same conductivity type as a substrate, and a gate electrode extends over this semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226187A JPS5944787B2 (en) | 1982-12-24 | 1982-12-24 | MOS type ROM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226187A JPS5944787B2 (en) | 1982-12-24 | 1982-12-24 | MOS type ROM |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50062898A Division JPS51139275A (en) | 1975-05-28 | 1975-05-28 | Method of manufacturing insulated gate type semi-conduceor integrated circuit means |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58116763A JPS58116763A (en) | 1983-07-12 |
| JPS5944787B2 true JPS5944787B2 (en) | 1984-11-01 |
Family
ID=16841245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57226187A Expired JPS5944787B2 (en) | 1982-12-24 | 1982-12-24 | MOS type ROM |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5944787B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6073259U (en) * | 1983-10-26 | 1985-05-23 | 三洋電機株式会社 | Dynamic ROM |
| JPS63131568A (en) * | 1986-11-21 | 1988-06-03 | Toshiba Corp | Semiconductor storage device |
| JPH0815186B2 (en) * | 1987-07-27 | 1996-02-14 | シャープ株式会社 | Semiconductor device |
| DE68910445T2 (en) * | 1988-09-01 | 1994-02-24 | Fujitsu Ltd | Integrated semiconductor circuit. |
-
1982
- 1982-12-24 JP JP57226187A patent/JPS5944787B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58116763A (en) | 1983-07-12 |
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